JPH04218100A - Pattern recognizing device - Google Patents

Abstract

PURPOSE:To effectively select a candidate at the time of executing rear-stage DP matching by selecting the candidate from the result of the fore-stage DP matching in two-stage DP matching with the pattern recognizing device which executes two-stage matching in a dynamic planning method. CONSTITUTION:This device has a candidate selecting means which selects plural pieces of the candidate standard pattern data by subjecting input pattern data to primary DP matching processing and selects the 1st and 2nd candidates from the data of the higher degrees of similarity therefrom, a means which announces a recognition failure if the distance between the 1st candidate and the input pattern data is above the 1st specific value, a means which determines the 1st candidate as the result of recognition when the distance between the 1st candidate and the 2nd candidate is above the 2nd specific value if the recognition failure is not judged and further, a means which determines the result of recognition by the secondary DP matching processing if the result of recognition is not determined. The primary DP matching processing is executed at the accuracy lower than the accuracy of the secondary DP matching processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recognition apparatus, and more particularly to a pattern recognition apparatus that selects candidates from the first-stage matching results of a recognition apparatus that performs two-stage matching in dynamic programming (hereinafter referred to as DP method).

0002

[Prior Art] Generally, character recognition devices, voice recognition devices, etc. extract characteristic parameters of input characters and voices.
It performs pattern matching with pre-stored patterns and selects and recognizes the one with the highest degree of similarity.

[0003] The frequency spectrum of the voice is often used as the voice characteristic parameter described above, and the spectrum is obtained by a method using a large number of bandpass filters or a fast Fourier transform. Then, as described above, the frequency spectrum of the audio obtained by these methods is compared with the pre-registered patterns, that is, the similarity with the standard pattern is determined, and the standard pattern closest to the input data is determined to be the input data. Output the result as .

[0004] When comparing the input data mentioned above with the registered patterns, there is not necessarily a one-to-one correspondence in the time axis between them, and changes may occur depending on the relationship between the words before and after the words or the length of long sounds. do. As described above, the DP method is a method of determining the similarity between patterns whose time axes etc. do not correspond one-to-one, that is, a pattern matching method (generally, the similarity between two patterns is expressed as a distance).

[0005] This DP method is applied not only to speech recognition but also to character recognition devices and the like. This DP method has the disadvantage that the calculation time increases as the number of feature points increases because the minimum distance between each feature point is determined over all. In order to compensate for the above-mentioned drawbacks of the DP method,
The following method is generally used. First, the pattern itself is linearly expanded or contracted, a preliminary selection is performed by linear matching, and a standard pattern with the minimum distance is determined using the DP method for the selected standard pattern.

[0006]

[Problems with the Prior Art] Since the processing speed of the linear matching method is faster than the DP method, the processing speed of the above-mentioned method is also faster than when the DP method is applied to all standard patterns. However, since this method linearly compresses the pattern, it has the drawback that the property of nonlinear compression on the time axis inherent in the DP method is weakened. Furthermore, the linear matching used for preliminary selection has the problem that it often misrecognizes words with long durations compared to the DP method, and may not be able to select the desired standard pattern in the preliminary selection. .

[0007]

[Object of the Invention] The present invention has been made in view of the above problems, and its purpose is to select candidates from the DP matching results of the first stage in two-stage DP matching, and to effectively select candidates when performing the second stage DP matching. An object of the present invention is to provide a pattern recognition device that performs the following steps.

[0008]

Summary of the Invention The present invention is characterized in that in a pattern recognition device that performs pattern matching between input pattern data and pre-stored standard pattern data to determine a recognition result, candidate selection means for selecting a plurality of candidate standard pattern data through a next DP matching process, and selecting those that are determined to have a higher degree of similarity as a first candidate and a second candidate; means for determining that the input pattern data is unrecognizable when it is determined that the distance between the input pattern data and the input pattern data is equal to or greater than a first specific value, and notifying that the input pattern data is unrecognizable; means for determining the first candidate as a recognition result when it is determined that the distance between the first candidate and the second candidate is equal to or greater than a second specific value; and a recognition result determined by the means. and means for determining a recognition result by performing a second DP matching process from among the plurality of candidate standard pattern data selected by the candidate selection means when the candidate standard pattern data is not selected by the first DP matching process. The pattern recognition apparatus is characterized in that the second matching process is performed with a coarser accuracy than the second matching process.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention using a processor. Microphone 1 is connected to BPF circuit 3 via AGC circuit 2. The output of the BPF circuit 3 is then applied to the A/D converter 4. Processor (
The bus line 7 connected to the CPU) 6 has the aforementioned A/
Read only memory (ROM) 8 in addition to D converter 4
, random access memory (RAM) 9, and input/output control system (IOCS) 10 are connected. The input/output control system (IOCS) 10 is connected to other devices such as a personal computer 11. The sound entering the microphone 1 is converted into an audio signal, that is, an electrical signal. The level of this electrical signal varies depending on the volume of the person's speaking voice or the distance between the speaker's mouth and the microphone, so the AG
Input to C circuit 2. The AGC circuit is a circuit whose gain changes so that its output remains approximately constant. The output of the AGC circuit 2, that is, the audio signal at a constant level, is applied to the BPF circuit 3. The BPF circuit 3 has a plurality of band pass filters so as to divide the audio band into 8, for example, and this BPF
The circuit 3 divides the signal into eight specific bands. 8 by band
The divided audio signals are applied to the A/D converter 4, which converts, for example, the power of the audio signals in each band into digital quantities. Since the A/D converter 4 converts one band, that is, one channel, of the output of the BPF circuit 3 into 8-bit data, a total of 64-bit data is output to the bus line 7 in units of 8 bits, for example. The aforementioned A/D converter 4 is controlled by a processor (CPU) 6 via a bus line 7, and the aforementioned 64-bit data is divided into channels and stored in a random access memory (RAM).
9 is stored.

In addition to controlling the A/D converter 4 and storing data, the processor (CPU) 6 also performs calculation processing in the DP method, that is, DP operation, and the personal computer 1
1. Input/output control system (IOCS) 1
Controls output via 0. These calculations and controls are performed by a processor (CPU) 6 executing a program stored in a read-only memory (ROM) 8 in advance. and random access memory (RA)
M) 9 is also used as a work area at that time.

FIG. 2 is a flowchart for explaining the above-mentioned DP calculation process. When data is input from the A/D converter 4, DP calculation processing starts 12, and first, a pre-stage DP calculation 13 is performed. This pre-stage DP calculation 13 is for finding the distance from standard data stored in the random access memory (RAM) 9 in advance. However, this operation is not performed for all input data, but for specific data intervals, for example, 3 out of 3 input data.
Do it once a time. Note that one measurement data consists of 64 bits in total as described above. When all the audio data of one word, for example, has been input for a specific time and all the corresponding calculations have been completed, the next candidate selection process 14 is executed. The first-stage DP operation 13 executed earlier is a DP operation performed on input data once out of three times, and the operation naturally lacks reliability. For this purpose, selection processing is performed to perform the DP calculation again on standard pattern data whose distance results fall within a specific range. This selection process is candidate selection process 14.
It is. However, if the distance of only one standard pattern data is within the predetermined distance by the previous stage DP calculation 13, the DP calculation is not performed again, and the standard pattern is determined to be the input data 15, and as shown in FIG. The data is output to a personal computer 11 via an input/output control system (IOCS) 10 shown in FIG. Further, if there is no object within a predetermined distance, the input data is deemed to be unrecognizable and invalid 16. Furthermore, if the calculation results using multiple standard patterns are within the above-mentioned specific distance and the difference in distance from the first candidate is within a specific range, the patterns from the minimum distance to, for example, the fifth one are Select as a candidate. Note that if the difference in distance from the first candidate falls within the specific range of five or less, only that number of objects are selected as candidates. Once a candidate is determined, the candidate selection process 14 is ended, and the next subsequent stage DP calculation 17 is executed. In the first stage DP calculation 13, the standard pattern data arranged according to the input data and time are calculated once every three times.
However, the subsequent DP calculation 17 calculates the minimum distance for all data of each of the selected standard pattern data. Then, corresponding to each selected standard pattern data, the standard pattern having the smallest value among the minimum distances is determined to match the input data (15) and is output.

FIG. 3 is a flow chart showing the aforementioned candidate selection process 14 in more detail. After a 14-1 start,
First, the minimum distance D(1) with respect to the standard pattern is detected and compared 14-2 with a first specific value Drej. That is, D(1) is subtracted by Drej to determine whether there is a carry or not. D(1)≧Dre without carry
In the case of j(Y), it is set as invalid 16. This means that in the first stage DP calculation, there is a high possibility that the target standard pattern does not exist even if the second stage DP calculation is performed because the distance is too far, and the first specific value Drej is
This is the threshold value. D with carry (1
)<Drej(N), then the second minimum distance D
It is determined 14-3 whether the difference value with (2) is greater than or equal to the second specific value Ddec. The processing in the first stage DP calculation has a larger error than the processing in the second stage DP calculation, but the first
If the difference between the candidate, that is, the standard pattern of the distance of D(1), and the second candidate, that is, the standard pattern of the distance of D(2) is greater than or equal to the second specific value Ddec, the subsequent calculation process is performed. However, there is no change in the ranking of candidates. As a result, if the difference is greater than or equal to the second specific value, the first candidate is determined to be a match (15). That is, it is determined that (D(2)-D(1))≧Ddec is satisfied (Y).

If the above-mentioned difference is small, it is within the error range in the previous stage processing, so the first to fifth candidates are selected 14-
4. That is, a candidate D(n) whose difference from the first candidate's minimum distance D(1) is smaller than the third specific value DDP is determined. Then, the first to fifth candidates are selected. In other words, the difference from the first candidate is the third specific value DDP
Select the fifth standard pattern from the minimum value among the following standard patterns. When the aforementioned selection process 14-4 ends, the candidate selection process 14 ends 14-5.

In FIG. 2, it is the latter stage DP calculation 17 that is performed on all the data corresponding to the time of the standard pattern, and since there are a maximum of five standard patterns at that time, this calculation time is the same for all the standard patterns. It is much faster than calculations performed by For example, if there are 64 standard patterns, the number can be shortened to 5/64 at the maximum. Furthermore, since the pre-stage DP calculation is performed once every three times, the calculation processing is much less than when it is performed on all data of one standard pattern.

Furthermore, after selecting candidates, there are cases where the number of candidates becomes less than 5, or even when they are determined, and the processing time is much faster than when all DP calculations are performed. .

FIG. 4 is a circuit diagram of a second embodiment of the present invention. Although the embodiment of the present invention shown in FIG. 1 performs calculations and controls thereof in a processor, the embodiment shown in FIG. 4 is entirely controlled by a circuit, and furthermore, calculations are also performed by a circuit. The A/D converter 18 has a BPF shown in FIG.
The output of the circuit 3 is added, and the output is inputted to the level detection section 21 and the input pattern memory 20 via the parameter normalization compression section 19. The detection output of the level detection section 21 is applied to the timing control section 22. and timing control section 2
The control output No. 2 is input to the A/D converter 18, the parameter normalization compression section 19, the frame counter 23, and the control section 24. The input pattern memory 20, the standard pattern memory 25, the work area memory 26, and the minimum distance memory 27 are supplied with the address output from the control section 24.

The distance calculation section 28 includes an input pattern memory 2.
0, the output of the standard pattern memory 25 is added, and the output is input to the work area memory 26 via the partial sum calculation section 29. The output of the work area memory 26 is applied to a partial sum calculation section 29 and a minimum distance calculation section 30. In addition to this, the minimum distance calculation section 30 receives the output of the standard pattern frame length memory 31 and the output of the frame counter 23 via the gate circuit 32, as well as the gate circuit 33 and the frame number correction section 3.
Join via 4. The output terminal of the minimum distance calculation section 30 is connected to the input terminal of the minimum distance memory 27, and the output terminal of the minimum distance memory 27 is connected to the input terminal of the candidate selection section 35. The output of the candidate selection section 35 is stored in the candidate number memory 3.
6 and the control section 24. Then, it is further output as a decision result 37. Candidate number memory 36 is connected to control section 24 . The control output of the control section 24 is applied to a distance calculation section 28, a partial sum calculation section 29, a minimum distance calculation section 30, a standard pattern frame length memory 31, and a candidate selection section 35. Furthermore, a control signal is input from the control section 24 to the control terminal of the gate circuit 32 and to the control terminal of the gate circuit 33 via the inverter 38 . Note that A in the figure is a symbol indicating that the devices are connected.

Each band-divided signal applied to the A/D converter 18 is converted into a digital quantity and input to a parameter normalization compression section 19. The parameter normalization compression unit 19 normalizes the input data with a value of the maximum value + 1, converts it to the number of bits required for processing, that is, cuts the data below the effective number of bits. Also, when the maximum value is less than a certain value,
Normalize the input data with a specific value and convert it to the number of bits required for processing in the same way as described above. The data thus converted into a specific number of bits is stored in the input pattern memory 20. The level detection unit 21 detects whether the data processed by the parameter normalization compression unit 19 described above is equal to or higher than a specific value, that is, a threshold level TH. The timing control unit 22 controls the operation of switching the timing signal based on the result obtained by the level detection unit 21.
will do. This is done in order to quickly detect the start of the voice section TS when the A/D converter 18 and the parameter normalization compression section 19 operate. As a result, when the input parameter, that is, data Da, is below the threshold level TH, the A/D converter 18 and the A/D converter 18 and The parameter normalization compression unit 19 operates. The data obtained by the above-described operation is stored in the input pattern memory 20 during the voice section TS. Similar to the processing of the processing device using the processor of FIG. 1 described above, the first stage D
The P operation and the subsequent DP operation are performed in the same circuit in the circuit of the embodiment of the present invention shown in FIG. The control of the control unit 24 determines whether the DP calculation is the first stage DP calculation or the second stage DP calculation. That is, the first-stage DP calculation and the second-stage DP calculation differ only in access to the input pattern memory 20, standard pattern memory 25, and work area memory 26, and the distance calculation unit 28, which is related to the DP calculation,
The partial sum calculation section 29 and the minimum distance calculation section 30 operate in exactly the same way. As mentioned in the explanation of Figure 1, the difference is that instead of performing DP calculation on all data,
This means that one out of every three operations is performed by the control unit 24.
The only difference is the address value of each memory generated.

The distance calculation unit 28, the partial sum calculation unit 29, and the minimum distance calculation unit 30 are circuit units related to the DP calculation, as described above. First, the DP calculation will be explained using equations. Input pattern |A|, standard pattern |B|, respectively |
A|=|A|1 , |A|2 , ... |A|j
...(1) |B|=|B|1 , |B|2 , ...
|B|i ... (2). ｜A｜1 ~｜A
|j, |B|1 to |B|i are feature vectors at a certain time. This feature vector at a certain time is, for example, an eight-dimensional feature vector (dividing the audio band into eight) in the embodiment of the present invention, and |A|j = (aj1
, aj2, ... aj8) ... (3
) | B | j = (bi1, bi2, ... bi8)
...It is expressed as (4).

The partial sum g(i,j) in DP operation is generally

[0021]

[Math 1]

It is expressed as: Here, d(i,j) is the distance between each feature vector,

[0023]

[Math 2]

It is defined as: Further, dw is the window width on one side, and if the window width is W, then W=2dW+1. The above-mentioned equation (5) is an equation expressing a partial sum in the DP calculation, and the inter-pattern distance is obtained by g(I, J). On the other hand, in the case of voice recognition and the like, input pattern data and standard pattern data each have different input times. That is, (1)
Since I and J in equation (2) are not constant, they must be normalized by the number of samples. In the embodiment of the present invention, the number of samples differs between the input pattern data and the standard pattern data, so the final inter-pattern distance G
(I, J) is

[0025]

[Math 3]

[0026] On the other hand, in the embodiment of the present invention shown in FIG. 4, calculations are performed by converting variables. That is, i=
m+j-dw-1
...(7) However, 1≦m≦wl=j

...(8) l'=j-1
...(9)
Calculations are performed using equations related to m, l, and l'. Substituting equations (7) to (9) into equations (5) and (6) and converting, e(dw+1,1)=2d(1,1)
...(10)

[0027]

[Math 4]

[0028] And the final inter-pattern distance E(M,L) after conversion is

[0029]

[Math 5]

[0030] However, M=I-J+dw+1
...(13) L=J

... is expressed as (14).

In formula (10)', m≠dw+1,1
When ≦m≦w, e(m, 1) is assumed to be infinite. This will be described later, but in order to store the minimum value of equation (11) in the memory, the maximum value is stored in the memory at the same time as or before the calculation of equation (10).

The description of FIG. 4 will be continued further. The distance calculation unit 28 is a circuit that calculates the distance d(i, j) between the aforementioned feature vectors. That is, the input pattern memory 20
and each data input from the standard pattern memory 25 (
5) Calculate the expression '. Then, the calculation result is output to the partial sum calculation section 29. The partial sum calculation unit 29 is the distance calculation unit 2
The calculations of equations (10) and (11) are performed using the calculation results obtained from step 8 and the data obtained from work area memory 26.

The first-stage DP calculation is performed on one out of three input data, ie, each of the above-mentioned feature vectors. That is, the input data |A|1 , |A|4 ・
...|A| Calculate only regarding 3P+1. Similarly, standard pattern data is also extracted from the standard pattern memory 25 at a rate of one in three pieces |B|1, |B|4...|B|3P'
+1 is read out and used for calculation.

Note that all data are used in the subsequent DP calculation. The minimum distance calculation unit 30 is a circuit that operates after the end of the voice section, which will be described later. This minimum distance calculation unit 30
calculates the minimum value of each standard pattern data from the distance data in the work area 26. That is, this is a circuit for determining E(M,L) of the above-mentioned equation (12).

First, M that satisfies the above equations (13) and (14)
, L corresponding to e(M,L) is stored in the work area memory 26.
Seek more. Furthermore, standard pattern frame length memory 31
The I output from the frame counter 23 and the data J output from the frame counter 23 are added, and e(M, L) is divided by the result. Then, the result is stored in the minimum distance memory 27. However, in the case of pre-processing, the frame length of the input pattern and standard pattern is approximately one third, but since I and J are integers and are not necessarily divisible by 3, this is
, when J is a multiple of 3, (I/3) + 1, (J/3) + 1, and when I and J are multiples of 3 plus 1, {(I-1)/3}
+1, {(J-1)/3}+1, and when I and J are multiples of 3 plus 2, {(I-2)/3}+1, {(J-2)/
3}+1 is output from the standard pattern length memory 31 and the frame number correction unit 34.

In this way, I/3 and J/3 are in the case of pre-processing, and in the case of post-processing, I is obtained from the standard pattern frame length memory 31 and J is obtained from the frame counter 23 via the gate. is input.

[0037]

[Math 6]

##EQU1## is calculated. The candidate selection unit 35 further finds the one having the minimum value from among the minimum distances for each standard pattern data stored in the minimum distance memory 27,
Pattern numbers (1 to n) corresponding to the standard pattern data are stored in the candidate number memory 36. Candidate selection section 35
Similar to the two-stage DP operation using the processor described above,
The operation of storing in the candidate number memory 36 differs depending on the conditions. If the distance of only one standard pattern data is within a predetermined distance according to the pre-stage DP calculation 13, the determination result, for example, the pattern number, is output to the terminal 37 as a determination. Further, this result is output to the input/output control system (IOCS) 10 via the control unit 24. At this time, the control unit 24 waits for the next input pattern data to be input without controlling the subsequent DP calculation process. If there is no object within a predetermined distance, the input data is determined to be unrecognizable and output to the control unit 24. In this case as well, the control unit 24 outputs to the input/output control system (IOCS) 10 that recognition is not possible. Furthermore, if calculation results using multiple standard patterns are found within the above-mentioned specific distance, and the difference in distance from the first candidate falls within a specific range, the pattern with the smallest distance, for example, up to the fifth one is selected as a candidate. Select. Note that if only five or fewer objects fall within the specific range, or furthermore, if the difference in distance from the first candidate does not fall within the specific range, only that number of objects are selected as candidates. That is, in this case, two to five numbers are stored in the candidate number memory 36. In addition, the candidate number memory 36
The number is stored only when the pre-processing is performed, and in the post-processing, the candidate selection section detects the minimum value and then outputs the number (1 to n) to the control section 24.

The aforementioned distance calculation unit 28 and partial sum calculation unit 29
, the minimum distance calculation section 30, and the candidate selection section 35 are used in common in the case of the first-stage DP calculation and the second-stage DP calculation, respectively.

As described above, the level detection unit 21 is a circuit that determines whether the level of the parameter normalization compression unit 19, that is, the parameter Da, is equal to or higher than a specific value (threshold level TH). T.H.
With the above detection, the clock TPS changes to TS to start the DP calculation process, but if it is detected during the calculation process, it becomes a signal that causes the candidate to be saved. The timing control section 22 is a circuit that controls these timings.

FIG. 5 is a circuit diagram of the timing control section 22. As shown in FIG. The detection signal from the level detection section 21 is passed through the set terminal S of the flip-flop 40, the reset terminal R of the counter 51, and the inverter 41 to the AND gates 42, 43.
join the gate. The output Q of the flip-flop 40 is connected to the gate of an AND gate 47 via the gates of AND gates 44 and 45 and an inverter 46. Clock outputs TS and TPS of the timing generator 48 are input to an OR gate 49 via AND gates 45 and 47. The output of the OR gate 49 is connected to the A/D converter 4 and the parameter normalization compression section 19. The output TS' of the AND gate 45 is the input of the ternary counter 50 and the AND gate 4.
Join gate 2,44. The output of the AND gate 44 is connected to the frame counter 23. and gate 42
The output of the counter 51 is added to the counter 51, and the output of the counter 51 is
O. The 7 output is applied to the reset terminal R of the flip-flop 40 and is output to the control section 24 as a terminal output. Clock output of timing generator, AND gate 43
The output of the flip-flop 40 and the output Q of the flip-flop 40 are applied to the control section 24. Counter 50 NO. The two outputs are connected to the timing generator 48 and the AND gate 43.

FIG. 6 is a timing chart diagram of the timing control section 22. The operation of the timing control section 22 will be explained below using FIG. When the flip-flop 40 is in the reset state, its output Q is at a low level (L level), so the AND gates 44 and 45 are turned off. However, since that signal is applied to the inverter 46, the output of the inverter 46 becomes high level (H level). Since the output of the inverter 46 is applied to the AND gate 47, the AND gate 47 is turned on and the clock TPS generated by the timing generator 48 is outputted via the AND gate 47 and the OR gate 49. The clock TPS' in FIG. 6 is a signal indicating the output of the AND gate 47. When the parameter Da becomes higher than the threshold level TH, the output of the level detector 21 becomes H level, setting the flip-flop 40 and resetting the counter 51. As a result, the output of the flip-flop 40 becomes H level, and the count value of the counter 51 becomes 0. When the output of the flip-flop 40 becomes H level, the AND gate 47 is turned off and the AND gates 44 and 45 are turned on. As a result, the clock TS generated by the timing generator 48 is changed to the AND gate 4.
5. Output via OR gate 49. or gate 4
Since the output of 9 is applied to each clock terminal of the A/D converter 18 and the parameter normalization compression section 19, the timing is TPS below the threshold level, and TS above the threshold level. For example, T.S.
If the relationship between the clock frequency and the TPS clock frequency is set to 1:3, the low level is read out with a clock three times the TS, and when it exceeds the threshold level, it is sampled with the TS clock and taken in as data for DP calculation. . Since the output of the AND gate 45, that is, the clock TS' is also applied to the counter 50, the output of the counter 50, that is, the clock TS' is 1 because the counter 50 is a ternary counter.
The signal frequency-divided by /3 is inverted via the timing generator 48 and applied to the controller 24 as a TFDP signal. The TFDP signal serves as a clock for the circuit shown in FIG. 3 to perform the DP calculation at that timing. Furthermore, since the AND gate 44 is also turned on, the clock TS' is output.
It is added to the frame counter 23. Furthermore, since the output Q of the flip-flop 40 is applied to the start end signal terminal of the control section 24, the control section 24 starts controlling the previous stage DP calculation when the flip-flop 40 becomes H level.

[0043] On the other hand, the signal level of audio signals etc. may drop temporarily. For example, the sound "tsu" as in Gakkou (school) is a boring sound, and its level as a voice has decreased. However, if this is taken as the end point, erroneous recognition will occur, so recognition is performed by detecting a decrease in the level at a specific time. The counter 51 detects this specific time. When the flip-flop 40 is set and the level detection section 21 becomes low level, the reset of the counter 51 is canceled, and the H level is applied via the inverter 41, and the AND gate 42 is turned on. As a result, the clock generated by the AND gate 45 is applied to the counter 51 via the AND gate 42. The counter 51 is an octal counter, and when seven clocks are input after the reset is released, the counter 51 is an octal counter. 7 output is H
level. The level detection unit 21 is activated again before 7 clocks.
When becomes H level, the counter 51 is reset. Then, when the signal inputted from the level detection section 21 becomes L level, the same operation is repeated again. When the counter 51 counts 7 clocks, NO. 7 output becomes H level, the flip-flop 40 is reset and becomes the initial state. No. of counter 51. 7 output is control part 2
The control unit 24 performs the subsequent DP calculation. On the other hand, since the signal from the level detector 21 is also applied to the gate 43 via the inverter 41, when the signal from the level detector 21 becomes L level, the gate 43
3 is added with an H level, and the output of the counter 50 is applied to the control section 24 as a save signal.

The save signal, that is, the output signal of the AND gate 43, is outputted to the control section 24 in synchronization with the output of the counter 50 when the level detection section 21 is in the L state. The control unit 24 then saves the candidates. Saving refers to reading data from the partial sum operation result in the DP operation stored in the work area memory 26, and performing the final calculation in the minimum distance calculation unit 30 for the number of standard patterns (1 to n), and saving the data to the minimum distance memory 2.
7, the candidate selecting unit 35 determines the candidate, and stores the candidate number in the candidate number memory 36. This evacuation is performed after the output of the level detection section 21 becomes L level.
It is also possible to perform this after the clock (TS'). However, by performing this saving during the L level detection period, that is, the aforementioned 7 clock period, it becomes possible to execute the subsequent DP calculation at the same time as the termination determination is made, so in the embodiment of the present invention, the entire processing time is becomes even shorter.

In the timing chart shown in FIG. 6, a temporary level drop is detected in the audio area and evacuation is performed, but since the subsequent level becomes H level,
The pre-stage DP calculation process is executed again. And silent section T
At Sn, candidates are saved again, the end is detected at the 7th clock, and the candidate is determined. The aforementioned speech section TS and silent section TSn are the first-stage DP calculation, and the second-stage DP calculation is performed between candidate determination and word determination. This section becomes the word determination section TJ. The clocks TBDP and TFDP are the clocks for the front-stage and rear-stage DP calculations, and the control unit 24 controls each calculation unit in synchronization with these clocks. Returning to FIG. 4, further explanation will be provided. A clock generated by the timing control section 22 and input to the frame counter 23 is counted by the frame counter 23. This counter 23
The number of frames of input pattern data is determined by: The output of the frame counter 23 is the gate circuit 32, 33
join. Since the output signal of the control section 24 is applied to the control terminal of the gate 33 via the control terminal of the gate 32 and the inverter 38, one of the gates 32 and 33 is always on. In the case of the pre-stage DP calculation, the L level is output from the control unit 24, so the gate 33 is turned on and the output of the frame counter 23 is applied to the frame number correction unit 34 via the gate 33. As mentioned above, the frame number correction unit 34 adjusts the value of the frame counter by approximately 1/
3, and when the input J is 3U (U is an integer),
(J/3)+1 is output, when input J is 3U+1 {(J-
1)/3}+1 is output, when input J is 3U+2 {(J-
2)/3}+1 is output. This output is used in the minimum distance calculation section 30 in the pre-stage DP calculation. on the other hand,
During the subsequent DP calculation, the gate 32 is turned on and the gate 33 is turned off, and the output J of the frame counter is directly applied to the minimum distance calculating section 30.

In addition, the standard pattern frame length memory 31
As described above, the control unit 24 controls whether the calculation is the first-stage DP calculation or the second-stage DP calculation, and the minimum distance calculation unit 30 stores a value related to the number of frames I of each standard pattern corresponding to it, that is, In the first stage DP operation, when I is 3U'(U' is an integer), (I/3) + 1, I is 3U'
+1, outputs {(I-1)/3}+1, when I is 3U'+2, outputs (I-2)/3+1, and outputs I during subsequent DP calculation.
Output as is. In addition, I is the standard pattern memory 25
It changes in accordance with the standard pattern data (1 to n) stored in .

FIG. 7 is a circuit diagram showing the candidate selection section 35 in FIG. 4 in detail. The output of the minimum distance memory 27 is input to the minimum value selection section 35-1. Minimum value selection section 35-
The first output of 1 is connected to the input of candidate memory 35-2, and the second output is output as a decision signal during subsequent DP calculation.
-3. An address counter 35 that counts signals from the control 27 is used to input the address of the candidate memory 35-2.
-4 output is added. The output of the candidate memory 35-2 is then applied to the latch 35-5, the first input of the comparison circuit 35-6, and the first input of the selection circuit 35-7. Latch 35-5
The output of is connected to the input of the comparison circuit 35-8, the second input of the comparison circuit 35-6, and the second input of the selection circuit 35-7. The comparison output of the comparison circuit 35-6 is input to the selection circuit 35-7 and is also applied to the control section 24. Furthermore, the decision output is input to the control unit 24 as a decision in the candidate selection process 14, and is also output as a decision 35-3'. The output of the selection circuit 35-7 is input to the candidate number memory 36. The comparison circuits 35-8, 35-6 and the selection circuit 35-7 include the first to
Data of the third specific values Drej, Ddec, and DDP are added, respectively.

Signal B applied to address counter 35-4
, the minimum value selection section 35-1 and the selection circuit 35-7 are supplied with the control signal B' and the above-mentioned first to third specific values Drej, Dde.
c, DDP data is data added from the control unit 24. The minimum value selection unit 35-1 compares the minimum distance data sequentially input from the minimum distance memory 27 with the data stored in the candidate memory 35-2. The candidate memory 35-2 is a memory that stores the fifth minimum distance data. Then, the stored data and the input data are selected by the minimum value selection unit 3.
5-1 compares in descending order, and if the data input from the minimum distance memory 27 is data of the corresponding rank, stores the data and its candidate number in the position of the corresponding rank;
Data for subsequent rankings is sequentially shifted. That is,
For example, B2, B7, B1, B8, and B4 are ranked higher than those whose minimum distance data of the standard pattern has a smaller value, and are ranked third than those whose minimum distance data B9 of the standard pattern input from the minimum distance memory 27 has a smaller value. If so, B9 is stored in the B1 position, and B1, B8
then shift. In other words, the result is B2
, B7, B9, B1, B8. In this way, by performing a size comparison process on the minimum distance data for all standard pattern data, the values (D(1) to D(5)) from smallest to smallest distance data are The number is stored in candidate memory 35-2. That is, the first to fifth candidates are unconditionally selected and stored. These operations are controlled by control signals B and B' input from the control section 24.

Next, the minimum distance data of the minimum value, that is, the first
Candidate D(1) is output from candidate memory 35-2 and stored in latch circuit 35-5. Then, the comparison circuit 35-
8 and the first candidate is the above-mentioned first specific value Drej
(Step 14-2 in FIG. 3). First candidate D
If (1) is greater than or equal to the first specific value Drej, an invalidation signal is output to the control unit 24 and it is determined to be invalid. In addition, if the value of the first candidate is smaller than the first specific value, a valid signal is output to the control unit 24, so that step 14 in FIG.
As indicated by -3, the address counter 35-4 is incremented by the control signal B of the control unit 24, and the candidate memory 3 stores the minimum distance data D(2) of the second candidate.
5-2, the minimum distance data D(2) of the second candidate from the candidate memory 35-2 is stored in the first
Participate in input. Comparison circuit 35-6 is shown in step 1 of FIG.
As shown in 4-3, this circuit calculates the difference between the data applied to the first input and the data applied to the second input, and determines whether the difference is smaller than the second specific value Ddec. It operates based on the output of the comparison circuit 35-8. That is, the second input of the comparison circuit 35-6 is connected to the latch 35 described above.
Since the first candidate data D(1) stored in -5 is added, the difference is calculated and compared with the second specific value Ddec. As a result, if the difference value is greater than or equal to the second specific value Ddec, a decision signal and a decision number are output to the control unit 24 as a standard pattern aiming at the first candidate (step 14-3 in FIG. 3). Note that the selection circuit 35-7 does not operate at this time. Moreover, contrary to the above, if the difference value is smaller than the second specific value Ddec, there is a possibility that other candidates exist in addition to the first candidate, so the operation signal that selects them is selected. Output to circuit 35-7. Selection circuit 35
-7 is a circuit that performs selection as shown in step 14-4 in FIG. - This is a circuit for selecting the fifth candidate. Although the first to fifth candidates are selected in the minimum value selection unit 35-1,
The selection by the minimum value selection unit 35-1 does not require a difference from the first candidate data. The selection circuit determines this difference and determines whether the difference is smaller than the third specific value DDP. That is, the difference between the signal D(n) applied to the first input and the signal D(1) applied to the second input is calculated, and if the difference value is smaller than the third specific value DDP, that candidate number is selected as the candidate. Output to number memory 36. When the operation start signal of the selection circuit 35-7 is inputted from the comparison circuit 35-6, the selection circuit starts the above-described operation.

This circuit starts operating when the third candidate data is input to the first input, and the candidate numbers of the first and second candidates are empty before starting this operation. The conditions are sequentially output to the candidate number memory via the selection circuit 35-7. That is, D(2)- in the comparison circuit 35-6
When it is determined that D(1)<Ddec (Figure 3 Step 1
4-3) Output and store the first and second candidate numbers in the candidate number memory, respectively. The selection circuit repeats the above-described discrimination operation sequentially starting from the third candidate data, and when the difference becomes larger than the third specific value DDP, the selection circuit selects the candidate number memory 36.
The candidate number will no longer be output. Candidate number memory 36
A maximum of 5 candidate numbers are stored in , but the number changes from 2 to 5 depending on the determination operation of the selection circuit.

Although a voice recognition device is used in the embodiment of the present invention described above, the present invention is not limited to this. For example, it can be applied to anything that recognizes patterns, such as a character recognition device.

[0052]

[Effects of the Invention] As described above, the present invention performs DP calculation in two stages, the front and rear stages are processes for selecting candidates, and the latter stage is a process for selecting candidates obtained in the first stage with high precision. This is a process of detecting a target pattern. The first stage does not process all data, but performs one distance calculation for, for example, three measurement points, so its processing speed is fast and it does not require a large amount of work memory. Similarly, in the latter stage, D is applied only to a specific number of candidates.
Since P calculation is performed, a large amount of memory is not required and the processing time is short.

According to the present invention, the target standard pattern is determined based on the result of the previous stage DP matching, or
Since ~5 candidates are selected and the subsequent DP calculation is performed, the average processing time becomes faster.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a first embodiment of the present invention using a processor.

FIG. 2 is a flowchart diagram illustrating DP calculation processing.

FIG. 3 is a flowchart diagram showing further details of candidate selection processing 14 according to the embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a timing control section.

FIG. 6 is a timing chart diagram of a timing control section.

FIG. 7 is a detailed circuit diagram of the candidate selection unit 35 according to the embodiment of the present invention.

[Explanation of symbols]

1 Microphone 2 AGC circuit 3 BPF circuit 4, 18 A/D converter 6 Processor 8 Read only memory 9 Random access memory 10
Input/output control system 13 Front stage DP calculation 14
Candidate selection processing 15 Post-stage DP calculation 19 Parameter normalization compression unit 20 Input pattern memory 21
Level detection section 22 Timing control section 23 Frame counter 24 Control section 25 Standard pattern memory 26 Work area memory 27 Minimum distance memory 2
8 distance calculation unit 29 partial sum calculation unit 30 minimum distance calculation unit 31 standard pattern frame length memory 32,
33 Gate circuit 34 Frame number correction section 35
Candidate selection section 36 Candidate number memories 50, 51 Counter 35-1 Minimum value selection section 35-2 Candidate memory 35-4 Address counter 35-5 Latch 35-6
, 35-8 Comparison circuit 35-7 Selection circuit

Claims (1)

[Claims] 1. A pattern recognition device that determines a recognition result by performing pattern matching between input pattern data and pre-stored standard pattern data, wherein a plurality of candidates are determined by a primary DP matching process on the input pattern data. Select the standard pattern data, and select the first candidate and the second candidate from among those that are judged to have a higher degree of similarity.
and means for determining that the first candidate is unrecognizable when it is determined that the distance between the first candidate and the input pattern data is equal to or greater than a first specific value, and notifying that the input pattern data is unrecognizable. , in the case where it is not determined that the first candidate is unrecognizable by the means, and the distance between the first candidate and the second candidate is determined to be greater than or equal to a second specific value, the first candidate is recognized. means for determining a result, and when a recognition result is not determined by the means, determining a recognition result from a plurality of candidate standard pattern data selected by the candidate selection means by a second DP matching process; A pattern recognition device comprising means for performing the first DP matching process with a coarser accuracy than the second matching process.