JPH04216287A - Luminance signal/chrominance signal separator - Google Patents

Abstract

PURPOSE:To reduce dot interference to appear at a luminance signal output by adaptively switching whether the interdigital characteristic part of the luminance signal output is set to all the bands or to a BPF band. CONSTITUTION:At a first arithmetic circuit 7, signals D-F are inputted and a chrominance signal output G is outputted corresponding to a control signal showing the chrominance signal output outputted from a first selector circuit 6. At a second selector circuit 8, signals A, C-F are inputted and as the luminance signal output, one of two signals B-G and (B+A)/2 is selected corresponding to the relation of the input signals. Then, a control signal showing the selected luminance signal is outputted. At a second arithmetic circuit 9, signals A, B and G are inputted and as the luminance signal output, any one of the signals B-A and (B+A)/2 is outputted corresponding to the control signal outputted from the second selector circuit 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a luminance signal/chrominance signal separation (hereinafter referred to as Y/C separation) device used in a video tape recorder (hereinafter referred to as VTR).

0002

2. Description of the Related Art In recent years, there has been an increasing demand for higher image quality in consumer VTR equipment, and the importance of Y/C separation devices built into VTR equipment has increased.

[0003] A conventional Y/C separation device will be explained below. FIG. 3 shows an example of a conventional Y/C separation device.

As shown in the figure, a first delay circuit 1 and a second delay circuit 2 having a delay period of one horizontal scanning period are used, and a first band-pass filter 3 (hereinafter referred to as (abbreviated as BPF), second BPF4, and third BPF
PF5 are provided, each of which has the same characteristics as the first BPF. Furthermore, it is comprised of a first selection circuit 6, a first arithmetic circuit 7, and a subtraction circuit 10.

The operation of the conventional Y/C separation device constructed as described above will be explained below with reference to FIG.

In the above configuration, the input video signal A is first delayed by one horizontal scanning period in the first delay circuit 1. 1st
The signal B output from the delay circuit 1 is sent to the second delay circuit 2.
is further delayed by one horizontal scanning period. The input signal A is also input to the first BPF 3, and a signal D from which the color signal band components are separated is output. The signal B output from the first delay circuit 1 is also input to the second BPF 4, and a signal E from which the color signal band components are separated is output. Said second
The signal C output from the delay circuit 2 is input to the third BPF 5, and a signal F from which the color signal band components are separated is output. The signals D, E, and F are input to the first selection circuit 6. The first selection circuit 6 outputs E, (E-D)/2, (E-D) as a color signal depending on the relationship of the input signals.
One signal is selected from among the four signals F)/2 and (2E-D-F)/4, and a control signal indicating the selected color signal output is output. In the first arithmetic circuit 7, the signals D, E,
F is input, and E, E,
(E-D)/2, (E-F)/2, (2E-D-F)/
4 is output as a color signal. Furthermore, the signal G is subtracted from the signal B by the subtraction circuit 10, and the output becomes the luminance signal output.

[0007]

[Problem to be Solved by the Invention] However, in the conventional configuration as described above, the edge portion of chroma, etc.
Since it has a frequency component outside the F band, there is a problem in that this frequency component appears as dot interference in the luminance signal output.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a Y/C separation device capable of performing more accurate Y/C separation.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the Y/C separation device of the present invention converts input video signal A into n(n
is an integer) A first delay circuit that delays the horizontal scanning period, a second delay circuit that delays the video signal B output from the first delay circuit by n horizontal scanning periods, and a second delay circuit that delays the video signal A from the video signal A through the color signal band. a first band-pass filter that passes the color signal band from the video signal B output from the first delay circuit; and a second band-pass filter that passes the color signal band from the video signal C output from the second delay circuit; a third bandpass filter that passes a signal band; a video signal D output from the first bandpass filter; a video signal E output from the second bandpass filter; and an output from the third bandpass filter. According to the correlation between the video signals D, E, F, the color signal outputs are E, (E-D)/2, (E-F)/2, (2E-D).
- Select one signal from the four signals of F)/4,
A first selection circuit outputs a control signal indicating the selected color signal output, and the color signal output G is set to E, (E-D)/2, according to the control signal output from the first selection circuit. (
a first arithmetic circuit that outputs any one of the signals A-F)/2 and (2E-D-F)/4, and the video signals A, C,
D, E, F are input, and the video signals A, C, D, E, F are input.
According to the correlation between B-G, (
B+A)/2, (B+C)/2, (2B+A+C)/4
a second selection circuit that selects one signal from among the four signals and outputs a control signal indicating the selected brightness signal output; and a brightness signal output according to the control signal output from the second selection circuit. As, BG, (B+A)/2, (B+C
)/2, (2B+A+C)/4, and a second arithmetic circuit that outputs one of the signals.

0010

[Operation] With the above-described configuration, the present invention allows the comb characteristic portion (
By adaptively switching the band of the delay circuit (i.e., the part with comb filter characteristics) between the entire band and the BPF band, it is possible to reduce dot interference appearing in the luminance signal output, resulting in more accurate Y/
C separation can be performed.

[0011]

Embodiments (Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a first delay circuit 1 and a second delay circuit 2 each have a delay period of one horizontal scanning period.
A first BPF 3, a second BPF 4, and a third BPF 5 are provided which pass the color signal band, and each has the same characteristics as the first BPF. Further, a first selection circuit 6, a first arithmetic circuit 7, a second selection circuit 8, and a second arithmetic circuit 9 are provided. Here, except for the second selection circuit 8 and the second arithmetic circuit 9, the circuit is the same as the conventional example shown in FIG.

The operation of the Y/C separation device constructed as described above will be explained with reference to FIG.

The input video signal A is first delayed by one horizontal scanning period in the first delay circuit 1. The signal B output from the first delay circuit 1 is further delayed by one horizontal scanning period in the second delay circuit 2. The input signal A is also input to the first BPF 3, and a signal D from which the color signal band components are separated is output. The signal B output from the first delay circuit 1 is also input to the second BPF 4, and a signal E from which the color signal band components are separated is output. Said second delay circuit 2
The signal C output from is input to the third BPF 5, and a signal F from which the color signal band components are separated is output. The signals D, E, and F are input to the first selection circuit 6. In the first selection circuit 6, E, (E-D)/2, (E-F)/2, (
One signal is selected from among the four signals of 2E-D-F)/4, and a control signal indicating the selected color signal output is output. The first arithmetic circuit 7 receives the signals D, E, and F, and selects E, (E-D )/
2, (EF)/2, or (2E-D-F)/4 is output as a color signal. Further, the second selection circuit 8 receives the signals A, C, D, E, and F, and selects B-G, (B+A)/B-G, (B+A)/
One signal is selected from the two signals of No. 2, and a control signal indicating the selected luminance signal output is output. In the second arithmetic circuit 9, the signals A, B, and G are input, and according to the control signal indicating the luminance signal output output from the second selection circuit 8,
As a luminance signal output, either BG or (B+A)/2 signal is output.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

A detailed circuit example of the second selection circuit 8 is shown in FIG. As shown in the figure, subtracters 11, 12, third, fourth,
Absolute value circuits (abbreviated as ABS) 13 and 1 that constitute the arithmetic circuits 28, 29, 30, 31, and 32 of 5, 6, and 7, respectively;
4, 15, 16, 17 and comparison circuits (abbreviated as COMP) 18, 19, 20, 21, 22, further a third delay circuit 23, NOT circuits 24, 25, 26, AND circuit 2
It consists of 7.

Second selection circuit 8 configured as described above
The operation will be explained below.

First, the subtracter 11 subtracts the signal A from the signal C, and the subtracter 12 subtracts the signal D from the signal F. The absolute value circuit 13 takes the absolute value of the output of the subtracter 11. The absolute value circuit 14 takes the absolute value of the output of the subtracter 12. The absolute value circuit 15 takes the absolute value of the signal D. The absolute value circuit 16 takes the absolute value of the signal E. The absolute value circuit 17 takes the absolute value of the signal F. Next, regarding the absolute value circuit 13 and the comparison circuit 18 that constitute the third arithmetic circuit 28, the output of the absolute value circuit 13 and a predetermined reference signal K1 are compared in the comparison circuit 18, and whether the value is correct or not is determined. Determine which one is negative. If the output of the absolute value circuit 13 is small, that is, if it shows a positive value, it outputs Hi, and if it is large, that is, if it shows a negative value, it outputs Lo to obtain the output signal F1. Regarding the absolute value circuit 14 and the comparison circuit 19 that constitute the fourth arithmetic circuit 29, the output of the absolute value circuit 14 and a predetermined reference signal K1 are compared in the comparison circuit 19, and if the output of the absolute value circuit 14 is small, For example, if it shows a positive value, it outputs Hi, and if it is large, that is, if it shows a negative value, it outputs Lo to obtain the output signal F2. Regarding the absolute value circuit 15 and the comparison circuit 20 that constitute the fifth arithmetic circuit 30, the output of the absolute value circuit 15 and a predetermined reference signal K2 are compared in the comparison circuit 20, and the output of the absolute value circuit 15 is compared with a predetermined reference signal K2.
If the output of 5 is small, that is, it shows a positive value, it outputs Hi, and if it is large, that is, it shows a negative value, it outputs Lo to obtain the output signal F4. Regarding the absolute value circuit 16 and the comparison circuit 21 constituting the sixth arithmetic circuit 31, the absolute value circuit 1
6 and a predetermined reference signal K2 are compared in the comparator circuit 21, and if the output of the absolute value circuit 16 is small, that is, it shows a positive value, it outputs Hi, and if it is large, that is, it shows a negative value, it outputs Hi. Lo is output to obtain an output signal F5. Regarding the absolute value circuit 17 and the comparison circuit 22 that constitute the seventh arithmetic circuit 32, the output of the absolute value circuit 17 and a predetermined reference signal K2 are compared in the comparison circuit 22, and if the output of the absolute value circuit 17 is small, In other words, if it shows a positive value, it outputs Hi, and if it is large, that is, if it shows a negative value, it outputs L.
o to obtain an output signal F6. The output F1 of the comparison circuit 18 is delayed by one horizontal scanning period in a third delay circuit 23 to obtain an output F3. The output F4 of the comparison circuit 20 is N
It is inverted by the OT circuit 24. The output F5 of the comparison circuit 21 is inverted by the NOT circuit 25. Output F of comparison circuit 22
6 is inverted by the NOT circuit 26. Output F1 of comparison circuit 18, output F2 of comparison circuit 19, third delay circuit 23
The output F3 and the outputs of the NOT circuits 24, 25, and 26 are input to the AND circuit 27, respectively, and the AND circuit 2
The output of 7 becomes the control signal output. When the output of the AND circuit 27 is Hi, (B+A)/2 is selected as the luminance signal output, and when the output of the AND circuit 27 is Lo, BG is selected as the luminance signal output.

With this configuration, dot interference appearing in the luminance signal output can be reduced by adaptively switching the band of the comb characteristic portion of the luminance signal output to the entire band or the BPF band. .

[0020] In this embodiment, the delay circuit for delaying n horizontal scanning periods is
Although the explanation was given regarding the case where n=1, in the PAL system, n=
It is also possible to set it to 2.

[0021]

As is clear from the embodiments described above, according to the present invention, by adaptively switching the band of the comb characteristic portion of the luminance signal output to the entire band or the BPF band, the luminance can be improved. It is possible to provide a Y/C separation device that reduces dot interference appearing in signal output and has more accuracy and excellent effects.

[Brief explanation of the drawing]

FIG. 1: Block diagram of a Y/C separation device according to an embodiment of the present invention

[FIG. 2] A block diagram of a circuit example of the second selection circuit shown in FIG. 1.

[Figure 3] Block diagram of conventional Y/C separation device

[Explanation of symbols]

1 First delay circuit 2 Second delay circuit 3 First BPF 4 Second BPF 5 Third BPF 6 First selection circuit 7 First arithmetic circuit 8 Second selection circuit 9 Second arithmetic circuit 23 Third delay circuit 27 AND circuit 28 Third arithmetic circuit 29 Fourth arithmetic circuit 30 Fifth arithmetic circuit 31 Sixth arithmetic circuit 32 Seventh arithmetic circuit

Claims (2)

[Claims] 1. A first delay circuit that delays an input video signal A by n (n is an integer) horizontal scanning periods, and a second delay circuit that delays a video signal B output from the first delay circuit by n horizontal scanning periods. a delay circuit; a first bandpass filter that passes a color signal band from the input video signal A; and a second bandpass filter that passes a color signal band from the video signal B output from the first delay circuit. , a third bandpass filter that passes the color signal band from the video signal C output from the second delay circuit, and a third bandpass filter that passes the color signal band from the video signal D output from the first bandpass filter and from the second bandpass filter. The video signal E to be output and the video signal F to be output from the third bandpass filter are input, and the video signal D is inputted.
, E, F as the color signal output according to the correlation of E, F,
(E-D)/2, (E-F)/2, (2E-D-F)/
a first selection circuit that selects one signal from among the four signals of No. 4 and outputs a control signal indicating the selected color signal output, and a control signal output from the first selection circuit;
As the color signal output G, E, (E-D)/2, (E-F)
/2, (2E-D-F)/4, and the video signals A, C, D, E,
F is input, and according to the correlation of the video signals A, C, D, E, F, the luminance signal output is B-G, (B+A).
a second selection circuit that selects one signal from the four signals of /2, (B+C)/2, and (2B+A+C)/4 and outputs a control signal indicating the selected luminance signal output;
According to the control signal output from the selection circuit, the brightness signal outputs are B-G, (B+A)/2, (B+C)/2,
A luminance signal/chrominance signal separation device comprising: a second arithmetic circuit outputting any one of (2B+A+C)/4 signals. 2. The length of the first and second delay circuits is one horizontal scanning period, and the configuration of the second selection circuit is such that reference signals of predetermined magnitudes are K1 and K2, and the length of the first and second delay circuits is one horizontal scanning period. A third arithmetic circuit (circuit output F1) that outputs whether the value obtained by subtracting the reference signal K1 from the absolute value of the difference between C and signal A is positive or negative.
and a fourth arithmetic circuit (circuit output F2) that outputs whether the value obtained by subtracting the reference signal K1 from the absolute value of the difference between the signals F and D is positive or negative, and the third arithmetic circuit output F1 is A delay circuit (circuit output F3) that delays the horizontal scanning period; a fifth arithmetic circuit (circuit output F4) that outputs whether the value obtained by subtracting the reference signal K2 from the absolute value of the signal D is positive or negative; A sixth arithmetic circuit (circuit output F5) that outputs whether the value obtained by subtracting the reference signal K2 from the absolute value is positive or negative, and outputs whether the value obtained by subtracting the reference signal K2 from the absolute value of the signal F is positive or negative. 7th to do
The arithmetic circuit (circuit output F6) outputs a control signal that selects other than B-G as a luminance signal output only when F1, F2, F3 are negative and F4, F5, F6 are positive, and F1, F2
, F3, F4, F5, and F6 are in a state other than the above-mentioned state, the luminance signal/color signal according to claim 1, further comprising a logic circuit that outputs a control signal for selecting B-G as a luminance signal output. Separation device.