JPH04216125A - Multiinput adder circuit - Google Patents

Abstract

PURPOSE:To obtain a multiinput adder circuit which can meet both requirements of a high processing speed and layout regularity by contriving the logical constitution of the circuit so that the circuit can be applied to the same digit addition of a input number which is equal to the multiple of 5 or lager than the multiple by one. CONSTITUTION:This multiinput adder circuit is provided with the 1st exclusive OR circuit (a) which outputs the exclusive OR signal S1 of the 1st and 2nd input signals x1 and x2, 2nd exclusive OR circuit (b) which outputs the exclusive OR signal S2 of the 3rd and 4th input signals X3 and x4, 3rd exclusive OR circuit (c) which outputs the exclusive OR signal S3 of the signals S1 and S2, 4th exclusive OR circuit (d) which outputs the exclusive OR signal S4 of the 5th input signal X5 and the 1st intermediate carry input CIN1 from a lower digit, 5th exclusive OR circuit (e) which outputs the exclusive OR signal S5 of the signals S3 and S4, and 6th exclusive OR circuit (f) which outputs the sum signal SSUM of a relevant digit by EXCLUSIVE ORing the signal S5 and the 2nd intermediate carry input CIN2 from the lower digit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a multi-input adder circuit that is applied to partial product addition of a multiplier circuit, and particularly a multi-input adder circuit that is suitable for adding the same digits of inputs that are multiples of 5 or one more (or less) than that. This invention relates to an input adder circuit. Generally, parallel multiplication processing between n-bit digital data (ai x bi, where i is 0 to n-1) is performed using n stages x n pieces (64 pieces), as shown in the example of n = 8 in Figure 5. After calculating the partial products (a0b0 to a7b7), the partial products of the same digit in each stage are added together.

The number of digits in this partial product addition process is 2n
-1 digit (P0 to P14), and the number of partial products added between the same digits is n at most (see the part surrounded by the dotted line in the figure). This is a factor that causes the configuration of the partial product addition processing section to become complicated and the addition processing time to increase, and therefore, improvements to the circuit configuration are required.

0003

2. Description of the Related Art FIG. 6 shows an 8-input wallace tree circuit (hereinafter referred to as "wallace tree") that performs eight partial product additions.
8W) is an example. In FIG. 6, x1 to x8 are inputs each corresponding to one partial product, and three inputs x6 to x8 and three inputs x3 to x5 are input to two 1-bit full adders (hereinafter referred to as 3W )110 and 111 respectively, and the remaining two inputs x1 and x2 are input to one 3W1 in the second stage.
12, and two 3W110s in the first stage,
The addition results of 111 are added to the two 3Ws 112 and 11 in the second stage.
Enter 3. And two 3W112, 1 in the second row
13 are input to the 3Ws 114 and 115 in the 3rd and 4th stages, and the intermediate carry (carry) Cin from the lower digit is input to each of the 3Ws 112 to 115 in the 2nd stage and below. The intermediate carry Cout of each 3W110 to 114 up to the stage is output to the upper digit. In addition, Cin, C
The numbers in parentheses attached to out represent the addition stage on the left and the position of 3W in the addition stage on the right (1 is on the left of the drawing, 2 is on the right of the drawing).

According to this, six 1-bit full adders (
3W) 110 to 115 can constitute an 8-input Wallace tree circuit, and the processing time is given by τ×number of stages=4τ, where τ is the processing time of a 1-bit full adder (3W). By the way, FIG. 7 is a configuration diagram of a four-input Wallace tree circuit (hereinafter referred to as 4W) using two 3W circuits. The configuration of this 4W is shown in FIG. 6 as follows: 3W110 in the first stage and 3W113 in the second stage.
A set of 3W111 in the first stage and 3W112 in the second stage,
This is the same as each set of 3W114 in the third stage and 3W115 in the fourth stage.

That is, the 8-input Wallace tree circuit of FIG. 6 can be constructed by repeating three basic circuits (4W), as shown in FIG. 8, and the ease of layout can be improved. Here, as an example of a 4W gate level configuration, the one shown in FIG. 9 is known. The first circuit A adds the four inputs xi (i is 1 to 4, the same applies hereafter) and the intermediate carry Cin from the lower digit, outputs the addition result S and the final carry C, and adds xi to the first circuit A. 2, and the intermediate carry Cout to the upper digit is output from this circuit B.

This 4W critical path has a 7-unit delay (see broken line F in the figure), and for example, the processing time for 8-input addition can be set to 3τ, making it possible to increase the processing speed.

[0007]

[Problems to be Solved by the Invention] However, when using such conventional 4W, it is possible to satisfy both layout regularity and high speed when the number of inputs of the same digit is a power of 2 (2n, where n is an integer), for example,
As shown in FIG. 10, I1, I2, ...2 up to I20
When dealing with 0 input, it takes 3τ for 4W in the first stage and 4W in the second stage, and 3τ for 4W in the third stage and 4W in the fourth stage, which is a total of 6τ, as shown in Fig. 11. Although this is slightly faster than the processing time of 7τ when all 3Ws are used, there is a problem in terms of layout regularity.

[0008] Note that if the number of inputs is 20, this is
It is preferable for the layout to divide each input into four parts.
For this purpose, a five-input Wallace tree circuit using three 3W transistors as shown in FIG. 12 can be used. However, with this configuration, it takes 3τ for addition processing of five inputs, and there are few advantages in using this circuit from the layout point of view. The present invention was made in view of these problems, and by devising the logical configuration, it can be applied to addition of the same digits for inputs that are multiples of 5 or 1 more (or less) than that, and can be applied to high-speed addition. The purpose of the present invention is to provide a multi-input adder circuit that can achieve both flexibility and layout regularity.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention calculates an exclusive OR of a first input signal x1 and a second input signal x2 and outputs a first exclusive OR signal S1. a first exclusive OR circuit a that performs the exclusive OR of the third input signal x3 and the fourth input signal x4, and a second exclusive OR circuit b that outputs the second exclusive OR signal S2. , the first exclusive OR signal S1 and the second exclusive OR signal S2.
A third exclusive OR circuit c which takes the exclusive OR of and outputs a third exclusive OR signal S3, and an exclusive logic between the fifth input signal x5 and the first intermediate carry input CIN1 from the lower digit. a fourth exclusive OR circuit d that calculates the sum and outputs a fourth exclusive OR signal S4, and the third exclusive OR signal S
3 and a fourth exclusive OR signal S4 to output a fifth exclusive OR signal S5; It is characterized by comprising a sixth exclusive OR circuit f that performs an exclusive OR with the second intermediate carry input CIN2 from a digit and outputs a sum signal SSUM of the digit.

0010

[Operation] In the present invention, the critical path of the sum signal SSUM of the relevant digit is provided by a four-stage exclusive logic circuit, and the addition result of five inputs is determined by 2τ. Therefore, the speed is increased by 1τ compared to the conventional circuit shown in FIG.
Since it is a dedicated input circuit, it also has layout advantages.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. First Embodiment FIG. 1 is a diagram showing an embodiment of a multi-input adder circuit according to the present invention. In FIG. 1, xi (i is 1 to 5) represents the first to fifth input signals, CIN1 represents the first intermediate carry input from the lower digit, and CIN2 represents the second intermediate carry input from the lower digit. , COUT1 represents the first intermediate carry output of the relevant digit (CIN1 when viewed from the upper digit), and COUT
2 represents the second intermediate carry output of the digit (CIN2 when viewed from the upper digit), SSUM represents the sum signal output of the digit, and C represents the final carry output of the digit.

Signals x1 and x2 are input to a 2OR/NAND composite gate 10, an EOR gate 14 (hereinafter referred to as the first exclusive OR circuit a), and a 2AND/NOR composite gate 13, and signals x3 and x4 are input to a 2OR/NAND composite gate 10, The signal is input to a NAND composite gate 10, an EOR gate 11 (hereinafter referred to as a second exclusive OR circuit b), and a 2AND/NOR composite gate 13. The output S10 of the 2OR/NAND gate complex 10 is inverted by the INV gate 15 and the signal COUT1
is output as Signal x5 together with signal CIN1
is input to the AND gate 16, and this NAND gate 16
constitutes a fourth exclusive OR circuit d together with the 1OR/NAND composite gate 17 and the INV gate 18.

The output S1 of the first exclusive OR circuit a is input to the EOR gate 19 (hereinafter referred to as the third exclusive OR circuit c) together with the output S2 of the second exclusive OR circuit b.
The output S3 of the third exclusive OR circuit c is input to the EOR gate 20 (hereinafter referred to as the fifth exclusive OR circuit e) together with the output S4 of the fourth exclusive OR circuit d. The output S5 of the fifth exclusive OR circuit e is
The signal SSUM is input to the R gate 21 (hereinafter referred to as the sixth exclusive OR circuit f), and the signal SSUM is output from the sixth exclusive OR circuit f.

On the other hand, the output S13 of the 2AND/NOR composite gate 13 is input to the NOR gate 22 together with S3, and the output S22 of the NOR gate 22 is the output S1 of the NAND gate 16 which is inverted by the INV gate 23.
6X is input to the NOR gate 24, and this NO
The output S24 of the R gate 24 is output via the INV gate 25 as a signal COUT2.

Signals S3, S4, S5, S16X, S22
and CIN2 are input to AND gates 26, 27, and 28, and the outputs of these AND gates 26, 27, and 28 are logically summed by a NOR gate 29 and output as a signal C via an INV gate 30. FIG. 2 is a symbol diagram of a five-input adder circuit having such a configuration. That is, input signals x1 to x5 and CIN1, CIN2,
As a result of the addition, the signals COUT1, COUT2, C
and output SSUM.

The logical expressions of each main signal in such a configuration can be expressed as the following Equations 1 to 4, and the four signals to be generated can be expressed without combining a 1-bit full adder (3W). Signal (SSUM, COUT1, COUT
2.C) can be created.

[0017]

[Math 1]

[0018]

[Math 2]

[0019]

[Math 3]

[0020]

[Math 4]

However, S22 is generated according to the following equation 5.

[0022]

[Math 5]

Here, the generation time of each of the four signals is CO
0.5τ in UT1, 1.5τ in COUT2, C and S
SUM is 2τ. Even the longest one has a conventional configuration of 5W.
The speed can be increased by 1τ compared to 3τ (see FIG. 12). Therefore, it is possible to increase the processing speed, and since it is configured as a dedicated circuit for 5-input addition, it is possible to improve the layout regularity.

It should be noted that the present invention is not limited to the configuration of the above embodiment, and various modifications can be made by changing some of the logical expressions. Second Embodiment For example, in FIG. 3, 40 to 43 are NAND gates;
44-46 are 1OR/NAND composite gates, 47 is 2A
ND/NOR composite gate, 48-50 are NOR gates,
51 is a 1AND/NOR compound gate, 52 and 53 are AN
D gate, 54 to 56 are INV gates, 57 is ENOR
Gate 58 is an EOR gate.

Here, the NAND gate 40 and 1OR/N
The AND compound gate 45 constitutes a negative circuit of the first exclusive OR circuit a, and is connected to the NAND gate 41 and 1OR/NAND.
The composite gate 44 constitutes a negative circuit of the second exclusive OR circuit b, and the ENOR gate 57 constitutes the third exclusive OR circuit c.
NAND gate 43 and 1OR
/NAND composite gate 46 constitutes a negative circuit of the fourth exclusive OR circuit d, and NOR gate 49 and 1AND/
The NOR gate 51 constitutes a fifth exclusive OR circuit e,
EOR gate 58 constitutes a sixth exclusive OR circuit f.

The logical expressions of each main signal in such a configuration can be expressed as shown in Equations 6 to 9 below, and as in the previous embodiment, a 1-bit full adder (3W) is combined. four signals (SSUM,
COUT1, COUT2, C) can be created.

[0027]

[Math 6]

[0028]

[Math 7]

[0029]

[Math. 8]

[0030]

[Math. 9]

However, S47 is generated according to the following equation 10.

[0032]

[Math. 10]

In this embodiment as well, the generation time of each of the four signals is 0.5τ for COUT1 and 1.5τ for COUT2.
5τ, 2τ for C and SSUM. Table 1 shows a comparison table between the above two embodiments and the conventional example (see FIG. 12).

[0034]

[Table 1]

In Table 1, the delay time is expressed as a relative ratio to the generation time of the signal SSUM when one 1-bit full adder (3W) circuit is used, which is 1τ. As is clear from this table, in the method of the embodiment, the critical path is shortened by 1τ, and therefore the speed is increased approximately 1.5 times compared to the conventional example. Please note that the above explanation is based on CM
Although the comparison is based on an OS logic circuit, it is not limited to this, and it goes without saying that it can also be applied to, for example, bipolar logic elements.

FIG. 4 shows an example in which a 20-input adder circuit is constructed using the 5-input adder circuit (hereinafter referred to as 5W) described in each embodiment. The 20 inputs from I1 to I20 are divided into 5 inputs each, and each divided input is input to each of the four 5Ws in the first stage. Then, the output of 5W from the first stage is changed to 2 from the second stage.
4W, and its output is input to one 4W in the final stage.

According to this configuration, 20 inputs can be processed in 5τ. This is the same as 6 in the conventional example (see Figure 10).
It is 1τ faster than τ. In other words, the speed can be increased by 20%. Also, you can create a regular layout,
In particular, technology suitable for integrated circuits can be provided. In addition, in the case of 9-input addition, the first stage is one 5W and one
It may be configured with 4Ws. The processing speed in this case is 3.
The processing speed becomes 5τ, which is 0.5τ faster than the processing speed of 4τ when everything is configured with 1-bit full adders.

[0038]

[Effects of the Invention] According to the present invention, since the logical configuration has been devised, it can be applied to addition of the same digits for inputs that are multiples of 5 or 1 more (or less) than that, achieving both high speed and layout regularity. A multi-input adder circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a 5-input adder circuit according to a first embodiment.

FIG. 2 is a symbol diagram of the 5-input adder circuit of the first embodiment.

FIG. 3 is a configuration diagram of a 5-input adder circuit according to a second embodiment.

FIG. 4 is a configuration diagram of a 20-input adder circuit using the 5-input adder circuit of the first embodiment or the second embodiment.

FIG. 5 is a process diagram of partial product addition used in the conventional explanation.

FIG. 6 is an 8W configuration diagram using six 3Ws used in the conventional explanation.

FIG. 7 is a 4W configuration diagram using two 3Ws used in the conventional explanation.

FIG. 8 is an 8W configuration diagram using three 4Ws used in the conventional explanation.

FIG. 9 is a configuration diagram of 4W used in the conventional explanation.

FIG. 10 is a configuration diagram of a 4W, 20-input adder circuit used in the conventional explanation.

FIG. 11 is a configuration diagram of a 3W 20-input adder circuit used in the conventional explanation.

FIG. 12 is a configuration diagram of a five-input Wallace tree circuit used in the conventional explanation.

[Explanation of symbols] a: first exclusive OR circuit, b: second exclusive OR circuit, c: third exclusive OR circuit, d: fourth exclusive OR circuit, e: fifth exclusive OR circuit, f: 6th exclusive OR circuit.

Claims (1)

[Claims] Claim 1: a) A first input signal x1 and a second input signal x2.
b) a first exclusive OR circuit that takes the exclusive OR of the third input signal x3 and the fourth input signal x4 and outputs the first exclusive OR signal S1; c) a second exclusive OR circuit that outputs a second exclusive OR signal S2; d) a third exclusive OR circuit that outputs a logical OR signal S3; and d) a first intermediate carry input CIN1 from the fifth input signal x5 and the lower digit.
e) a fourth exclusive OR circuit that calculates the exclusive OR of the third exclusive OR signal S3 and the fourth exclusive OR signal S4, and outputs the fourth exclusive OR signal S4; A fifth circuit that calculates an exclusive OR and outputs a fifth exclusive OR signal S5.
an exclusive OR circuit; and f) the fifth exclusive OR signal S5.
and a sixth exclusive OR circuit that performs an exclusive OR operation with a second intermediate carry input CIN2 from a lower digit and outputs a sum signal SSUM of the relevant digit. .