JPH04215469A - Formation method of complementary bipolar transistor - Google Patents

Abstract

PURPOSE: To provide a method for forming a complementary bipolar transistor body structure, while utilizing a self-alignment technique. CONSTITUTION: This process requires only minimum masking steps, because of the simultaneous formation of a PNP emitter contact 71C and NPN additional base contacts 71A and 71B and the similar simultaneous formation of an NPN emitter contact 52C and a PNP additional base contact 52D. The problem of conventional automatic doping generated at the time of patterned subcollector formation is canceled by the P<+> -subcollector formation of a PNP transistor due to ion implantation.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates generally to semiconductor devices and, more particularly, to a method and resulting structure for forming complementary bipolar transistors.

0002

BACKGROUND OF THE INVENTION In the field of bipolar transistor devices, it is generally accepted that it is desirable to incorporate complementary transistors, i.e. both NPN and PNP transistors, on a single chip or substrate. . When complementary transistors are used in this manner, during operation, one transistor is typically on while the other is off, and both types of transistors are in an on/off state at approximately the same time. change. This complementary operation results in improved semiconductor chip characteristics such as reduced power consumption and reduced signal noise.

However, it has also been recognized that it is difficult to fabricate high performance complementary transistors on a single substrate. This difficulty is due in large part to the fact that fabricating high-performance transistors requires highly specialized processes, and these processes are tailored for either NPN or PNP transistors. This is due to Previously, it was extremely difficult to set up a built-in process to form both NPN and PNP high performance transistors on a single substrate/chip.

Those skilled in the art have approached the task of fabricating complementary bipolar transistors in a number of different ways, some of which will be briefly described below.

US Pat. No. 4,719 to Goth,
No. 185 (assigned to the assignee of this invention) includes vertical N
A complementary transistor structure is shown in which PN and PNP transistors are formed by ion implantation of the transistor regions. The transistor areas will later be provided with metal contacts.

No. 4,48 to Magdo et al.
No. 5,552 (assigned to the assignee of the present invention) shows a complementary transistor structure that utilizes isolation structures that allow carefully controlled impurity doping of transistor regions. The incidental base and emitter regions of the PNP device are out-diffused from the doped polysilicon region.

US Pat. No. 3,730 to Ghosh
, 786 (assigned to the assignee of the present invention), in which vertical NPN emitter regions and vertical PNP base regions are formed by outdiffusion from a single doped oxide layer.
A method of forming complementary bipolar transistors is shown. The NPN base region and PNP emitter region are formed by separate diffusions.

Fairchild Semiconductor
European Patent Application No. 0 301 468 by ctor Corporation describes a fabrication process for complementary bipolar transistors in which the emitter region and ancillary base region of the complementary transistor are formed by out-diffusion from a single layer of polysilicon. It is shown. This out-diffusion is accomplished by first defining and doping selected areas of the polysilicon layer and then heating the device to out-diffuse these areas into the substrate. The separation of emitter and incidental base is
It is limited by the resolution of the type of phosphorography used to etch the polysilicon in between.

The present invention seeks to provide a method for fabricating high performance complementary bipolar transistors using processes compatible with current self-aligning transistor manufacturing technology.

0010

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new and improved high performance complementary bipolar transistor structure and method of manufacturing the same.

Another object of the present invention is to provide a method for forming complementary bipolar transistor structures including high performance vertical NPN and PNP transistors.

Another object of the present invention is to provide a method for fabricating complementary bipolar transistors using self-aligned transistor fabrication technology.

Yet another object of the present invention is to provide a high performance vertical PNP transistor structure that includes self-aligned emitter and base regions.

[0014]

SUMMARY OF THE INVENTION In accordance with the present invention, at least two electrically isolated
providing a substrate of semiconductor material including two N-type device regions; forming a P-type buried sub-collector region in a first region of the device region; forming a buried sub-collector region and depositing N on a common surface of the first device region;
forming a P-doped polysilicon layer overlying the base region of the first device region and overlying the second device region; patterning the layer to form an emitter contact approximately centered on the base region of the first device region and a generally annular base contact in the second device region; , forming a layer of insulating material overlying the P-doped polysilicon layer, forming a substantially conformal N-doped polysilicon layer overlying the device, and patterning the N-doped polysilicon layer. hand,
forming a base contact substantially surrounding an emitter contact of a first device region and forming an emitter contact substantially surrounded by a base contact of a second device region; heating the device at least once; and implanting impurities into the device region from the base contact and the emitter contact of the second device region, thereby forming a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region. A method of forming a complementary bipolar transistor device is provided.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, FIG. 1 shows a substrate structure 10 made in conventional manner for fabricating complementary bipolar transistors in accordance with the present invention. Structure 10 includes a slab 12 of P+ silicon formed by a conventional crystal pulling process to have a sheet resistance in the range of, for example, 0.01 ohm-cm. With reference to N-type and P-type semiconductor materials, it is clear that the dopant impurity type is relatively concentrated in the appropriate areas.

A layer 14 of epitaxially grown P-silicon overlies slab 12, while a layer 16 of epitaxially grown N-silicon overlies layer 14. Spaced isolation trenches 18A of insulating material
, 18B, 18C extend downwardly from the top surface 24 of layer 16 into slab 12 to form electrically isolated first and second device regions 26, 28, respectively.

An N+ buried region 30 extends over the P- layer 14 between trenches 18B and 18C, with a heavily doped N++ layer adjacent trench 18C.
It is connected to the surface 24 by a region 32 that spans the entire area. A buried N+ sub-collector region 34 similarly extends across device region 26 between trenches 18A and 18B and is connected to surface 24 by an N++ spanning region 36 adjacent trench 20. A layer 44 of silicon dioxide (SiO2) is conformally disposed overlying the upper surface of structure 10.

As will be apparent to those skilled in the art, the structure 10 shown in FIG. 1 represents a conventional structure for fabricating semiconductor devices, and is based on a number of known processes. It is possible to form Structure 10
An example of a process for forming is as follows. A) Slab 12 is formed by conventional crystal pulling. B) layer 14 is grown on slab 10 in a conventional epitaxial growth reactor using conventional parameters to a thickness of, for example, about 5 micrometers;
For example, it is grown to a thickness of approximately 1×10 15 atoms/cm 3 . C) The surface of layer 14 is doped to give it an N++ conductivity, for example by implanting arsenic ions at a dose of approximately 1.times.10@16 atoms/cm@2. D) Layer 16 is grown on layer 14 in a conventional epitaxial growth reactor utilizing conventional parameters to a thickness of, for example, about 1.0 micrometer. During the growth of layer 16, the heavily doped regions mentioned in step C) self-diffuse into layer 16;
Regions 30 and 34 are formed. E) Isolation trenches 18A, 18B, 18C are e.g.
U.S. Pat. No. 4,104,086 or U.S. Pat.
No. 307,180 (each assigned to the assignee of the present invention and incorporated herein by reference). F) A layer 44 of SiO2 is formed to a thickness in the range of approximately 0.05 to 0.10 micrometers, for example, by a conventional thermal oxidation process. G) N++ spanning regions 32 and 36 are formed by conventional photolithographic masking and ion implantation.

Referring now to FIG. 2, a buried P+ sub-collector region 38 is formed in the device region 26 overlapping the buried region 30. A P+ spanning region 40 is formed between the surface 24 and a region 38 adjacent an N++ spanning region 32. Preferably, sub-collector region 38 and P+ full region 40 are formed by high energy ion implantation with conventional boron ions.

Continuing with FIG. 2, N-type base region 42 is formed using, for example, conventional photolithography masking and phosphorus ion implantation or diffusion.
Formed on surface 24 of device region 26 . The base region 42 includes a region 40 extending over the entire P+ region and a trench 18B.
located in the middle of the latter and adjacent to the latter, the embedded region 30
There is a gap between. As discussed in more detail below, base region 42 serves as a substantial base for a subsequently formed vertical PNP transistor. Referring now to FIG. 3, a layer 46 of silicon nitride is formed overlying layer 44 to a thickness of approximately 0.10 micrometers, for example, by a conventional chemical vapor deposition (CVD) process. Ru.

Continuing with the explanation of FIG. 3, layer 46
After formation, apertures 48 and 50 are masked and etched using conventional photolithographic masking (not shown). Aperture 48 is positioned to expose a portion 24A of the surface of device region 28, while aperture 50 is positioned to expose portion 24B of the surface of base region 42 in device region 26. Layers 46 and 44 may include, for example, C
Apertures 48 and 50 are etched using a reactive ion etching process (RIE) using F4/CHF3/Ar gases.

Referring now to FIG. 4, a layer 52 of P+ doped polysilicon is formed conformally overlying device 10. Referring now to FIG. Layer 52 is, for example, doped in-situ and formed by a conventional CVD process to a thickness of approximately 0.30 micrometers. Alternatively, layer 52 may be deposited without doping (
i.e. native polysilicon) and then doped by ion implantation. A layer of SiO2 can be deposited, for example by thermal oxidation, to about 0.10 microns.
It is formed conformally overlapping layers 52 to a thickness of meters. A layer 56 of Si3N4 is formed conformally overlying layer 54 to a thickness of approximately 0.15 micrometers by a CVD process.

Referring now to FIG. 5, using a conventional photolithographic mask 58,
Surface portions 24B and 24A of device regions 26 and 28
Masking is applied to independent portions of layers 52, 54, and 56 that overlap. The unmasked portions of layers 52, 54, 56 are removed, resulting in aligned portions 52A, 54A, and 56A overlying surface 24B, and aligned portions 52B overlying surface 24A. 54B,
And 56B is left. Layers 56, 54, and 52 are sequentially etched using a RIE process, for example, utilizing CF4/CHF3/Ar and then Cl2 gas.

Referring now to FIG. 6, a second photolithographic mask 60 is utilized to define the base region 4.
2. A matched portion 52C of the layers overlapping approximately in the center of 2;
54C, 56C and aligned portions 52D, 54D, 56D of the layer generally circumscribing the central region of surface 24A.
Masking is applied to The device is then etched and the portions of these layers to be removed are marked by apertures 62, 64. Layers 56, 54, and 5
This etching for portion 2 is performed by an RIE process utilizing the same etching solution as above. As will be described in detail later, the remaining polysilicon region 52C
serves as the emitter contact and dopant impurity source for the vertical PNP transistor that will subsequently be formed. Similarly, the remaining polysilicon region 52
D serves as a base contact and ancillary base dopant impurity source for the vertical NPN transistor that will subsequently be formed.

Continuing with the discussion of FIG. 6, aperture 64 is enlarged a short distance, eg, about 0.05 micrometers, into the surface of base region 42 and into raised pedestal portion 42 of base region 42.
It is circumscribed by A. Aperture 62 is similarly enlarged by the same distance into surface 24A of device region 28, forming recess 28A. Device area 26
and 28 silicon, for example, Cl2/O2/Ar
Etching is performed using gas and RIE process. This over-etching of silicon surfaces 24A, 24B results in polysilicon regions 52
C or 52D undesirable remnants are present in the aperture 62.
or 64. mask 60
are removed in a conventional manner.

Continuing with reference to FIG. 6, the silicon defects are repaired and the dopant impurity in base contact 54D is diffused down into device region 28 and P
+ Diffusing dopant impurities downward from emitter contact 52C to form additional base region 68;
into the device region 26, P+ emitter region 6
9 is formed. A substantially P-type base region 66 is then formed in the device region 28 through the aperture 62 by, for example, boron ion implantation. It is noted that aperture 64 can be blocked by a photolithographic mask during ion implantation. However, by N-doping region 42, P-type ion implantation is overcome.

Referring now to FIG. 7, all exposed vertical edges of the layers overlying structure 10 are covered by protective oxide/nitride sidewalls labeled 66A-E. These sidewalls 66A-E are formed, for example, by sequential blanket deposition of SiO2 and Si3N4 followed by anisotropic etching, leaving the indicated sidewalls. A suitable process for sidewall formation is shown and described in US Pat. No. 4,256,514 to Pogge, assigned to the assignee of the present invention and incorporated herein by reference.

Referring now to FIG. 8, an N+ doped polysilicon layer 71 is deposited conformally overlying structure 10 to fill apertures 62 and 64. It is noted that layer 71 is made of insulating material 54C-D, 56
CD and is insulated from polysilicon regions 52C and 52D by the intervening insulating sidewalls 66A-E. Layer 71 may be formed, for example, by a conventional CVD process using in-situ doping, or
Alternatively, intrinsic polysilicon may be deposited to a thickness of approximately 0.20 micrometers by subsequent ion implantation or diffusion doping.

Continuing with the discussion of FIG. 8, the device is subjected to a conventional annealing process at 880° C. for, for example, 20 minutes. This annealing causes dopant impurities to diffuse downwardly from layer 71 into underlying device regions. Thus, N+ ancillary base regions 70, 72 are formed in device region 26, and N+ emitter regions 74 are formed in device region 28.

As is clear from the above, device area 2
8, a vertical NPN transistor was formed including an emitter region 74, a substantial base region 66, an incidental base region 68, and a sub-collector region 34. at the same time,
According to the present invention, a vertical PNP transistor was formed in the device region 26. This PNP transistor includes an emitter region 69, ancillary base regions 70, 72
, a substantial base region 42, and a sub-collector region 3
Contains 8.

Referring now to FIG. 9, layer 71 is patterned using conventional photolithographic masking techniques to form the lateral side boundaries of emitter contact 52C and to be bounded by insulating sidewalls 66C. Additional base contact areas 71A, 71 spaced therefrom
B will remain. The patterning of this layer 71 also leaves an emitter contact region 71C located approximately centrally within the collateral base contact 52D and isolated therefrom by sidewalls 66B. The layer 71 is made of, for example, Cl
It is formed by using an RIE process using 2/O2/Ar gas.

Referring now to FIG. 10, an aperture formed to receive an electrical contact, ie, an NPN
Aperture 75 to base contact 52D, aperture 76 to N++ spanning region 36 of the NPN subcollector, aperture 78 to PNP emitter contact 52C, region 4 spanning P+ of the PNP subcollector
Aperture 80 to 0 and N+ of PNP ground
A device is shown with an aperture 82 to a region 32 spanning +. Each of these apertures is formed by conventional photolithographic masking followed by etching into the oxide-on-nitride stack. This etching can be performed using, for example, RI gas using CF4/CHF3/Ar gas.
It is formed using the E process.

As can be seen by referring to FIGS. 10, 11, and 12 collectively, the NPN transistor in device region 28 is necessarily rectangular in its entirety, with emitter region 74 bounded by base regions 66 and 68. Besieged. On the other hand, the emitter region 69 of the PNP transistor in the device region 26 forms a bridge to the laterally extending collateral base regions 70 and 72 and is substantially surrounded by the base region 42 .

The devices shown in FIGS. 10 and 11 are completed using conventional multi-level metallization, many types of which are known to those skilled in the art. .

There is thus a new and improved method for fabricating complementary bipolar devices, ie, complementary NPN and PNP transistors, formed on the same semiconductor substrate. The process steps used to fabricate the PNP transistor are:
This is a state-of-the-art self-aligning transistor manufacturing technique. PNP transistors require tight tolerance photolithography alignment, especially
A self-aligning region is included that is formed without the need for base and emitter contact spacing determined by insulating sidewalls.

The application of the invention is in the formation of integrated circuits,
Particularly in the field of very large scale integration (VLSI) circuits.

Although the present invention has been illustrated and described with respect to specific embodiments, those skilled in the art will recognize that many changes, modifications, and changes will occur within the spirit and scope of the invention.
Improvements may come to mind.

[0038]

The present invention provides a number of significant advantages over the prior art. Due to the simultaneous formation of the PNP emitter contact and the NPN collateral base contact, and the similar simultaneous formation of the NPN emitter contact and the PNP collateral base contact, the process of the present invention requires a minimal number of masking steps. Formation of the P+ sub-collector of a PNP transistor by ion implantation eliminates the conventional automatic doping problems that occur when forming patterned sub-collectors. Furthermore, the series resistance of the ion-implanted P+ sub-collector region is
This is the desired small size to prevent device saturation. The base resistance Rbb is desirably small, and the base/emitter junction capacitance and base/collector junction capacitance are NP
Both N and PNP transistors are small.

The resulting NPN transistor is a high performance device, while the PNP transistor also
It exhibits excellent, high-performance operating characteristics, including speed and frequency response close to that of an N-transistor.

[Brief explanation of the drawing]

1 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention; FIG.

FIG. 2 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 3 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 4 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 5 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 6 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 7 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 8 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 9 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 10 is a cross-sectional view depicting a series of steps in the fabrication of a complementary bipolar transistor device according to the present invention.

FIG. 11 is a plan view of the structure of FIG. 10;

12 is a cross-sectional view taken at 12-12 in FIGS. 10 and 11. FIG.

Claims (11)

[Claims] 1. Providing a substrate of semiconductor material comprising at least two electrically isolated N-type device regions with a planar common surface; and P-type implantation in a first region of the device regions. forming an N-type buried sub-collector region in a second region of the device region; and forming an N-type base region in the common surface of the first device region. forming a layer of P-doped polysilicon overlying the base region of the first device region and overlying the second device region; and forming a layer of P-doped polysilicon overlying the base region of the first device region and overlying the second device region. forming an emitter contact centered on the base region of the first device region and forming an annular base contact in the second device region; forming a layer of insulating material overlying the layer of P-doped polysilicon; and forming a layer of conformally N-doped polysilicon overlying the device;
The layer of N-doped polysilicon is patterned to form a base contact surrounding the emitter contact of the first device region and an emitter contact surrounded by the base contact of the second device region. forming a vertical PNP in the first device region; heating the device at least once and implanting impurities into the device region from the base and emitter contacts of the first and second device regions; forming a vertical NPN transistor in the second device region. 2. The step of preparing the substrate includes the step of preparing a slab of P-type semiconductor forming a planar first surface, and adding an N-type semiconductor layer forming the common surface to the first surface. 2. The method of claim 1, further comprising the steps of: epitaxially growing the device regions; and forming insulating regions extending into the slab from the common surface to isolate the device regions. 3. The method further comprises the step of epitaxially growing a lightly doped P-type region between the slab and the N-type semiconductor layer.
The method described in. 4. Forming a heavily doped N-type buried region in the first device region intermediate the buried sub-collector region and the slab; 3. The method of claim 2, wherein a containing region is formed simultaneously with the N-type sub-collector region in the second device region. 5. The method further comprises forming an N-type full range region from a surface of the first device region to contact the N-type buried region in the first device region. 4. A method according to claim 3, characterized in that: 6. The method further comprises forming an N-shaped spanning region from a surface of the second device region to contact the sub-collector region in the second device region. A method according to claim 1, characterized in that: 7. The method further comprises forming a P-type full-length region that will contact the P-type sub-collector region in the first device region from a surface of the first device region. A method according to claim 1, characterized in that. 8. prior to performing said step of forming said layer of P-doped polysilicon, forming a layer of insulating material overlying surfaces of said first and second device regions; 2. The method of claim 1, further comprising patterning the layer to expose a portion of each of the first and second device regions. 9. The step of forming the insulating layer on a patterned P-doped polysilicon layer comprises:
2. The method of claim 1, further comprising the step of forming sidewalls of insulating layer material at exposed edges of the layer of P-doped polysilicon. 10. After the step of patterning the layer of P-doped polysilicon, the method further comprises forming a P-type collateral base region in the second device region by depositing impurities. 2. The method according to claim 1, characterized in that: 11. The N in the first device region
removing a portion of the surface of the N-shaped base region to form a recess in the N-shaped base region; and providing insulation to the walls of the N-shaped base region formed by the last-mentioned removal step. 2. The method of claim 1, further comprising: whereby the base contact for the second device region is formed at least partially within the recess.