JPH04215171A - Information processor - Google Patents

Abstract

PURPOSE:To offer an information processor simulating a neural network capable of performing efficient learning with a small quantity of calculation. CONSTITUTION:Three layer structures X, Y, and Z are provided, and each layer is provided with a signal conversion circuit 11, and a correction circuit 12, and an output signal from the output layer Z is inputted to an error calculation circuit 13 with a teacher signal, and difference between the output signal is sent to the correction circuit 12, and the strength of synapse coupling is changed at the signal conversion circuit 11. Simultaneously, a control circuit 14 selects an appropriate learning mode by a signal from the error calculation circuit 13, and changes the strength of the synapse coupling by a mode fitted in the initial stage of learning or the one fitted in the final stage of learning.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device imitating a neural network.

0002

2. Description of the Related Art In recent years, information processing devices imitating neural networks have been developed, and are now being widely used in pattern classification devices such as character recognition devices. Such an information processing device is described, for example, in the literature (PDP model, D.E.
Ramelhart et al., supervised translation by Shunichi Amari, 1989)
The configuration described in is known.

The configuration will be briefly explained below with reference to FIG. FIG. 4 shows a schematic configuration of an information processing device imitating a neural network having a three-layer structure of a first layer X, a second layer Y, and a third layer Z. 1X, 1Y, and 1Z are signal conversion circuits that generally have a plurality of neural elements each consisting of a linear conversion section and a nonlinear conversion section. 2X, 2Y, and 2Z are correction circuits that rewrite the characteristics of the linear conversion sections in the signal conversion circuits 1X, 1Y, and 1Z. 3 is the ideal output T and the actual output S(z)
This is an error calculation circuit that calculates an error signal D(z) to be sent to the correction circuit 2Z from the error signal D(z).

Next, the operation of the above information processing apparatus will be explained. Note that in most information processing devices that imitate neural networks, multiple signals flow in parallel, but distinguishing them all using subscripts will only complicate the expression, so the following In the explanation, subscripts are omitted unless particularly necessary.

[0005] In the learning operation of an information processing device imitating a neural network, the signal conversion circuit 1X converts the input signal S(
i) is converted into a signal S(x) and output, but the correction circuit 2X stores the signal S(i) and the signal S(x) internally and waits until the input of the error signal D(x). Similar processing is performed in the signal conversion circuits 1Y and 1Z and the correction circuits 2Y and 2Z.
It is also done in Then, the final output S(z) and the ideal output corresponding to the input signal S(i), T, which is also called a teacher signal, are sent to the error calculation circuit 3. In the error calculation circuit 3, from the output signal S(z) and the teacher signal T,
The error signal Dj(z
), for example,

[0006]Dj(z)=-μ(Sj(
z)-Tj) Here, μ is calculated to be a positive constant, and an error signal D(z) summarizing the results is sent to the correction circuit 2Z. The correction circuit 2Z receives the held signals S(y), S(z) and the error signal D(z), sends the correction signal M(z) to the signal conversion circuit 1Z, and j in the signal conversion circuit 1Z. Strength of coupling Wji (z) of the linear conversion section between the th neural element and the neural element in the signal conversion circuit 1Y
of,

[0007]Wji(z) +Dj(z)・S
Corrected to j(z)・(1−Sj(z))・Si(y),
For example, as the error signal D(y),

[0008]ΣD
j(z)・Sj(z)・(1−Sj(z))・Wji
(z) is sent to the correction circuit 2Y. Thereafter, similar processing is performed in the signal conversion circuits 1Y, 1X and the correction circuits 2Y, 2X. By repeating this procedure called learning, an information processing device imitating a neural network learns the relationship between the input signal S(i) and the ideal output T, and also learns the relationship between the input signal S(i) and the ideal output T. Appropriate output will be output based on experience.

In this way, when the information processing device imitating a neural network performs sufficient learning and the error D(z) output from the error calculation circuit 3 becomes smaller than a certain value, the correction circuits 2Z, 2Y, The procedures related to 2X are omitted, and only forward processing from input to output is performed.

[0010] Since such a learning method takes time to converge, a device for speeding up learning is disclosed in, for example, Japanese Patent Laid-Open No. 1-320565. The learning efficiency method shown there prepares a set of several learning parameters (parameter η that determines the step size, parameter α that adjusts the amount of momentum), proceeds with learning for each, and performs the learning every set number of times. The method calculates the error in each case and selects the learning parameter with the least error.

[0011]

[Problem to be Solved by the Invention] However, in the above-mentioned conventional method for improving learning efficiency, error calculations for multiple learning parameters are performed every set number of times, so a huge amount of calculation is required. The problem was that it was needed.

The present invention is intended to solve these conventional problems, and an object of the present invention is to provide an information processing device imitating a neural network that can perform more efficient learning.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention prepares a plurality of learning modes in advance and switches these learning modes according to the output error. .

[0014]

[Operation] With the above-described configuration, the present invention can switch between a learning mode suitable for the early stage of learning and a learning mode suitable for the latter stage of learning, and can perform efficient learning.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus according to an embodiment of the present invention. This information processing device consists of a first layer X, a second layer Y, and a third layer from the input side.
It has a three-layer structure with layer Z. 11X, 11Y, 11Z
is a signal conversion circuit, and 12X, 12Y, and 12Z are correction circuits. 13 is an error calculation circuit, and 14 is a control circuit.

FIG. 2 is a block diagram showing a specific example of the configuration of the correction circuits 12X, 12Y, and 12Z in the information processing apparatus shown in FIG. 121 is a first correction circuit;
2 is a second correction circuit, and 123 is a switching circuit.

The operation of the above embodiment will be explained below with reference to FIGS. 1 and 2. Note that in this embodiment, the information processing device has an error calculation mode and a learning mode.

In the error calculation mode, the signal conversion circuit 11X,
This is a mode in which forward calculations are performed and errors are calculated without changing the internal states of 11Y and 11Z. This mode is normally executed every set number of times, depending on the start of learning and the learning method.

The learning mode is a mode in which learning proceeds according to a learning method selected by a control signal from the control circuit 14. For example, when using the error backpropagation method, it is advantageous to modify the synaptic load each time an input is received as a learning method in the initial stage of learning. It is more advantageous to correct the synaptic load at once after receiving the input a sufficient number of times to be able to estimate it statistically. In the following explanation, a multilayer perceptron having the above two learning algorithms will be explained as an example, but the correction circuit 12 shown in FIG.
The first correction circuit 121 in X, 12Y, 12Z operates according to the former learning algorithm, and the second correction circuit 122
shall operate according to the latter learning algorithm.

First, at the start of learning, the control circuit 14 is reset, and the control circuit 14 uses the correction circuits 12Z and 12Y.
, 12X outputs a control signal for the error calculation mode. An error calculation is performed based on this, and the result is held in the control circuit 14 as an initial error.

Next, the control circuit 14 sends a control signal for selecting a learning method suitable for the initial stage of learning to correction circuits 12Z, 12Y,
12X to the switching circuit 123, and first the first
The correction circuit 121 is selected and learning is started. In addition,
In the configuration of this embodiment, the correction circuit that does not operate has an output of 0.
It is said that

The learning algorithm of the first modification circuit 121 selected by the switching circuit 123 is a method of modifying the synaptic load each time it receives an input, and operates in the same manner as described in the conventional example.

When the output error decreases to a certain rate as learning progresses, the control circuit 14 issues a control signal to operate the switching circuit 123. The switching circuit 123 is a learning algorithm that stops the first correction circuit 121, operates the second correction circuit 122, and corrects the synaptic load at once after receiving multiple inputs, preferably enough times to statistically estimate the input distribution. Learning proceeds based on the following.

When the information processing device imitating this neural network performs sufficient learning and the error output from the error calculation circuit 13 becomes smaller than a certain value, the correction circuits 12X, 12Y
, 12Z are omitted, and only forward processing from input to output is performed.

Note that the control signal output from the control circuit 14 for switching the learning algorithm may be output when the amount of change in the connection weight becomes less than or equal to a set value.

In the first embodiment, the correction circuit 1
2X, 12Y, 12Z are composed of a first correction circuit 121, a second correction circuit 122, and a switching circuit 123, but if the learning algorithm used in the above embodiment is used, the correction circuits 12X, 12Y , 12Z may have the configuration shown in FIG.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 3, 124 is the variation of the error for each input with respect to the synaptic load;

d
It is a variation calculation unit that calculates E/d Wji|pattern, and 125 is an integration unit that integrates the variation results until it receives a signal from the counter 126. 127 is the previous update amount that is reset when switching modes;

128 is an update amount buffer section that calculates ΔWji old, and reference numeral 128 indicates a learning rate μ corresponding to the number of integration times for the integrated variation output from the integrating section 125.
Multiply by

[0030] μ・Σd E/d Wji | patter
129 is a learning rate conversion unit that outputs n, and 129 multiplies the previous update amount by the momentum parameter α,

003
1] A momentum conversion unit that outputs α·ΔWji old. counter 12
6 determines the number of integrations in response to a control signal from the control circuit 14, counts the output of the variation calculation unit 124, and outputs an output when the set number of times is reached. send a signal to.

The operation of the second embodiment will be explained below. When using a learning algorithm that modifies the synaptic load for each input, the set value of the counter 126 is set to 1 by the control signal from the control circuit 14, and when using the other learning algorithm, the input space is statistically modified. The number N is such that it can be estimated.

In the forward calculation process of the information processing device, the variation calculation section 124 includes the preceding stage signal conversion circuits 12X, 1.
The output of 2Y is input. In the case of backward calculation, the error signal from the error calculation circuit 13 is input to the variation calculation unit 124, and the variation regarding the synaptic load of the error for each input,

d E/d Wji|pattern and an error signal to be sent to the next correction circuit 12Y or 12X are determined and sent to the integrating section 125, the counter 126, and the next correction circuit 12Y or 12X, respectively. counter 1
26 counts the number of signals sent from the variation calculation unit 124, and updates it with the integration unit 125 until it becomes equal to the set value (1 or N) determined by the signal from the control circuit 14. The amount buffer section 127 is stopped so that no signal is output. When the count number becomes equal to the set value, the counter 126 sends the integration result to the integration unit 125 and the update amount buffer unit 127.

[0035] Σd E/d Wji | pattern
and the previous update amount,

ΔWji old is output to the learning rate converter 128 and the momentum converter 129, respectively, and the internal values of both are set. The learning rate conversion unit 128 multiplies the integration result in the integration unit 125 by the learning rate μ determined by the signal from the control circuit 14 and outputs the result. The momentum conversion unit 129 multiplies the previous update amount by the momentum parameter α and outputs the result. These two outputs are added to give the update amount,

[0037] ΔWji=μ・Σd E/d Wji|patte
rn + α・ΔWji old, and the signal conversion circuit 1
1X, 11Y, and 11Z are sent to the update amount buffer section 127.

As described above, in the second embodiment, switching between the two learning modes is realized by controlling the set value of the counter 126 and the magnitude of the learning rate by the control circuit 14.

In order to avoid the complexity of the explanation, in the explanation of the second embodiment, only the learning rate is changed when changing the learning mode, but the momentum parameter can also be changed simultaneously or independently.

Furthermore, although the first and second embodiments have been explained using an example in which a multilayer perceptron is trained by the error backpropagation method, the present invention uses a multilayer perceptron as an information processing device imitating a neural circuit. The learning algorithm is not limited to the error backpropagation method. For example, the present invention can be applied to a learning vector quantization method, and as a matter of course, any number of learning modes may be used as long as there are a plurality of learning modes.

Furthermore, although the control signal is output when the value falls below a set value, the control signal may be generated depending on the error range.

[0042]

[Effects of the Invention] As described above, according to the present invention, since the learning mode is switched according to the output error, it is possible to switch between the learning mode suitable for the early stage of learning and the learning mode suitable for the late stage of learning. This allows for more efficient learning.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a correction circuit in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a specific configuration example of a correction circuit in a second embodiment of the present invention.

[Fig. 4] Block diagram showing a schematic configuration of an information processing device imitating a conventional neural circuit

[Explanation of symbols]

11X, 11Y, 11Z Signal conversion circuit 12X, 12
Y, 12Z Correction circuit 13 Error calculation circuit 14 Control circuit 121 First correction circuit 122 Second correction circuit 123 Switching circuit 124 Variation calculation section 125 Integration section 126 Counter 127 Update amount buffer section 128 Learning rate conversion section 129 Momentum conversion section

Claims (5)

[Claims] 1. An information processing device imitating a neural network, characterized in that it has a plurality of learning modes, and the plurality of learning modes are switched by a control signal from a control circuit according to an output error. [Claim 2] The learning mode includes a mode in which the strength of the connection is modified each time one input signal is input, and a mode in which the strength of the connection is modified each time the input signal is input a set number of times. The information processing apparatus according to claim 1, wherein the information processing apparatus is in a mode. 3. The information processing apparatus according to claim 1, wherein the control signal is output when the output error becomes equal to or less than a set value. 4. The information processing apparatus according to claim 1, wherein the control signal is output when the output error becomes equal to or less than a set ratio of the output error at the start of learning. 5. The information processing apparatus according to claim 1, wherein the control signal is output when the amount of change in the connection weight becomes less than or equal to a set value.