JPH04213137A - Data secrecy device memory module - Google Patents

Abstract

PURPOSE:To protect a memory module from an illegal usage by operating a secrecy releasing control by using the first access information at the time of the power-on and start of a reader/writer, when the writing or reading of data for a nonvolatile memory is operated. CONSTITUTION:The writing or reading of the data for an incorporated nonvolatile memory 20 is operated, according to the access from the electromagnetically guided and combined reader/writer. At that time, a secrecy circuit 100 successively compares a read command, address, and data as secrecy releasing information serially transferred by every one but from the pertinent reader/ writer to a control circuit 18 at the time of the power-on and start, from the first bit. The secrecy circuit 100 strops the comparison at the time of detecting a bit incoincidence, stops the operation of the nonvolatile memory 20, and prevents the memory access after that from being performed, when the data different from the preliminarily decided pertinent secrecy releasing information are transmitted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data concealment device for a memory module that writes data to or reads data from a built-in nonvolatile memory in response to access from a reader/writer to which electromagnetic induction is coupled.

0002

2. Description of the Related Art Conventionally, as a memory module of this type, a memory package system disclosed in Japanese Patent Application Laid-Open No. 1-184781 is known. In this memory package system, as shown in FIG.
By placing the coil 16 provided in the memory module 10 close to the coil 14 of No. 2, frequency-modulated access information is sent to the control circuit 18 of the memory module 10 by electromagnetic inductive coupling, and at the same time, the signal of the coil 16 is sent to the rectifier circuit 22. to create the power supply voltage Vcc, and EEPRO
Read access or write access to the nonvolatile memory 20 such as M is performed.

For example, during read access, the control circuit 1
8 is a chip select signal CS for the nonvolatile memory 20.
is activated by sending the shift clock signal SK.
It sends read control data DI consisting of a read command and a read address in synchronization with , receives read data DO read out from the designated address of the nonvolatile memory 20 one bit at a time, modulates the frequency, and then transmits it to the reader/writer 12 side. .

The same holds true for write access, and the control circuit 18 sends write data in addition to a write command and address to the nonvolatile memory 20 as write control data DI.

[0005]

[Problems to be Solved by the Invention] However, in such conventional memory modules, there is no special secrecy regarding reading or writing of the nonvolatile memory 20 from access from the reader/writer 12. First, when the reader/writer 20 is powered on and started, the memory module 10 can be read or written directly.

However, this type of memory module is planned to be used, for example, as a data carrier or an IC card for automatically debiting payment amounts from an account in a cashless system, and memory access must be controlled to prevent unauthorized use. However, there was a problem in that some kind of confidentiality measures had to be taken. The present invention has been made in view of such conventional problems, and it is possible to protect memory modules from unauthorized use by decryption control using the first access information at the time of power-on/start of the reader/writer. The purpose of the present invention is to provide a data concealment device for a memory module.

[0007]

[Means for Solving the Problems] In order to achieve this object, a data concealing device for a memory module according to the present invention is constructed as follows. In addition, the reference numerals in the drawings of the embodiments are also shown. First, the present invention provides a memory module 10 which is electromagnetically coupled to a reader/writer 12 and writes or reads from a built-in non-volatile memory 20 in response to an access from the reader/writer 12 which sends a command, an address, and data in this order. Targets data concealment devices.

In the present invention, such a data concealment device includes a read command detection means (32a) for detecting that the command is a read command "0110", and a read command detection means (32a) for detecting that the command is a read command "0110", and a read command detecting means (32a) for detecting that the command is a read command "0110", and a read command detection means (32a) for detecting that the command is a read command "0110", An address match detection means (28) that detects a match with the bit pattern "000000" and a decipher stored at an address in the nonvolatile memory 20 specified by the predetermined bit pattern "000000" of the address match detection means. The data matching detection means (28) detects that the data "K63-K0" and the data "D63-D0" match, and the data matching detection means (28) detects that the data "K63-K0" and the data "D63-D0" match, and the data matching detection means (28) detects that the command, address data, and deciphering data all match in the above order. A coincidence storage means (32b) that stores information until the power is turned off, and a coincidence storage means (32b).
Permitting means (32c, 34, 3
6), and the non-volatile memory 2 when a mismatch is first detected among the command, address, and deciphering data.
Stopping means (32d, 34, 36) for stopping the operation of 0
It is characterized by having the following.

[0009]

[Operation] According to the data concealment device for a memory module of the present invention having such a configuration, upon power-on start, the read command, address, and
and data are successively compared from the first bit, and if bit data different from the read command, address address, and deciphering data of a predetermined bit pattern is sent, the comparison is performed when a bit mismatch is detected. The non-volatile memory operation is stopped and no further memory access is possible.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a data concealment device provided in a memory module. Figure 1
First, the memory module includes a coil 16 that is electromagnetically coupled to the reader/writer side, as in the conventional example shown in FIG.
Control circuit 18, rectifier circuit 22 that produces power supply voltage Vcc
A nonvolatile memory 20 using EEPROM or the like is provided. A chip select signal CS, a shift clock signal SK, and read control data (read command/read address) are sent from the control circuit 18 to the nonvolatile memory 20.
Alternatively, a DI signal that sends a write control signal (write command, write address, and write data) is provided. Further, read data DO is sent from the nonvolatile memory 20 to the control circuit 18.

Memory module 1 having such a configuration
0 is newly provided with a secret circuit 100. Hidden circuit 1
00 has a comparison circuit 28, a counter 30, and a sequential circuit 32.
is provided. In the present invention, when the illustrated reader/writer 12 is powered on and started, the decryption information is sent from the reader/writer to the control circuit 18 of the memory module 10 by electromagnetic coupling, and the control circuit 18 demodulates the information. , a shift clock signal shown in FIG. 2, a chip select signal, and a DI signal synchronized with the shift clock signal are sent to the nonvolatile memory 20.

In this embodiment, the deciphering request information shown by the DI signal in FIG. 2 has a bit length of 75 bits. The first 4 bits of the 75 bits are the read command "0110", and the next 6 bits are the addresses A5 to A.
0, and with one 0 bit added, the remaining 64 bits store first deciphering data D63 to D0. In response to such deciphering request information from the reader/writer side shown in FIG. 2, the addresses of the nonvolatile memory 20 specified by addresses A5 to A0 in FIG. Release data K63 to K0 are stored in advance. The nonvolatile memory 20 is the control circuit 18
The read command “0” included in the anonymization request information from
110'' and addresses A5 to A0, K shown in FIG.
The read data DO consisting of 63 to K0 is output. Here, the period to when the read command and address are being received,
The read output DO of the nonvolatile memory 20 is in a high impedance state.

Referring again to FIG. 1, comparison circuit 28
Data coincidence detection means that determines whether the I signal and the DO signal match or do not match, and detects that the deciphering data D63 to D0 and the deciphering data K63 to K0 read from the nonvolatile memory 20 match. It has the function of The comparator circuit 28 also has a function as an address match detection means for detecting that addresses A5 to A0 in FIG. 2 match a predetermined bit pattern "000000".

The comparison function of the comparison circuit 28 is realized by an inverting exclusive OR circuit (EX-OR) shown in FIG. Comparison circuit 28 of FIG. 3 produces a coincidence output EQ which becomes 1 when the DI signal and DO signal match. DI signal and DO
If the signals do not match, the comparison circuit 28 generates a mismatch output *EQ (indicating an inverted output of EQ) which becomes 0. Also D
The input line of the O signal is pulled down by a resistor R, and as shown in FIG.
While the DO output of 0 is in high impedance, the DO signal is fixed to 0. By pulling down the DO signal by this resistor R, a bit pattern "000000" is set for determining a match with addresses A5 to A0.

Furthermore, a counter 30 is provided in the secret circuit 100 of FIG. The counter 30 counts the shift clock signal SK obtained from the control circuit 18, and
When 75 shift clock signals SK corresponding to 75 bits as the bit length of the deciphering request information shown as DI in FIG. 2 are obtained from the start, a count output CNT is generated.

FIG. 4 shows a specific embodiment of the counter 30, in which the chip select signal CS shown in FIG.
= 0, the clear state is released and when the chip select signal CS is turned on and CS = 1, the clear state is released and counting of shift clock signals SK is started. When 75 shift clock signals SK are counted, the count output CNT will occur.

Referring again to the secret circuit 100 of FIG.
A sequential circuit 32 is provided. The sequential circuit 32 receives the DI signal, the DO signal, the output of the comparison circuit 28, and the output of the counter 30, and performs the state transition shown in FIG.
2d. In the state transition shown in FIG. 5, the sequential circuit 32 is first in the idle state IDL, and when the chip select signal CS turns on in the idle state IDL, it accepts the DI signal. Here, if the DI signal is a read command and "0110" is input, the status is S1, S2
, S3 and S4. In transition state S4,
Match output EQ from comparison circuit 28 and 7 from counter 30
When the count output CNT from 5 counts is obtained, the pass state PAS is determined based on the logical product (EQ・CNT) of the two.
S, and the output to the AND gate 34 in FIG. 1 is set to 1.
The control circuit 1 for the DO signal from the non-volatile memory 20 as
8 of the gate circuit 36, and
The PASS output to the ND gate 38 is set to 1, and the CS signal is sent to the nonvolatile memory 20 via the AND gate 38 and the OR gate 42.

Furthermore, when the comparison circuit 28 obtains a mismatch output *EQ in the transition state S4, the fail state F
AIL, the output of the sequential circuit 32 to the AND gate 34 in FIG.
Sending of the DO signal from 0 to the control circuit 18 is prohibited. At the same time, the AND gate 38 of the gate circuit 36 is disabled due to the PASS signal being 0 due to the mismatch output *EQ, and the AND gate 40 is also disabled due to the FAIL output being 1, and the chip select signal CS to the non-volatile memory 20 is disabled.
Turn off.

Then, if the chip select signal CS stops in the fail state FAIL, that is, *CS(CS
(inverted value), the state returns to the original idle state IDL. Also, in the IDL state, the read command “0110
” If a pattern other than “” is entered, FAIL will occur at that point.
transition to state. As a result, the sequential circuit 32 detects the read command detection unit 32 which detects that it is a read command.
a, a coincidence storage section 32b that stores that all three of the command, address data, and deciphering data match in order until the power is turned off; and based on the coincidence storage of the coincidence storage section 32b, a A permission section 32c that permits writing and reading, and a stop section 32d that stops the operation of the nonvolatile memory 20 when a mismatch is first detected among commands, addresses, and deciphering data.
It will have the function of

Next, the operation of the embodiment shown in FIG. 1 will be explained. still,
Addresses A5 to A0 use "000000". When the reader/writer side is powered on or initial started with the coil 16 of the memory module brought close to the reader/writer side coil (not shown), the shift clock signal SK and chip select signal shown in the figure are sent to the memory module. Deciphering request information having a predetermined format shown by signals CS and DI is sent. Of course, in electromagnetic inductive coupling, these bit information are frequency modulated and sent.

The signal induced in the coil 16 is transmitted to the rectifier circuit 2.
The power supply voltage V for the inside of the memory module is rectified by 2.
cc, and at the same time, the control circuit 18 outputs the shift clock signal SK shown in FIG. 2 demodulated from the frequency modulation signal.
, a chip select signal CS and a DI signal are output to the nonvolatile memory 20. The DI signal output from the control circuit 18 is input to the sequential circuit 32 of the secret circuit 100. Furthermore, when the control circuit 18 sends a read command and address to the nonvolatile memory 20 bit by bit, the same data stored in advance from the nonvolatile memory 20 is sent in synchronization with subsequent deciphering data D63 to D0. The deciphering data K63 to K0 having contents are read bit by bit.

To explain in more detail, first, when a read command "0110" is input, the state changes to S4. From here, the output EQ of the comparison circuit 28 is evaluated. Next, add 1 dummy bit to addresses A5 to A0 to create “000000”.
Since the DO output of the non-volatile memory 20 is in a high impedance state during the to period in FIG. 2 when "0" is input, it is pulled down by the resistor R of the comparison circuit 28 shown in FIG. 3, and the DO signal becomes 0 during the to period. becomes. For this reason, address +
If the dummy bit is "0000000", the output EQ of the comparison circuit 28 becomes EQ=1 during the to period, and the transition state S4 is maintained.

[0023] Subsequently, data comparison is performed. That is, D
A comparison of i and Ki (where i = 63 to 0) is performed for each bit, and if Di and Ki are consecutively equal, the state is S.
4, but if they become no longer equal halfway through, the state changes from S4 to FAIL, and the FAIL state is maintained until CS=0. On the other hand, the counter 30 releases the clear state when the chip select signal CS turns on, and counts the subsequently obtained shift clock signal SK. When the count is reached, the count output CNT
will occur.

When the count output CNT of count value 75 is obtained from this counter 30, if the transition state is S4 and the comparison circuit 28 has produced a coincidence output EQ, the sequential circuit 32 passes the pass as shown in FIG. Move to state PASS, AND
The gate 34 is placed in an allowable state. At the same time, by turning on the AND gate 38 of the gate circuit 36, the chip select signal CS from the control circuit 18 is sent directly to the nonvolatile memory 20 via the OR gate 42.

Therefore, from then on, the read data DO of the nonvolatile memory 20 is transferred to the control circuit 1 via the AND gate 34.
8, and the chip select signal CS
The nonvolatile memory 20 is also directly connected to the nonvolatile memory 20 via the gate circuit 36.
Therefore, read access and/or write access to the nonvolatile memory 20 of the memory module can be effectively performed until the reader/writer side is powered off.

On the other hand, in the case of unauthorized use, the reader
As shown in the DI signal in Figure 2 from the writer side, when a command other than the read command is sent and a bit mismatch in the command is detected, even if the read command is correct, the address and deciphering data following the read command are incorrect. When an error (inconsistency) is detected even when an item is sent, the sequential circuit 32 shifts to the fail state FAIL in FIG. 5, keeps the output of the sequential circuit 32 to the AND gate 34 at 0, and 36 turns off the chip select signal CS. Therefore, non-volatile memory 2
Sending of read data DO from 0 is prohibited, and the chip select signal CS remains off, making read access and/or write access to the nonvolatile memory 20 impossible due to unauthorized use from the reader/writer side.

In the above embodiment, in the event of unauthorized use where the decryption request information does not match, the transmission of read data from the non-volatile memory 20 is prohibited and the chip select signal CS is also turned off. However, at the same time, the DI signal line for the nonvolatile memory 20 may be disconnected to prohibit write access and read access to the nonvolatile memory 20 itself. Furthermore, the operation of the nonvolatile memory 20 may be prohibited for the line of the shift clock signal SK. Of course, the power supply from the rectifier circuit 22 to the nonvolatile memory 20 may be cut off. Further, in the above embodiment, the addresses A5 to A0 are all zeros, but it goes without saying that any other appropriate address may be used as the keyword storage address.

[0028]

As described above, according to the present invention, a decryption request is made to the memory module immediately after the power-on start of the reader/writer side, and upon receiving this decryption request, the memory module side makes preparations. The memory module cannot be accessed unless a match is obtained with the decryption information, and unauthorized use such as unauthorized rewriting of the memory contents of the memory module can be reliably prevented. Furthermore, even if a read command or the like is sent before sending a deciphering request, these commands can be ignored.

[Brief explanation of the drawing]

[Fig. 1] An embodiment configuration diagram showing one embodiment of the present invention.

[Figure 2
] An explanatory diagram showing the shift clock signal SK first sent from the reader/writer, the chip select signal CS, the DI signal as decryption request information, and the DO signal read from the memory.

[Fig. 3] A diagram illustrating a specific example of the comparison circuit in Fig. 1.

[Figure 4
] An explanatory diagram of a specific example of the counter in FIG. 1

[Figure 5] Figure 1
Transition state diagram of sequential circuit

[Fig. 6] Explanatory diagram of a conventional device

[Explanation of symbols]

10: Memory module 12: Reader/writer 14, 16: Coil 18: Control circuit 20: Non-volatile memory (EEPROM) 22: Rectifier circuit 28: Comparison circuit 30: Counter 32: Sequential circuit 32a: Read command detection section 32b: Match storage unit 32c: Permission section 32d: Stop part 34, 38, 40: AND gate 36: Gate circuit 42: OR gate

Claims (1)

[Claims] Claim 1: A reader/writer that is electromagnetically coupled to a reader/writer and sends commands, addresses, and data in this order.
In a memory module that writes data to or reads data from a built-in nonvolatile memory in response to access from a writer, a read command detection means detects that the command is a read command; address match detection means for detecting a match with a bit pattern; the data matches deciphering data stored at an address in the nonvolatile memory indicated by a predetermined bit pattern of the address match detection means; a data matching detection means for detecting that;
a coincidence storage means for storing that all the commands and addresses match in order until the power is turned off; permission means for permitting writing to and reading from the non-volatile memory based on the coincidence memory of the coincidence storage means; and the command and the address. , and in the de-masked data,
A data concealment device for a memory module, comprising: stopping means for stopping the operation of the nonvolatile memory when a mismatch is first detected.