JPH04212995A - Electronic musical instrument with built-in pedal effect attachment - Google Patents

Abstract

PURPOSE:To cause fluctuation and swell of resonating sounds similar to those of an acoustic piano by means of operation of a keyboard and/or a pedal. CONSTITUTION:A pedal stepping distance is read (S2001) from an AD converter as a variable PD on a RAM and it is decided whether or not this PD is changed as compared with one read last time. If there is any change in the PD, access is made to a table on a ROM according to the value of the PD and corresponding reverb depth RVD and reverb time RVT are read and set on the RAM (S2003). Similarly, a corresponding vibrato depth factor FMD and a corresponding value of LFO rates are read and set on the RAM (S2004). The RVD, RVT, FMD and RAT are transferred to a factor memory in a DSP (S2005). These factors are supplied to a comb filter, a multiplier, the multiplier of a vibrator address computing element and the adder of a triangular wave generator portion and then reverberation effect accompanied by different fluctuation effects proportional to the pedal stepping distance is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument, such as an electronic piano, which generates resonant sound by operating operators such as a keyboard and pedals.

0002

2. Description of the Related Art Conventionally, pedal effects have been widely added to electronic pianos for the purpose of adding effects similar to those of the sustain pedal of an acoustic piano. For example, when a pedal is on, the sound is produced with the same musical envelope as when the key is held down even after the key is released, or the envelope characteristics are switched depending on the on/off status of the pedal. It has been known. There is also a device in which this switching is performed in response to continuous changes in the amount of depression of the pedal.

Furthermore, when considering the function of the pedal on an acoustic piano, the unique sound produced when the pedal is depressed is not simply due to the change in the envelope, but is due to the damper of all the strings. Focusing on the fact that the resonance sound generated by the vibrations of strings that are pressed apart and causing other strings to resonate is an important component, the musical tones produced by electronic musical instruments are
There is a technique in which the above-mentioned resonance sound is generated in a pseudo manner by adding a reverb effect in response to a pedal operation.

[0004] With such a technique, it is possible to easily add the effect of resonance sound.

[0005]

[Problem to be Solved by the Invention] In an acoustic piano, the strings are tuned based on a characteristic called a tuning curve, and due to overtone deviations caused by the size of the strings themselves, the resonance tone may fluctuate. Swells occur.

However, as in the conventional example described above, there is a problem in that it is difficult to generate the effects of fluctuations and undulations in resonance by simply adding a reverb effect. An object of the present invention is to make it possible to generate fluctuations and undulations in resonance sound.

[0007]

SUMMARY OF THE INVENTION The present invention first includes sound source means for generating musical tone signals in accordance with performance information. The means is, for example, a digital sound source based on a PCM method, a frequency modulation method, a phase modulation method, or the like. The performance information in this case is, for example, key press information including key notes generated from the keyboard of the electronic piano, key release information, and the like.

[0008] Next, a modulating means is provided for modulating either the frequency or the phase of the original musical tone signal generated from the sound source means. The means is, for example, a vibrato effect adding device. Next, it has a modulation characteristic control means for arbitrarily controlling the modulation characteristic of the musical tone signal modulated by the modulation means. The means is a delay memory for calculating and setting a vibrato depth coefficient according to, for example, a combination of key notes generated from a keyboard or an amount of pedal operation.

[0009] The apparatus also includes reverberation sound generation means for generating reverberation sound by adding a reverberation effect to the musical tone signal modulated by the modulation means. The means is, for example, a reverb effect adding device.

[0010] Next, there is provided an operation means for generating operation information for controlling the volume of the reverberation sound based on the operation by the performer. The means is, for example, a pedal operating means. Furthermore, it has a reverberation volume control means for controlling the volume of reverberation sound generated by the reverberation sound generation means according to operation information from the operation means. The means is, for example, a multiplier that multiplies the reverberation sound by a reverb depth corresponding to the amount of pedal operation.

[0011]The apparatus further includes an adding means for adding the reverberant sound generated by the reverberant sound generating means to the original musical tone signal generated from the sound source means and outputting the result as a musical tone output signal. The above-described configuration of the present invention may be configured to further include reverberation time control means for controlling the reverberation time of the reverberation sound generated by the reverberation sound generation means in accordance with operation information from the operation means. The means is, for example, a multiplier that sets the reverb time according to the amount of pedal operation as the feedback amount of reverberant sound.

[0012]Furthermore, it is also possible to have a modulation characteristic control means for controlling the modulation characteristic of the musical tone signal modulated by the modulation means in accordance with the operation information from the aforementioned operation means or the aforementioned performance information. The means is means for setting the speed and depth of vibrato according to, for example, information indicating the type of chord chord produced by key operation or the amount of pedal operation.

[0013]

[Operation] First, in the modulation means, the frequency or phase of the original musical tone signal from the sound source means is modulated based on the performance information generated from the keyboard or the like or the amount of pedal operation. next,
Based on the modulated musical tone signal, the reverberation sound generation means controls the volume or reverberation time of the reverberation sound based on operation information from an operation means such as a pedal operation means.

[0014] Thereby, it is possible to add a fluctuation or undulation effect to the resonance sound, similar to the pedal effect of an acoustic piano.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram according to an embodiment of the present invention.

[0016] The CPU 101 loads the program stored in the ROM 102 connected via the bus 114 into the RAM.
By executing 103 as a work memory, an interface circuit (I/F) 109 from the keyboard 108,
Sound source 10 based on performance information input via bus 114
4, a DSP (Digital Signal Pro
cessor) 105.

The musical tone signal generated from the sound source 104 is D
Input to SP105. The DSP 105 uses the connected delay memory (E) 106 and the like and executes a predetermined operation program to give a desired time change to the read address of the digital musical tone signal data input from the sound source 104. Performs processing to modulate and add reverberation effects. The digital musical tone signal that has been modulated and has a reverberation effect is converted into an analog musical tone signal for left and right channels by a D/A converter 107 and output, and then amplified by amplifiers 112L and 112R for the right and left channels, respectively. , the sound is emitted from the speakers 113L and 113R.

Next, FIG. 2 is a diagram showing the internal configuration of the DSP 105 of FIG. 1. In the figure, a program memory 201 is a memory that stores a predetermined microprogram, and supplies a predetermined operating program to a control circuit 202 according to instructions from the CPU 101 in FIG.

The control circuit 202 includes a program memory 20
Based on the output contents of 1, it outputs various control signals for data transfer and calculation between each register and memory, opening and closing control of each gate and latch, as well as a counter value SC that is incremented at each sampling timing, which will be described later. Perform the desired signal processing operation.

The coefficient memory (P) 203 is shown in FIG.
As shown in 7, this is a register that stores various parameters for adding a reverberation effect, and these coefficients are stored in the CPU 1.
01, the data is read out from the RAM 103 in FIG. 1 and stored.

The work memory (W) 204 is a working memory in which waveform signals created within the DSP 105 are temporarily saved, as shown in FIG. 18, which will be described later. Further, as shown in FIG. 19, which will be described later, the address offset memory (T) 205 is connected to the delay memory (E) 10, which will be described later.
This is a register that stores the offset value of address 6, and the offset value is controlled by the CPU 101 as shown in FIG.
is read out from the RAM 103 and stored.

The delay memory (E) 106 has its output and input connected in a ring through registers (EI) 230 and (EO) 229, and has a counter value SC incremented at each sampling timing and a delay memory The value obtained by adding the offset value from the address offset memory 205 by the adder 227 is set as an address. The delay time of data written with a certain offset value is expressed as the difference between that offset delay and the offset delay of the read address. Note that reading and writing data to the delay memory 106 is performed by registers (EO) 229 and (EI), which will be described later.
) 230.

The input register (PI) 206 stores the digital input musical tone signal from the sound source 104 in FIG. 1, and supplies it to each section via the internal bus 207. The previously mentioned coefficient memory (
P) 203, the output of the work memory (W) 204, and the output of the input register (PI) 206 are input to the gate terminals of gates 208 to 211 along with outputs from each register described later, and the outputs from the gates 208 to 211 are Registers (M0) 212, (M1) 213, (A0) 214,
(A1) 215 is input.

Register (M0) 212, (M1) 213
The data being supplied to the multiplier 216 is stored, and the registers (A0) 214 and (A1) 215 are storing the data being supplied to the adder/subtractor 217. The output of SR 213 and the output of register (SR) 224, which will be described later, are input to multiplier 216 via gate 218, and are also input to register (A0) 2.
14 and the output of a register (MR) 221, which will be described later, are input to an adder/subtractor 217 via a gate 219, and output to a register (A1) 215 and a register (A1, which will be described later).
The output of R) 222 is sent to the adder/subtractor 21 via the gate 220.
7 is output.

The multiplication result of the multiplier 216 is stored in the register (MR
) 221, the output of the register (MR) 221 is supplied to the gate 209 and the gate 219, and the operation result of the adder/subtractor 217 is stored in the register (AR) 222, and the output of the register (AR) 222 is gate 220
is supplied to the register (S) via a clipper circuit 223 to prevent overflow (overflow).
R) 224. The output of the register (SR) 224 is supplied to the gate 218, and is also stored in the work memory (W) 204 via the internal bus 207 as the result of processing for a certain note.

The above calculation result is stored in the work memory (W) 20.
When the series of processing is completed, the data stored in the memory is transferred to the output register (OR) 225, and output from the register to the D/A converter 107 in FIG.

On the other hand, address offset memory (T) 2
The output of 05 is input to a register (TR) 226, and the output of the register is input to an adder 227 together with a counter value SC that is incremented at every sampling timing. The calculation result of the adder 227 is stored in register (EA) 2.
The digital input musical tone signal to which the reverberation effect is to be added is input to the register (EO) 229 via the internal bus 207 and the value of the register is stored as an address in the delay memory (E) 106. , the output of the same register is supplied to the delay memory (E) 106. The output from the delay memory (E) 106, which is delayed by a predetermined amount and modulated by the difference value between the write address and the read address, is output to the register (EI) 230.

The musical tone signal data to which the reverberation effect has been added and stored in the register (EI) 230 is transmitted via the internal bus 207 to, for example, the registers (A0) 214 and (A0).
1) Transferred to 215 and output as right channel output and left channel output.

FIG. 3 shows the sound source 104 of FIG. 1 and the sound source 104 of FIG.
FIG. 2 is a block diagram of the operating principle of the DSP 105 of FIG. Sound source 10
4 has 16 sound generation channels based on time-sharing processing, and the output of each channel is processed by multipliers 301, 302, and 303 into three types of weighting parameters RLn, LLn,
It is multiplied by ELn (n represents each sound generation channel number from 0 to 16) and accumulated by adders 304 to 306 for each three groups. The cumulative results of the adders 304, 305, and 306 are stored as the right channel direct sound R, left channel direct sound L, and pedal effect sending sound E in the work memory (W) 204 in the DSP 105 (FIG. 2 and FIG. 18 described later).
reference). The above three types of parameters RLn
, LLn, and ELn are given from a key follow table shown in FIG. 9, which will be described later, and which is stored in the ROM 102 shown in FIG. 1, depending on the keynote to be sounded. With this key follow table, as will be explained later, similar to the string arrangement of an acoustic piano, the direct sound of the left and right channels is localized and produced closer to the right as the key note is higher, and further to the left as the key note is lower. The higher the pitch, the higher the pitch.
The lower the bass, the lower the setting.

In the DSP 105, the vibrato effect adding section 3 is first applied to the pedal effect sending sound E set in the work memory (W) 204 (FIG. 2) from the sound source 104.
A vibrato effect is added in step 07, and then a reverb effect is added in a reverb effect adding section 308 to the vibrato output VO output from there, and then a reverb right channel output R from the reverb effect adding section 308 is added.
OT and reverb left channel output LOT are added to right channel direct sound R and left channel direct sound L in adders 309 and 310, respectively, and the D/A conversion in FIG. 1 is performed as right channel musical sound output ROUT and left channel musical sound output LOUT. output to the device 107. Here, the reverb time RVT, which will be described later, in the reverb effect adding section 308 is
, and the reverb depth RVD are continuously variably controlled according to the amount of depression of the pedal 110 in FIG.

FIGS. 4A and 4B are block diagrams showing the operating principle of the vibrato effect adding section 307 shown in FIG. The addition section consists of the vibrato calculation section in Fig. 4(a) and the vibrato calculation section in Fig. 4(a).
b) A vibrato address generating section.

First, in the vibrato calculation section of FIG. 4(a), the pedal effect sending sound E output from the sound source 104 of FIG. , the write address when the pedal effect sending sound E is written to the delay memory 401 is the address offset memory (T) 205, which will be described later.
The write address VWA is generated by adding a counter value SC that is incremented at each sampling timing to a constant value vibrato write address offset VW stored in the write address VW. Further, the read addresses at which the vibrato output is read from the delay memory 401 are given as two read addresses VRA1 and VRA2 generated by a vibrato address generation section described below with a vibrato effect added thereto. Then, an interpolation operation is performed on the two memory outputs read from the above two read addresses of the delay memory 401 using adders 402 and 403 and a multiplier 404, thereby obtaining a vibrato output.

Next, the vibrato address generation section shown in FIG. 4(b) is composed of a triangular wave generator section 404, a low pass filter (LPF) section 405, and a vibrato address calculation section 406. Then, a sinusoidal LF obtained by smoothing the triangular LFO (low frequency oscillation) output TRI generated from the triangular wave generator section 404 in the LPF section 405.
Based on the O signal SIN, read addresses VRA1 and V
By periodically changing RA2 and accessing the delay memory 401 using these addresses, a low frequency modulated vibrato output can be obtained.

In the triangular wave generator section 404,
1 sample delay unit 40 for each sampling timing
7, the sawtooth LFO output SAW at the previous sampling is read out, and the adder 408 reads out the sawtooth LFO output SAW from the previous sampling.
By sequentially adding the rate correspondence values RAT, a linearly increasing signal value is obtained. At this time, the sawtooth LFO output SAW has a constant bit width, and if its most significant bit (MSB) is the sign bit, the value of the output is
At each sampling timing, the value increases by RAT from 0, and at the next timing when it reaches the maximum positive value (the most significant bit is "0" and the other bits are "1"), it becomes the minimum negative value. It jumps to a value (all bits are "1"), and then linearly increases by RAT from there toward the maximum positive value again. That is, the sawtooth LFO output from the adder 408
The output SAW becomes a sawtooth low frequency period (LFO) signal that increases linearly from a negative minimum value to a positive maximum value and then jumps again to the negative minimum value.

Further, in the adder/subtracter 409, when the sawtooth signal SAW is positive, this signal value is set to a constant coefficient value of 0.
．． 5, and conversely, if it is negative, the sawtooth signal is subtracted from the coefficient value 0.5. As a result, the adder/subtractor 409
As the output of A triangular wave LFO output TRI having a characteristic of increasing linearly toward the positive maximum value once the negative minimum value is reached is obtained.

Next, the triangular wave LFO output TRI is input to an LPF section 405 consisting of multipliers 410, 413, an adder 411, and a one-sample delay section 412, where the harmonic components of the output are cut. , sinusoidal LF
O output SIN is obtained.

Next, this sinusoidal LFO output SIN is input to the vibrato address calculation section 406. Here, basically, the counter value SC is incremented every sampling period by adders 415 and 416.
By adding the vibrato read address offset VR to, in synchronization with the write address VWA,
A read address VRA2 that changes while maintaining a constant offset is generated to follow this.

[0038] Then, in the adder 415, the sinusoidal LFO output SIN, which changes periodically around the value 0, is added to the address value calculated as described above, so that the address value has a periodic value. It gives fluctuation. As a result, the low frequency sinusoidal LFO output S is output from the delay memory 401 of the vibrato calculation section in FIG.
A vibrato output VO that has been frequency modulated at IN and has a vibrato effect added thereto is read out. In this case, the range of change in the depth of the vibrato effect is determined by the vibrato depth coefficient FM multiplied by the sinusoidal LFO output SIN in the multiplier 414.
Controlled by D. The value of this coefficient is automatically set together with the LFO rate corresponding value RAT in accordance with the type of chord detected based on the keynote of the performance information.

Here, in order to improve the accuracy of frequency modulation, the following interpolation calculation is performed. That is, first, the adder 416 generates the read address VRA2 based on the vibrato write address offset VR, and the adder 417 generates the read address VRA2 based on the vibrato write address offset VR+1.
Read address VR with address value +1 to A2
A1 is generated. Next, the subtracter 402 in FIG. 4(a)
In this step, the difference value between the two outputs read from the two adjacent addresses VRA2 and VRA1 of the delay memory 401 is determined. Then, in the multiplier 404, the difference value is added to the sinusoidal L output from the multiplier 414.
By multiplying the value VL of the decimal part of the FO output SIN, a change corresponding to the decimal value is calculated. and,
The adder 403 adds the above change to the output value of the address VRA2, thereby obtaining an accurately interpolated vibrato output VO.

[0040] The range of change in the speed of the vibrato effect is
It is controlled by the value of the LFO rate corresponding value RAT, and as described above, this value is automatically changed and set in accordance with the type of chord played by the performer.

FIG. 5 shows the reverb effect adding section 308 in FIG.
FIG. 2 is a block diagram of the operating principle. In this figure, the vibrato output VO of FIG. 3 or 4 is connected to #1 in series.
The signal is inputted to eight comb filters 503 to 510, #1 to #8, which are connected in parallel, through two-stage all-pass filters 501 and #2, 501 and 502.

First, the vibrato output VO is input to a first-stage all-pass filter (all-pass filter) 501, where the delay component of the vibrato output VO is increased and an output signal AO1 having a large number of delay components is obtained. The signal is output to the second stage all-pass filter 502 as a signal.

In the all-pass filter 502, the delay component is further increased in the signal AO1 with the increased delay component, and the resulting output signal AO2 is passed through a plurality of parallel-connected comb filters 503 of #1 to #8. ~510 is output.

In this embodiment, an example is shown in which two all-pass filters 501 and 502 are inserted as all-pass filters provided before the comb filters 503 to 510 for adding reverberant sound, but of course the number and connection method may vary. is not limited, and may be one or three or more. In this case, according to experiments conducted by the inventor, the best effect could be obtained when two stages of all-pass filters were inserted in series.

The all-pass filters 501 and 502 include a delay element 529, multipliers 530 and 531, and adders 532 and 53, as shown in FIG.
It is composed of 3. In this way, the all-pass filters 501 and 502 have a delay element 529 in between, and the output side is fed back via the multiplier 530 which is multiplied by a coefficient of 0.5, and the input side is also fed back through the multiplier 530 which is multiplied by a coefficient of 0.5.
31, so when a signal is input to the all-pass filters 501 and 502, a large number of delay components are output based on the input signal. Note that the configurations of the all-pass filters 501 and 502 are not limited to the above-described configuration, and other types of all-pass filters may be applied to each.

The output signal data AO2 of the all-pass filter 502 described above is input to eight comb filters 503 to 510, #1 to #8, arranged in parallel. These comb filters 503 to 510 are, for example, shown in FIG.
As shown in FIG. 2, it is composed of a delay element 534, a multiplier 535, and an adder 536. Each comb filter 503~
From 510, the aforementioned signal data AO2 is transmitted to each delay element 5.
34, the amount of feedback to the input is delayed by an amount corresponding to a different offset address (described later), and the amount of feedback to the input is
Output signals CLOi and CROi (1≦i≦8) of the two left and right channels, which are determined in accordance with the common reverb time RVT given to the reverberation circuit 35, are output.

Then, the comb filter right channel output C
RO1, CRO2, . . . CRO8 are multipliers 511 to
After being weighted by a common reverb depth RVD in 518, it is accumulated in an accumulator 527 and output to the adder 309 in FIG. 3 as the reverb right channel output ROT. Similarly, left channel comb filter output CLO1, CL
O2, . . . CLO8 are also weighted by a common reverb depth RVD in multipliers 519 to 526, then accumulated in an accumulator 528, and output to the adder 310 in FIG. 3 as a reverb left channel output.

Here, the reverb time RVD supplied to the comb filters 503 to 510 is varied depending on the amount of depression of the pedal 110 in FIG. 1, as will be described later, so that different reverberation effects can be obtained.

The reverb right channel output ROT and reverb left channel output LOT obtained as above are as follows:
They are added to the right channel direct sound R and the left channel direct sound L by adders 309 and 310, respectively, and are added to D in FIG. 1 as the right channel musical sound output and the left channel musical sound output.
/A converter 107.

The concrete operation of one embodiment of the configuration shown in FIGS. 1 to 5 will now be described in sequence. First, the CPU 10 in FIG.
1 will be explained based on the operation flowcharts of FIGS. 6 to 8. Note that the operations in FIGS. 6 to 8 are similar to C in FIG.
This is realized as a process in which the PU 101 executes a program stored in the ROM 102 using the RAM 103 as a work memory. In this case, the CPU 101 operates as shown in FIGS.
Each timer process is executed at regular intervals by a timer interrupt.

First, timer 1 processing in FIG. 6 will be explained. Here, an instruction to start generating sound to the sound source 104, settings of various weighting parameters, etc. are performed. First, keyboard information is read from the keyboard 108 via the interface circuit 109 and bus 114 (step S601).
.

Next, it is determined whether the keyboard information has changed since the last time it was read (step S602). If there is no change, no processing is performed and the timer 1 processing ends.

If a change has occurred in the keyboard information, it is determined whether the change is due to a key depression operation (step S603). If it is due to key press operation, first,
A chord chord formed by the pressed keys is detected (step S604). This detection is performed by comparing the keynotes of all pressed keys with, for example, a chord composition note table (not shown) in the ROM 102 that stores keynote groups constituting each chord. ) is detected.

Next, based on the detected code, LF
An O rate corresponding value RAT and a vibrato depth coefficient FMD are set (step S605). Regarding the settings of this LFO rate corresponding value RAT and vibrato depth coefficient FMD, for example, code names maj, min, 7th, m7
Code numbers 1, 2, 3, . . . are assigned to th, dim, aug, sus, . The smaller the code number is, the larger the LFO rate corresponding value RAT is, that is, the vibrato effect is set slower and the vibrato depth coefficient FMD is also set larger. On the other hand, the larger the code number, the smaller the LFO rate corresponding value RAT, that is, the faster the vibrato effect, and the faster the vibrato depth coefficient FM.
D is also set small. Of course, the setting can be done in the opposite way, that is, the smaller the code number, the smaller the LFO rate corresponding value RAT, while the larger the code number, the smaller the LF
The O rate corresponding value RAT may be set to be large.

[0055] Then, the LFO rate corresponding value RAT and vibrato depth coefficient FMD set in the RAM 103 as described above are transferred to the DSP 105 (step S606).

Note that in other embodiments to be described later, steps S604 and S60 shown surrounded by a broken line S600
5 and S606 are omitted, and other processes are performed in their place.

Subsequently, an empty channel is selected from the 16 sound generation channels (see the explanation of FIG. 3 above) and is set as key press channel "n" (step S607). Next, a gate flag KOn, which is a variable on the RAM 103, corresponding to key press channel "n" is set to "1". This flag is set for 16 sound generation channels, and its value is “1”.
If so, it indicates that the sound channel is in the key-depressed state. In addition, the RAM 10 corresponding to the key press channel “n”
The keynote corresponding to the pressed key is set in the keynote KNn, which is the variable above 3 (step S6
08). This keynote KNn is also provided with 16 sound generation channels.

Then, the right channel panning weighting parameter RLn, the left channel panning weighting parameter LLn, and the resonance volume weighting parameter ELn corresponding to the keynote KNn are read from the key follow table in the ROM 102 and set in the RAM 103. (Step S609). FIG. 9 shows an example of the conversion characteristics of the key follow table stored in the ROM 102. FIG. 5A shows a key follow table for right channel panning, and the higher the key note KNn indicates a key, the larger the weighting parameter RLn for right channel panning is output. FIG. 6B is a key follow table for left channel panning, and the higher the keynote KNn indicates a key, the smaller the weighting parameter LLn for left channel panning is output. Furthermore, FIG. 6(c) is a key follow table for resonance volume, and the higher the key note KNn indicates a key, the larger the weighting parameter ELn for resonance volume is output.

Then, the keynote KNn, right channel panning weighting parameter RLn, left channel panning weighting parameter LLn, and resonance volume weighting parameter ELn set in the RAM 103 as described above are transferred to the sound source 104 ( Step S6
10).

The sound source 104 time-divisionally generates digital musical tone signals for each sound generation channel using existing digital signal processing technology. Then, the outputs of each sound generation channel are multiplied by the three types of weighting parameters RLn, LLn, and ELn transferred from the CPU 101 through the above-described processing by multipliers 301, 302, and 303. 306, respectively.
Right channel direct sound R, left channel direct sound L
and output as pedal effect sending sound E.

[0061] Here, the above three types of parameters RLn
, LLn, and ELn are given based on the conversion characteristics of the key follow table shown in FIG. 9, depending on the keynote KNn to be sounded. Due to this characteristic, similar to the string arrangement of an acoustic piano, the direct sound of the left and right channels will be localized and sounded closer to the right as the key note is higher, and further to the left as the key note is lower, and the resonance sound will be louder as the key note is higher.
The lower the tone, the lower the setting.

On the other hand, if it is determined in step S603 that the change in key information is due to a key release operation rather than a key press operation, the released keynote is
The key-release channel "n" is searched for by comparing it with the keynote KNn of each sound generation channel that is currently being pressed and registered in M103 (step S611).

[0063] Then, RAM1 corresponding to that channel
The gate flag KOn on 03 is set to "0", and a key release instruction is issued to the sound source 104 (step S612).
. Next, timer 2 processing in FIG. 7 will be explained. Here, envelope data for the sound source 104 is set.

Here, first, the gate flag KOn set in the RAM 103 (see step S608 in FIG. 6)
and pedal data PD indicating the amount of depression of the pedal 110 input via the A/D converter 111 and the bus 114.
Based on this, envelope data for controlling the volume and timbre of musical tones is calculated (step S701). In other words, creation of envelope data is started for the sound generation channel whose gate flag KOn has newly become "1", and corresponds to each section of ADSR (attack, decay, sustain, release) from the start of sound generation to mute. Each value of an envelope consisting of a rate value and a target level is variably controlled based on pedal data.

[0065] The envelope data thus obtained is transferred to the sound source 104 (step S70).
2). The sound source 104 generates an envelope signal based on this, and controls the volume or tone envelope of the generated musical tone.

Next, timer 3 processing in FIG. 8 will be explained. Here, the reverb depth RVD and reverb time RVT for the DSP 105 are set. First, the amount of depression of the pedal 110 is read from the A/D converter 111 as pedal data PD, which is a variable on the RAM 103 (step S801).

[0067] Then, it is determined whether or not this pedal data PD has changed since it was last read (step S802). If there is no change, no processing is performed and the timer 3 processing is ended.

[0068] If a change occurs in the pedal data PD,
The reverb table on the ROM 102 is accessed according to the values, and the corresponding reverb depth RVD and reverb time RVT are read out and set in the RAM 103 (step S803). FIG. 10 shows an example of conversion characteristics of a reverberation table.

[0069] The reverb depth RVD and reverb time RVT thus obtained are then
5 (coefficient memory (P) 203 (FIG. 2 and FIG. 1 described later)
7) (step S804).

Here, the reverb depth RVD and reverb time RVT are supplied to comb filters 503 to 510 and multipliers 511 to 526, as explained in FIG. 5, and are calculated based on the table characteristics shown in FIG. Different reverberation sounds can be obtained by varying the amount of pedal depression. That is, the greater the amount of depression of the pedal 110, the deeper the reverberation and the longer the reverberation time. Of course, this characteristic can be changed arbitrarily.

Next, the DSP 105 of FIG. 1, 2 or 3
The operation will be explained based on the operation flowcharts of FIGS. 11 to 16. Note that these operations are realized as processing in which the DSP 105 in FIG. 1 or 2 executes a microprogram stored in the program memory 201.

[0072] Also, in each operation flowchart, for example, P
(RAT) is stored in the coefficient memory (P) 203 in FIG. 2, and the name indicates the content of the coefficient (constant) of RAT. Similarly, for example, W (SAW) and T (VW) are stored in the work memory (W) 204 and address offset memory (T) 205 in FIG. ). Here, the addresses, names, and contents of the coefficients (constants) or variables stored in each memory are as shown in FIGS. 17 to 19. Furthermore, E(E
A) is the register (
EA) 228 indicates the contents of the address specified by the address value.

First, using the operation flowcharts of FIGS. 11 to 13, the reverb effect adding section 308 of FIG.
The DSP 105 of FIG. 1 or 2 to realize the functions of
The operation will be explained.

FIG. 11 shows processing operations executed by the DSP 105 in FIG. 1 or 2 to realize the function of the triangular wave generator section 404 in FIG. 4(b). First, from the work memory (W) 204, the sawtooth LFO
The contents of the output SAW (see FIG. 18) are read out and set in the register (A0) 214 (step S1101).
). Note that the initial value of this value may be any value.

Next, from the coefficient memory (P) 203, the LFO
The contents of the rate correspondence value RAT (see FIG. 17) are read out and set in the register (A1) 215 (step S1102). The contents of the triangular wave LFO output TRI stored in the memory (W) 204 are read out to the register (M1) 213 (step S1201).

Then, in the multiplier 216, the value of the register (M0) 212 and the value of the register (M1) 213 are multiplied, and the multiplication result is stored in the register (MR) 221.
(Step S1202). As a result, Figure 4
Processing equivalent to the function of the multiplier 410 in (b) is realized.

Along with this, L of the coefficient memory (P) 203
The FO filter coefficient 1-G (the value obtained by subtracting the value G from the value 1) is read out to the register (M0) 212, and the sinusoidal LFO output SIN (
(see FIG. 18) is read out to the register (M1) 213 (also in step S1202).

Next, the result of multiplying the triangular wave LFO output TRI obtained in the register (MR) 221 by the coefficient G is transferred to the register (AR) 222 via the adder/subtractor 217 (step S1203).

Furthermore, in the multiplier 216, step S
The value of the register (M0) 212 set in step 1102 is multiplied by the value of the register (M1) 213, and the multiplication result is obtained in the register (MR) 221 (also in step S1203). As a result, the multiplier 4 in Fig. 4(b)
Processing equivalent to the function of No. 13 is realized.

Subsequently, the adder/subtracter 217 reads the register (A
The value of R) 222 and the value of register (MR) 221 are added, and the addition result is newly set in register (AR) 222 (step S1204). This content is further stored in the register (SR) 224 (step S1
205). This realizes processing equivalent to the function of the adder 411 in FIG. 4(b).

In this way, register register (SR)
The value obtained at 224 is the new sinusoidal LFO output SI
N is stored in the work memory (W) 204 (step S1206).

Next, FIG. 13 shows that in order to realize the functions of the vibrato address calculation section 406 of FIG. 4(b) and the vibrato calculation section of FIG. 4(a),
05 shows the processing operations executed by 05.

First, as explained in FIG. 3, the sound source 104
work memory (W) 20 in the DSP 105
The pedal effect sending sound E (see FIG. 18) stored in 4 (FIG. 2) is read out to the register (EO) 229. Also,
In the adder 227, the vibrato write address offset VW (see FIG. 19) read from the address offset memory (T) 205 is added to the counter value SC generated from the control circuit 202 at each sampling timing, and this added value is is set in the register (EA) 228 as the write address VWA (step S1301)
.

Next, the pedal effect sending sound E read out to the register (EO) 229 is stored in the delay memory (E) 106.
It is written to the write address VWA set in the upper register (EA) 228 (step S1302). As a result, a process equivalent to the function in which the pedal effect sending sound E is written to the delay memory 401 in FIG. 4(a) is realized.

Next, the vibrato depth coefficient FMD stored in the coefficient memory (P) 203 is stored in the register (M0).
212. In addition, the sinusoidal LFO obtained in the work memory (W) 204 by the process shown in FIG.
The output SIN is read out to the register (M1) 213 (
Step S1303).

Then, the value of the multiplier 216 and the register (M
1) is multiplied by the value of 213, and the multiplication result is obtained in the register (MR) 221 (step S1304). This realizes processing equivalent to the function of the multiplier 414 in FIG. 4(b).

Next, the integer part (higher bits) of the multiplication result obtained in the register (MR) 221 is sent to the adder/subtractor 21.
7 and the register (LF) via the register (AR) 222.
) 231. In addition, the above register (MR) 2
The value 21 is the address 08 of the work memory (W) 204.
is stored as interpolation LFO data VL (see FIG. 18) (step S1305).

Next, in the adder 227, the integer part of the multiplication result read out to the register (LF) 231 is added to the counter value SC generated from the control circuit 202 at each sampling timing, and once Register (ER)
Further, in the same adder 227, the vibrato read address offset VR (see FIG. 19) read from the address offset memory (T) 205 is added to the value of the register (ER) 232, and this addition The value is read as address VRA2 in the register (EA)
228 (step S1306). This realizes processing equivalent to the functions of adders 415 and 416 in FIG. 4(b).

Then, as described above, register (EA) 2
The delay memory (E) 106 is accessed by the read address VRA2 set to 28, and the waveform data written at the previous sampling timing (see step S1302) is read from that address and stored in the register (EI) 230. Stored (step S1307)
. This realizes processing equivalent to the function of reading data from address VRA2 of delay memory 401 in FIG. 4(a).

Furthermore, the adder 227 calculates the counter value S generated from the control circuit 202 at each sampling timing.
The integer part of the above-mentioned multiplication result read out to the register (LF) 231 is added to C, and the register (E
R) 232, and also in the adder 227,
The vibrato read address offset VR+1 (see FIG. 19) read from the address offset memory (T) 205 is added to the value of the register (ER) 232, and this added value is set in the register (EA) 228 as the read address VRA1. (also in step S13)
07). This realizes processing equivalent to the functions of adders 415 and 417 in FIG. 4(b).

Then, in step S1307, the output value from the address VRA2 obtained in the register (EI) 230 is saved in the register (A0) 214, and then set in the register (EA) 228 as described above. The delay memory (E) 106 is accessed at the read address VRA1, and the waveform data written at the previous sampling timing from that address (step S1302
reference) is read out and stored in the register (EI) 230 (step S1308). As a result, Fig. 4(a)
A process equivalent to the function of reading data from address VRA1 of delay memory 401 is realized.

The output from the address VRA1 thus obtained in the register (EI) 230 is sent to the register (A1).
) 215 (step S1309). next,
In the adder/subtractor 217, the register (A1
) 215 is subtracted, and the result of the subtraction is obtained in the register (AR) 222 (step S1310). As a result, Fig. 4(a)
) is realized.

The contents of this register (AR) 222 are further stored in the register (SR) 224 (step S1
311). Also, the interpolation LFO data VL stored in the work memory (W) 204 in the process of step S1305
The decimal part (lower bit) of is read out to the register (M0) 212 (also in step S1311).

Then, in the multiplier 216, the value of the register (M0) 212 is multiplied by the difference value obtained in the register (SR) 224, and the multiplication result is stored in the register (
MR) 221 (step S1312). This realizes processing equivalent to the function of the multiplier 404 in FIG. 4(a).

At the same time, the address VRA2 stored in the register (A0) 214 in step S1308
The output value from is transferred to the register (A1) 215 (also in step S1312).

Then, in the adder/subtracter 217, the value of the register (MR) 221 and the register (A1) 21
5 is added, and the addition result is stored in the register (AR
) 222 (step S1313). This realizes processing equivalent to the function of the multiplier 403 in FIG. 4(a).

The addition result obtained in the register (AR) 222 is stored at address 0 of the work memory (W) 204.
9 as the vibrato output VO (see FIG. 18) (step S1314).

As described above, the DSP 10 of FIG. 1 or 2
5 repeats the program of the processing shown in the operation flowcharts of FIGS. 11 to 13 at each sampling timing, so that the vibrato effect adding section 3 of FIG. 3 or FIG.
07 functions are realized.

Next, using the operation flowcharts of FIGS. 14 to 16, the reverb effect adding section 308 of FIG.
The DSP 105 of FIG. 1 or 2 to realize the functions of
The operation will be explained.

FIG. 14 shows the all-pass filter 50 of FIG.
In order to realize the function of 1, the DSP 10 of FIG. 1 or 2
5 shows the processing operations executed by 5. First, the adder 227 adds the read address offset AR1 (
(see FIG. 19) is added, and this added value is set in the register (EA) 228 as an address value (step S
1401).

Next, as described above, the register (EA) 22
Delay memory (E) 10 with address value set to 8
6 is accessed, and the waveform data written at the previous sampling timing is read from that address.
stored in the register (EI) 230 (step S14
02).

Next, the above-mentioned waveform value stored in register (EI) 230 is transferred to register (M1) 213 and register (A0) 214. At the same time, the coefficient value 0.5 is read from the coefficient memory (P) 203 and set in the register (M0) 212 (step S
1403).

[0103] Then, in the multiplier 216, the value of the register (M0) 212 to which the above-mentioned coefficient value 0.5 is set, and the register (M1) 213 to which the waveform value from the delay memory (E) 106 is set. is multiplied by the value of , and the value is set in the register (MR) 221 (step S
1404).

[0104] Through the operations in steps S1401 to S1404 described above, in the all-pass filter 501 of FIG. Processing equivalent to the function is realized.

At the same time, the vibrato output VO generated by the processing in the vibrato effect adding section 307 described above is read out from the work memory (W) 204 and set in the register (A1) 215 (also in step S1).
404).

Next, in the adder/subtractor 217, the vibrato output V set in the register (A1) 215 described above is
The value of O is set to the register (
The value of MR) 221 is added, and this added value is stored in the register (
AR) 222 (step S1405). Then, the addition result of this register is transferred to the output register (SR) 224 (step S1406). As a result, the adder 5 of the all-pass filter 501 in FIG.
Processing equivalent to the function of No. 32 is realized.

Subsequently, the value of the register (SR) 224 is stored in the register (EO) 229. Also, in the adder 227, the write address offset AW1 of the all-pass filter 501 is read from the address offset memory (T) 205 into the sampling counter value SC.
is added and set in the register (EA) 228 (step S1407).

At the same time, the multiplier 216 outputs a coefficient value of 0.
The value of the register (M0) 212 set to 5 and the register (SR) 22 set in step S1406
4 and the value is stored in the register (MR) 221.
(also in step S1407). As a result, the multiplier 531 of the all-pass filter 501 in FIG.
Processing equivalent to the processing in is realized.

Furthermore, the delay memory (E) 106 stored in the register (A0) 214 in step S1403
The waveform data of the previous sampling timing from
is transferred to the register (A1) 215 (also in step S).
1407).

Next, in step S1407, the register (E
The value set in O) 229 is stored in the delay memory (E) 106 using the value stored in the register (EA) 228 calculated in step S1407 as an address (step S1408). As a result, the output of the adder 532 of the all-pass filter 501 in FIG.
Processing equivalent to the functions stored in 29 is realized.

Further, in the adder/subtractor 217, the multiplication result also obtained in the register (MR) 221 is subtracted from the waveform data set in the register (A1) 215 in step S1407, and the result is stored in the register (AR) 22.
2 (also in step S1408), and the register value is further transferred to the output register (SR) 224 (step S1409). Thereby, processing equivalent to the function of the adder 533 of the all-pass filter 501 in FIG. 5 is realized.

Finally, the output result obtained in the register (SR) 224 described above is stored in the work memory (W) 204 as data AO1 (step S1410). As a result, the output signal AO1 of the all-pass filter 501 in FIG. 5 is obtained.

As described above, the DSP 10 of FIG. 1 or 2
5 repeats the processing program shown in the operation flowchart of FIG. 14 at each sampling timing, thereby realizing the function of the all-pass filter 501 of FIG.

Next, in order to realize the function of the all-pass filter 502 in FIG. 5, the DSP 105 may execute a program similar to the operation flowchart in FIG. 14 on the output AO1 of the all-pass filter 502. , As a result, the output AO to the work memory (W) 204
2 is obtained (see FIG. 18).

Next, FIG. 15 shows the comb filter 5 of FIG.
In order to realize the function of 03, DSP1 of FIG. 1 or 2
05 shows the processing operations executed by 05. First, the adder 227 adds the right channel read address offset CRR1 (see FIG. 19) of the comb filter 503 read from the address offset memory (T) 205 to the counter value SC generated from the control circuit 202 at each sampling timing. is added, and this added value is set in the register (EA) 228 as an address value (
Step S1501).

Next, as described above, the register (EA) 22
Delay memory (E) 10 with address value set to 8
6 is accessed, and the waveform data written at the previous sampling timing is read from that address.
It is stored in the register (EI) 230 as waveform data for the right channel (step S1502).

Next, the adder 227 adds the counter value S generated from the control circuit 202 at each sampling timing.
The left channel read address offset CLR1 of the comb filter 503 read from the address offset memory (T) 205 is added to C, and this added value is set in the register (EA) 228 as an address value (
Step S1503).

[0118] Also, in step S1503, the register (E
I) The waveform data for the right channel set in 230 is moved to the register (M0) 212, and is also stored as the right channel output CRO1 of the comb filter 503 at address 0C shown in FIG. 18 of the work memory (W) 204. (Same as step S1503). This results in
Processing equivalent to the function in which the right channel output CRO1 is output from the delay element 534 of the comb filter 503 in FIG. 5 is realized.

Furthermore, the reverb time RVT is read out from the coefficient memory (P) 203 (see FIG. 17) and set in the register (M1) 213 (also in step S15).
03).

Next, in step S1503, the register (E
A) The delay memory (E) 106 is accessed with the address value for the left channel set to 228, the waveform data written at the previous sampling timing is read from that address, and the left channel data is stored in the register (EI) 230. It is stored as waveform data for the channel (step S1504).

[0121] Next, in the multiplier 216, step S15
The waveform data for the right channel set in the register (M0) 212 in 03 and the same register (M1) 213
is multiplied by the set reverb time RVT, and the multiplication result is stored in the register (MR) 221 (step S1504). Thereby, processing equivalent to the function of the multiplier 535 of the comb filter 503 in FIG. 5 is realized.

At the same time, the output AO2 of the all-pass filter 502 (FIG. 5) stored in the work memory (W) 204 is read out to the register (A1) 215 (also in step S1504).

Next, in step S1504, the register (E
I) The waveform data for the left channel set in 230 is sent to the output C for the left channel of the comb filter 503 at address 14 shown in FIG. 18 in the work memory (W) 204.
It is stored as LO1 (step S1505). As a result, the delay element 534 of the comb filter 503 in FIG.
Processing equivalent to the function in which the left channel output CLO1 is outputted from is realized.

[0124] Also, in the adder/subtractor 217, the multiplication result obtained in the register (MR) 221 in step S1504 and the output AO2 of the all-pass filter 502 stored in the register (A1) 215 in step S1504 are added. The result is obtained in the register (AR) 222 (step S1503). Then, the register value is stored in the output register (SR) 224 (step S1506). As a result, the comb filter 5 in FIG.
Processing equivalent to the function of the adder 536 of No. 03 is realized.

Next, the adder 227 adds the address offset memory (T) to the sampling counter value SC.
The write address offset CW1 of the comb filter 503 read from the comb filter 205 is added to the register (EA).
Set to 228. In addition, register (SR) 224
The above-mentioned addition result stored in register (EO) 229
(step S1507).

Then, the value set in the register (EO) 229 is stored in the delay memory (E) 106 using the value stored in the register (EA) 228 as an address (step S1508). As a result, the output of the adder 536 of the comb filter 503 in FIG.
Processing equivalent to the functions stored in .34 is realized.

As described above, the DSP 10 of FIG. 1 or 2
5 repeats the processing program shown in the operation flowchart of FIG. 15 at each sampling timing, thereby realizing the function of the comb filter 503 of FIG.

Next, other comb filters 504 to 5 in FIG.
In order to realize the 10 functions, the DSP 105 only needs to execute a program similar to the operation flowchart in FIG. 15 on the output AO2 of the all-pass filter 502. Comb filter right channel outputs CRO2 to CRO8 and left channel outputs CLO2 to CLO8 are obtained (see FIG. 18).

Finally, FIG. 16 shows the multipliers 511 to 511 of FIG.
3 illustrates the processing operations performed by the DSP 105 of FIG. 1 or 2 to implement the accumulation function by the accumulator 518 and the accumulator 527.

First, the reverb depth RVD corresponding to the weighting coefficient multiplied by each channel output from each comb filter is read from the coefficient memory (P) 203 and set in the register (M0) 212. Further, the right channel output CRO1 of the comb filter 503, which has been determined based on the operation flowchart in FIG. 15, is read from the work memory (W) 204 and set in the register (M1) 213 (step S1601). .

Next, in the multiplier 216, the register (M0)
The reverb depth RVD set in 212 is multiplied by the right channel output CRO1 of the comb filter 503 set in the register (M1) 213, and the multiplication result is set in the register (MR) 221 (step S
1602). Thereby, processing equivalent to the function of multiplier 511 in FIG. 5 is realized.

Further, the right channel output CRO2 of the comb filter 504 is read out from the work memory (W) 204 to the register (M1) 213 (also in step S1).
602).

Next, after the contents of the register (MR) 221 are transferred to the register (AR) 222, the multiplier 216
Then, the reverb depth RV set in the register (M0) 212 is set to the right channel output CRO2 of the comb filter 504 set in the register (M1) 213 above.
D is multiplied, and the multiplication result is stored in the register (MR) 221.
(Step S1603). As a result, Figure 5
Processing equivalent to the function of the multiplier 512 is realized.

[0134] Below, each comb filter 505 to 51 in FIG.
Regarding the right channel outputs CRO3 to CRO8 of 0,
Similarly, the reverb depth RVD is multiplied. Then, each multiplication result obtained in the register (MR) 221 is sequentially accumulated in the adder/subtractor 217 to the accumulated value obtained in the register (AR) 222, and a new register (AR) is added.
)222 (steps S1604 to S161
0). In this way, processing equivalent to the functions of multipliers 513 to 518 and accumulator 527 in FIG. 5 is realized.

The reverb depth RVD is weighted on the right channel outputs CRO1 to CRO8 of the comb filters 503 to 510, and the cumulative results are stored in the register (AR
) 222, its contents are stored in the output register (
SR) 224 (step S1611), and the contents of the register (SR) 224 are transferred to the reverb right channel output RO at address 1D in FIG. 18 of the work memory (W) 204.
It is stored as T (step S1612).

[0136] Then, this reverb right channel output R
OT is set in the signal output register (OR) 225, and is output as the reverb right channel output ROT from the reverb effect adding section 308 in FIG.
Step S1613).

As described above, the DSP 105 of FIG. 1 or 2
However, by repeating the processing program shown in the operation flowchart of FIG. 16 at each sampling timing, the accumulation function of the multipliers 511 to 518 and accumulator 527 of FIG. 5 is realized.

Next, in order to realize the accumulation function by the multipliers 519 to 526 and the accumulator 528 in FIG.
105 may execute a program similar to the operation flowchart in FIG. The reverb left channel output LOT is obtained at address 1E, and is set in the signal output register (OR) 225, thereby being output as the reverb left channel output LOT from the reverb effect adding section 308 in FIG.

As described above, the DSP 10 of FIG. 1 or 2
5 repeats the processing program shown in the operation flowcharts of FIGS. 14 to 16 at each sampling timing, thereby creating the reverb effect adding section 30 of FIG. 3 or FIG.
8 functions are realized.

Finally, the operation of the DSP 105 in FIG. 1 or 2 to realize the functions of the adders 309 and 310 in FIG. 3 will be explained. That is, in the DSP 105 of FIG. 2, first, as described above, the right channel direct sound R obtained from the sound source 104 in the work memory (W) 204 in the DSP 105 is read out to the register (A0) 214, and the Similarly, the work memory (W) is
) 204 is read out to the register (A1) 215. Then, in the adder/subtracter 217, the contents of both registers are added, and the result of the addition is the register (AR) 222 and the register (S).
After being stored as the right channel musical tone output ROUT at address 1F of the work memory (W) 204 via the R) 224, it is transferred to the output register (OR) 225, and from the same register to the D/A converter 107 in FIG. Output. Thereby, processing equivalent to the function of adder 309 in FIG. 3 is realized.

Similarly for the left channel, the left channel direct sound L from the sound source 104 on the work memory (W) 204 and the reverb left channel output LOT are added by the adder/subtractor 217, and the addition result is stored in the work memory. (W) Left channel musical tone output L to address 20 of 204
After being stored as OUT, the output register (OR) 22
5 and from the same register to the D/A converter 10 in FIG.
7 is output. Thereby, processing equivalent to the function of adder 310 in FIG. 3 is realized.

In the above embodiments, the value of the vibrato depth coefficient FMD, which controls the range of change in the depth of the vibrato effect, and the value of the LFO, which controls the range of change in the speed of the vibrato effect.
The rate correspondence value RAT is automatically changed and set according to the type of chord detected based on the keynote of the performance information. That is, the vibrato effect is configured so that the depth and speed of the vibrato effect change in conjunction with key depressions of chord tones on the keyboard. On the other hand, the value of the vibrato depth coefficient FMD and the value of the LFO rate corresponding value RAT may be configured to change depending on the amount of pedal depression, as in the case of the reverb effect. Specific operations of other embodiments configured in this manner will be described below.

First, the structure is exactly the same as the structure of FIGS. 1 to 5 in the above-described embodiment. Next, regarding the specific operations, among the processes explained in the CPU operation flowcharts of FIGS. 6 to 8, the processes of steps S604, S605, and S606 surrounded by the broken line S600 of the timer 1 process in FIG. is not executed, and timer 3 in FIG.
The process is replaced by the timer 3 process in FIG. The operation of this part will be explained below. It should be noted that explanations of the configuration and operation of the same parts as those of the above-mentioned embodiments will be omitted.

Timer 3 in another embodiment shown in FIG.
In the process, steps S2001 to S2003 are the same as steps S803 to S803 in the timer 3 process of the embodiment shown in FIG.

[0145] In step S2003 of FIG.
As described in the above embodiment, the reverb table on the ROM 102 is accessed in accordance with the changed value of the pedal data PD, and the corresponding reverb depth RVD and reverb time RVT are read out and set in the RAM 103. .

[0146] Similarly, in accordance with the changed value of the pedal data PD, a vibrato table (not particularly shown) on the ROM 102 is accessed, the corresponding vibrato depth coefficient FMD and LFO rate corresponding value RAT are read out, and the corresponding value RAT is read out from the RAM 103. (Step S2004
). This vibrato table is similar to the reverb table shown in FIG.
The rate correspondence value RAT is configured to correspond to the reverb time RVT shown in the figure.

[0147] Next, in this way, the above step S2
Reverb depth RVD obtained with 003 and S2004
, reverb time RVT, vibrato depth coefficient FMD, and LFO rate corresponding value RAT are transferred to the coefficient memory (P) 203 in the DSP 105 (step S2005).
).

Here, the reverb depth RVD and the reverb time RVT are supplied to the comb filters 503 to 510 and the multipliers 511 to 526, as explained in FIG. 5, and are calculated based on the table characteristics shown in FIG. Different reverberation sounds can be obtained by varying the amount of pedal depression. That is, as described in the above embodiment, the greater the amount of depression of the pedal 110, the deeper the reverberation and the longer the reverberation time.

[0149] Also, the vibrato depth coefficients FMD and LF
As explained in FIG. 4, the O rate corresponding value RAT is supplied to the multiplier 414 of the vibrato address calculation section 406 and the adder 408 of the triangular wave generator section 404, and this is used to generate a vibrato signal similar to the reverberation table of FIG. 10 described above. Different fluctuation effects can be obtained by varying the amount of pedal depression based on the table characteristics determined by the table used. That is, the greater the amount of depression of the pedal 110, the deeper the fluctuation and the longer the fluctuation time. In this case, the right pedal may control the vibrato effect, and the left pedal may control the reverb effect. Of course, the opposite is also possible.

[0150] Thus, according to the other embodiments described above,
The vibrato effect can be controlled by information on the amount of depression from the pedal 110. Note that the operation of the DSP 105 in FIG. 1, FIG. 2, or FIG. 3 in this embodiment is also exactly the same as that described based on the operation flowcharts in FIGS. 11 to 16.

[0151]

According to the present invention, by modulating the original musical tone signal from the sound source means used for generating reverberant sound in the reverberant sound generating means with the modulating means, the acoustic piano can be controlled by using the operating means. Similar to the pedal effect, it is possible to add a fluctuation or undulating effect to the resonance sound.

[0152] Therefore, it is possible to obtain a resonance sound effect with fluctuations and undulations even by key operation, and it is also possible to obtain a more realistic and pleasant pedal effect.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a DSP.

FIG. 3 is a block diagram of the operating principles of the sound source and DSP.

FIG. 4 is a block diagram of the operating principle of a vibrato effect adding section.

FIG. 5 is a block diagram of the operating principle of the reverb effect adding section.

FIG. 6 is an operation flowchart of timer 1 processing by the CPU.

FIG. 7 is an operation flowchart of timer 2 processing by the CPU.

FIG. 8 is an operation flowchart of timer 3 processing by the CPU.

FIG. 9 is a diagram showing a key follow table.

FIG. 10 is a diagram showing a reverb table.

FIG. 11 is an operation flowchart of the triangular wave generator section.

FIG. 12 is an operation flowchart of the LPF unit.

FIG. 13 is an operation flowchart of the vibrato calculation section.

FIG. 14 is an operation flowchart of a DSP that implements the function of an all-pass filter in a reverb effect adding section.

FIG. 15 is an operation flowchart of the DSP that implements the comb filter function of the reverb effect adding section.

FIG. 16 is an operation flowchart of the DSP that implements the right channel accumulation operation in the reverb effect adding section.

FIG. 17 is a diagram showing a coefficient memory map.

FIG. 18 is a diagram showing a work memory map.

FIG. 19 is a diagram showing an address offset memory map.

FIG. 20 is an operation flowchart of another embodiment of timer 3 processing by the CPU.

[Explanation of symbols]

101 CPU 102 ROM 103 RAM 104 Sound source 105 DSP 106 Delay memory 108 Keyboard 110 Pedal

Claims (7)

[Claims] 1. Sound source means for generating a musical tone signal in accordance with performance information; modulation means for modulating either the frequency or the phase of the original musical tone signal generated from the sound source means;
Reverberant sound generating means generates reverberant sound by adding a reverberation effect to the musical sound signal modulated by the modulator, and generates operation information for controlling the volume of the reverberant sound based on an operation by a performer. an operating means; a reverberation volume control means for controlling the volume of the reverberant sound generated by the reverberant sound generating means according to operation information from the operating means; An electronic musical instrument having a built-in pedal effect adding device, characterized in that it has an addition means for adding to a generated original musical tone signal and outputting it as a musical tone output signal. 2. The pedal effect addition according to claim 1, further comprising reverberation time control means for controlling the reverberation time of the reverberation sound generated by the reverberation sound generation means in accordance with operation information from the operation means. An electronic musical instrument with a built-in device. 3. Pedal effect addition according to claim 1, further comprising modulation characteristic control means for controlling the modulation characteristics of the musical tone signal modulated by the modulation means in accordance with operation information from the operation means. An electronic musical instrument with a built-in device. 4. The musical tone signal according to claim 1, further comprising modulation characteristic control means for controlling the modulation characteristics of the musical tone signal modulated by the modulation means in accordance with the performance information.
An electronic musical instrument with a built-in pedal effect adding device as described above. 5. The pedal effect adding device according to claim 4, wherein the performance information used by the modulation characteristic control means to control the modulation characteristic is information indicating a type of played chord. An electronic musical instrument with a built-in 6. An electronic musical instrument incorporating a pedal effect adding device according to claim 1, wherein said operating means is a pedal operating means. 7. Claims 1, 2, 3, 4, 5, further comprising a keyboard for generating the performance information.
Or an electronic musical instrument incorporating the pedal effect adding device described in 6.