JPH04211831A - Program verifying method, and trace data displaying method and compiling method for the same - Google Patents

Abstract

PURPOSE:To offer a method for checking the reference relation of array data and verifying propriety for parallel processing or vector processing by executing an objective program, and the method for displaying intelligibly the result of this verification. CONSTITUTION:The propriety for the parallel processing or the vector processing is verified by inputting array access information 512 obtained by executing the object program, and comparing access identifiers included in old reference information and newly read reference information with each other for the same array element by a processing part 520, and the result is displayed on a display device after a display color is determined by a display color determining part 526 in order to display the result so as to be easy to understand.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying a program, and a program verification tool and compiler for the method.

In particular, a method for detecting the possibility of unauthorized reference to array data during execution of a program aimed at parallel processing or vector processing and verifying the appropriateness of the corresponding source program, and a method useful for executing the method. Regarding program verification tools and compilers.

0003

2. Description of the Related Art When a user program is executed on a parallel computer or a vector computer, one of the causes of failures that often occur is incorrect references to array data (that is, changes in the order of definition and reference).

[0004] A compiler that has a function of automatically finding parts that can be executed on a parallel computer or a vector computer from a source program for sequential execution has a function of automatically finding parts that can be executed on a parallel computer or vector computer from a source program for sequential execution. It is determined whether the source program can be parallelized or vectorized by analyzing whether the loop is repeated. However, if there is a variable whose value is determined during execution within an array index, it is not possible to determine which array element it is during compilation. In this case, the compiler cannot determine whether to parallelize or vectorize the program, so it usually parallelizes the program according to user instructions. However, this method often causes poor execution results due to incorrect instructions.

Furthermore, in a program written in a language that can describe parallel processing, errors in the user's description are likely to occur. It is possible to detect this error by checking the reference relationships of array data by the compiler, but as mentioned above, not all cases are revealed by analysis at compile time, so it may still cause poor execution results. be.

A conventional method for checking and displaying the access pattern to array data when a program is executed is ``Parallel Computing9 (1
988/89) 25-35. This method is aimed at verifying algorithms for high-performance computers, and displays the access order of definitions and citations in separate windows when a sequential execution program is executed.

[0007]

[Problems to be Solved by the Invention] The above-mentioned prior art does not take into consideration programs to be executed on parallel computers or vector computers. That is, from the viewpoint of debugging, no consideration is given to checking the possibility of unauthorized reference to array data. Therefore, a method is needed to check the reference relationships of array data and verify whether a program is suitable for parallel processing or vector processing. Additionally, a method for displaying verification results in an easy-to-understand manner and a program verification tool and compiler for this purpose are also required.

[0008] Programs intended to be executed on parallel computers or vector computers are generally debugged using these target computers. However, using these high-performance computers for debugging has a problem in terms of computer utilization efficiency.

A first object of the present invention is to provide a method for checking the reference relationships of array data during execution of an object program and verifying whether the corresponding source program is suitable for parallel processing or vector processing.

A second object of the present invention is to provide a method for displaying the verification results in an easy-to-understand manner.

A third object of the present invention is to provide a compiler for compiling a source program intended to be executed on a parallel computer or vector computer.

0012

[Means for Solving the Problems] In a first aspect of the characteristics of the present invention, numbers are assigned to a plurality of parallel processes as parallel processing units, and the number of the parallel process in which an array element is defined and the number of the parallel process in which the array element is The possibility of an illegal reference to the array element is determined based on whether the two match. This allows the possibility of parallel processing of the program to be verified.

In addition, in a second aspect of the characteristics of the present invention, the vectorized statements are numbered in order, and the vectorized statement number in which the array element to be inspected is defined, and the vectorized statement in which the array element is cited are assigned numbers. The statement number is compared and the possibility of an illegal reference to the array element is determined based on the size of both. This allows the vector processing capability of the program to be verified.

[0014] Furthermore, in a third aspect of the characteristics of the present invention,
Display areas corresponding to a plurality of array elements are arranged in a one-dimensional or two-dimensional matrix, and data indicating the possibility of unauthorized reference to the corresponding array element is displayed in each display area.

According to a fourth aspect of the characteristics of the present invention, the access type indicating whether an array element is defined or cited, the subscript value, and the accessed parallel process number or vectorized source statement number are used as array access information. input as information and compare the parallel process number or vectorization source statement number in which the array element was defined with the parallel process number or vectorization source statement number in which the array element was cited,
A program verification tool that can verify the parallelism or vectorability of a program and a compiler that allows the program verification tool to obtain the array access information from a source program are provided.

[0016]

[Operation] In order for parallel processing to be possible, correct results must be obtained even if parallel processes are executed in any order. This means that each array element must be defined and referenced in the same parallel process. By detecting that the parallel process number at the time of definition and the parallel process number at the time of quotation are different, it is possible to detect the possibility of unauthorized reference to array data. That is, from the first viewpoint, it is possible to verify the suitability of a program for parallel processing.

On the other hand, when vector processing is performed, the reference order of each array element is in the order of the vectorization source statement number, so in order for the definition to come before the quotation, the source statement number at the time of quotation of a certain array element must be must be greater than the source statement number at the time the array element was defined. By comparing the size of the source statement number at the time of quotation and the source statement number of the definition, it is possible to detect the possibility of illegal reference to array data. That is, from the second viewpoint, it is possible to verify whether a program is suitable for vector processing.

In the trace data display method according to the third aspect, the possibility of unauthorized reference to each array element is displayed in a matrix arrangement on the screen. Therefore, it becomes possible to understand at a glance which array element is the cause of inhibiting parallel processing or vector processing.

Since the program verification tool and compiler of the present invention according to the fourth aspect can operate on a sequential computer, a source program intended to be executed on a parallel computer or a vector computer can be debugged using a sequential computer. It becomes possible to do so.

[0020]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited thereby.

FIG. 1 shows the configuration of a sequential computer system for converting a source program into a load module and executing it. The sequential computer system has 10 CPUs and 1 memory.
2, external storage device 14, display device 16, keyboard 18
It consists of The device 14 has a source program 100
and a compiler 200 according to the present invention are stored. FIG. 3 shows a functional block diagram of the sequential computer system. Source program 100 and compiler 200 stored in device 14 are loaded into memory 12 . Compiler 2
00 is executed by the CPU 10, and the source program 1
00 is converted to the load module 300 depending on the name of the array to be inspected input by the user, and the memory 12
is stored in After that, the load module 300
It is stored in 4.

[0022] The compiler 200 uses a loop dividing unit 230
, an access information addition section 210, and a code generation section 220
It has

When the source program 100 is intended for parallel processing, 230 divides the part of the source program 100 to be parallel processed into a plurality of parallel processing units.
0 allocates an access identifier indicating the parallel processing unit to the element of the array to be inspected specified by the user within each parallel processing unit. For example, 230 converts loop 40 in FIG. 13 to loop 41. If the number of divisions ND for parallel processing is 4, the loop 41 is equivalent to the loops 40a to 40d. 210 assigns access identifier #1 to the elements of array A defined by statement 41a in loop 40a of parallel process number #1 and to the elements of array A referred to by statement 42a. Similarly, parallel process numbers #2, #3, #4
Access identifiers #2, #3, and #4 are assigned to elements of array A defined and referenced in loops 40b, 40c, and 40d, respectively.

Next, the code generation unit 220 generates an object code for outputting the access information record to the array access information file 400 every time an element of the array to be inspected is defined or cited, and adds it to the object program. and outputs it to the load module 300. It may also be added to the object program during compilation. The access information record includes the access identifier, the value and subscript of the array element to be accessed, and the statement number of the source program.

As described above, when the execution of the load module 300 output from the compiler 200 is completed, an array access information file 400 storing access information records regarding the array data is created and stored in the storage device 2.
6.

Each record of the file 400 has a data format as shown in FIG. Field 410 stores the order in which the elements of array data are accessed. Field 420 stores an access type indicating whether it is a definition or a quotation. Field 430 stores array subscript values for each dimension. Field 440 stores an access identifier. Field 450 stores the statement number of the source program. Field 460 stores the value of the accessed array element.

The file 400 is a trace data display tool 5 including a program verification tool according to an embodiment of the present invention.
00 from the storage device 14 of the single computer system to the memory 12 and executed. This allows the parallel computer system to be used for other processing.

FIG. 6 shows a tool 500. The tool 500 includes an array information input section 510 and an array access information processing section 520.
have. The section 510 inputs the records of the file 400 in the order of access numbers in the field 410, and the section 520
give it to

As shown in FIG. 8, the unit 520 includes an access identifier comparing unit 522 and an access identification information updating unit 524.
, a display color determining section 526 , and a storage 528 for storing an access identifier. The storage 528 has entries corresponding to array elements, and stores the access identifier and access identification of the accessed array element in the corresponding entry. This stored access identifier is expressed as PREID and has an initial value of 0.

The unit 520 operates according to the flowchart shown in FIG. 9 for programs intended to be executed on parallel computers.

In these flowcharts, step 522
a to 522e perform the processing by the unit 522 in step 524.
a performs the processing by the unit 524 in steps 526a to 526.
c indicates processing by the unit 526.

Next, the operation of the program intended to be executed on the parallel computer shown in FIG. 9 will be explained.

First, an embodiment of the program verification method of the present invention for a source program intended to be executed on a parallel computer will be described with reference to FIGS. 11 to 14.

Computing the loop 30 shown in FIG. 11 in parallel means that the loop 30 is
30d, and these divided loops 30a, 30b
, 30c, and 30d in parallel. At this time, if definitions and references to the same array element exist across the divided loops, the original order of definitions and references may be reversed. This is because even though it is called parallel execution, each divided loop is not necessarily executed at the same time depending on the idle state of the processor.

Furthermore, even if definitions for the same element exist in different loops of the divided loops, the final value of that element may change depending on the state of the processor. Therefore, these two cases can be executed correctly on a parallel computer.

FIGS. 12A to 12E show the loop 30 in FIG. 11 when the input variable K=0, and the loops 30a and 30.
It shows the relationship between definitions and references of elements of array A in b, 30c and 30d. Element A(I)d of array A represents a definition, and element A(I)u of array A represents a citation. In any of the loops 30, 30a, 30b, 30c, and 30d, each element of the array A is defined/quoted only in the same loop, and there is no definition/quotation relationship between different loops. Therefore, loop 30 can be correctly executed on a parallel computer.

Next, executing the loop 40 of FIG. 13 means that the loop 40a, which is obtained by dividing it,
This is equivalent to executing 40b, 40c, and 40d in parallel.

FIGS. 14(A) to (D) Loop 40 and array A in loops 40a, 40b, 40c, and 40d
It shows the relationship between definitions and citations of elements. In this case, the same element is defined and referenced between different loops. Therefore, there is a possibility that illegal references may occur due to parallel execution.

In general, if an array subscript is complex and includes a variable whose value is determined by an input statement at runtime, this reference relationship is not known until execution, so it is necessary to check at compile time whether it can be executed correctly on a parallel computer. It is not easy to judge. Therefore, we converted the original program into a program equivalent to dividing the parallel target part (for example, a loop) into parallel processing units and arranging them in an arbitrary order, and then executed the program sequentially on a computer so that the definitions and references of each array element were the same. The above reference relationship can be easily checked by checking whether it occurs in a parallel processing unit, in a different parallel processing unit, or in parallel processing units with different definitions.

In other words, check whether the parallel process number (number given to a parallel processing unit) at the time of quoting each array element is the same as the parallel process number at the time of definition, or whether the parallel process numbers at each definition are the same. By doing so, it is possible to verify the possibility of parallel processing of the program.

In step 522b of FIG. 9, the old access identifier PREID and the old access type are read from the entry in the access identifier storage storage 528 that has the same subscript value as they correspond to the input array element to be processed.

In step 522d, it is determined whether PREID=0. If PREID=0, that is, the value of the array element currently being processed has not been defined or referenced yet,
Proceed to step 524a. PREID≠0, i.e.
If the value of the array element currently being processed has already been defined or referenced, the process proceeds to step 522e. Step 5
In step 22e, it is determined whether the new and old access types are both quotation. If both are citations, the process advances to step 522a. If neither is a citation, the process advances to step 522c. In step 522c, it is determined whether the new access identifier NOWID and the old access identifier PREID of the array element currently being processed are equal. If different, proceed to step 526a. If they are equal, the process proceeds to step 522a.

In step 524a, the access identifier NOWID and the access type of the array element currently being processed are stored in the corresponding storage 528 entry. The process then proceeds to step 522a. In step 522a, the access type of the array element currently being processed is determined. If the type is definition, the process advances to step 526c. If the type is citation, the process advances to step 526b.

In step 526a, it is determined that the array element currently being processed is to be displayed in color C and with high brightness for a short period of time. Color C indicates elements whose access identifiers do not match when defined or cited. In other words, this indicates that the element may be referenced illegally. The reason why it is displayed with high brightness for a short time is to indicate that the array element is currently being processed. Meanwhile, step 526b
Now, it is decided to display the array element currently being processed in color B and with high brightness for a short period of time. Color B is
Indicates that the element is quoted. In step 526c, it is determined that the array element currently being processed is to be displayed in color A and with high brightness for a short period of time. Color A indicates a defined element.

The above operation is performed in a loop 700 shown in FIG.
This will be specifically explained using the case of K:1.

When loop 700 is parallelized by DO 200, the compiler converts it into loop 701 using division number ND, and outputs access information by executing the following for statements 7010a and 701b in the loop in FIG. 810,
820 is added to the object code. At this time, it is assumed that the source sentence numbers 701a and 702b are n and n+1, respectively. For the array element A (I, J) to be inspected in 701a, the access type "DEF" indicating that it is a definition, the subscript values I, J, the source statement number n, and the value of the array element are used as trace data. Generate code to output. For A(I, J-K) of 701b,
A code is generated that outputs the access type "USE" indicating use, the subscript values I, J-K, the source statement number n+1, and the array element value as trace data. For convenience of explanation, it is assumed that ND=4, and loops 700a, 700b, 700c, and 700d corresponding to loop 701 will be explained. The array element is A(I, J).

FIG. 17(A) shows the first loop 700a.
The contents of the storage 528 are shown at the time when the execution of the process is completed. Since all access identifiers in the entries in storage 528 are initialized with the value 0, loop 700a
All entries corresponding to array elements that are not accessed by execution of are set to 0. On the other hand, loop 700
All entries corresponding to array elements accessed by execution of a are set to 1. u and d are defined respectively,
Show citation.

An example of the screen display at this time is shown in FIG. 17(B). In the figure, color A (defined element) is indicated by a diagonal line going up to the right, color B (quoted element) is indicated by a line downward to the right, and color C (
(Elements that may be referenced illegally) are shown with mesh. In addition, high-intensity display is indicated with a thick frame. FIGS. 18(A) and 18(B) are
This is an example of the contents of the storage 528 and the screen display at the time when the statement 702b is executed when I=1 and J=3. Sentence 702
The array element accessed by executing b is A(1,3)
Therefore, in step 522b of FIG.
Access identifier PREID from entry (1, 3) of 8
is read and the initial value is 0, so step 522
d, the process proceeds to step 524a. The access type of the array element A (1, 3) currently being processed is "definition" and the access identifier NOWID is the parallel process number #2 of the loop 700b. Therefore, in step 524a, the storage 52
Access identifier 2 and access type "definition" are set in entry (1, 3) of No. 8. and step 526c
As a result, element A (1, 3) is displayed in color A with high brightness for a short time.

FIGS. 19(A) and 19(B) show I=1, J=3
The storage 52 at the time when statement 703b was executed
This is an example of the content and screen display of item 8. Since the array element accessed by executing statement 703b is A(1,2), the entry (
1, 2), the old access identifier PREID=1 and the old access type "definition" are read, and the old access identifier PR
Since the EID is not 0, the process proceeds from step 522d to step 522e. The access identifier NOWID of the element A (1, 2) currently being processed is the parallel process number #2 of the loop 700b, and the access type is quotation. Therefore, since the new and old access types are different, step 522c
Proceed to.

At step 522c, this access identifier NOWID=2 and the old access identifier PREID=1 are compared, and since they do not match, the process proceeds to step 526a. Then, in step 526a, element A(1,3) is displayed in color C with high brightness for a short time. Color C indicates that there is a possibility of unauthorized reference.

FIGS. 20(A) and 20(B) show I=2, J=3
The storage 52 at the time when the statement 702b is executed
This is an example of the content and screen display of item 8.

FIGS. 21(A) and 21(B) show I=2, J=3
The storage 52 at the time when statement 703b was executed
This is an example of the content and screen display of item 8.

[0053] As a result of similar processing, loop 70
The contents of the storage 528 and the screen display at the time when 0b ends are as shown in FIGS. 22(A) and 22(B). Element A (
Since I, 2) and element A (I, 6) are displayed in color C on the screen, it is clear that there is a possibility of unauthorized reference. In other words, "definition" and "quotation" of array A between parallel processes
occurs, so it can be easily determined that the loop 700 cannot be processed in parallel. Note that in the above example, since the array was a two-dimensional array, the entire array could be displayed on a two-dimensional screen. If the array is a multidimensional array with three or more dimensions, the user only needs to leave two dimensions and set the other dimensions to specific values. For example, 3-dimensional array B(I, J
, K), by setting B(I, 5, K), the access status of array B on the J=5 plane can be displayed on a two-dimensional screen.

Next, another embodiment of the present invention will be described.

FIG. 4 shows a functional block diagram of the parallel computer system. The source program 100 is a compiler 200
is translated into the load module 300 by The compiler 200 consists of an access information addition section 210 and a code generation section 220, and 210 and 220 have the same functions as in FIG. 3. When the load module 300 is executed, the parallel processing part is copied to a plurality of parallel processing part load modules 360 at the beginning of the parallel execution part, and is allocated to the parallel processors and executed. In this case, a parallel process number determined at the time of execution is attached to the access identifier in the access information.

The load module is executed by the parallel computer system shown in FIG. Each parallel process is loaded into the processor 21-i (i=1 ton), and when the processing by the processor 20-1 reaches a part to be parallel-processed, each processor executes the parallel processing of the parallel process. At this time, when the array data A stored in the data area in the shared memory 24 is accessed by each processor, an access information record is output from each processor according to the object code and stored in the array access information file 400.

The access information file 400 is shown in FIG.
The trace data display tool 500 shown in FIG. This operation is the same as in the previous embodiment.

Next, the operation of a program intended to be executed by the vector computer shown in FIG. 10 will be explained.

An embodiment of the program verification method of the present invention for a source program intended to be executed on a vector computer will be described with reference to FIGS. 5 to 23 to 31.

When the source program 100 is intended to be executed on a vector computer, the loop to be processed is vectorized, and the access information addition unit 210 in FIG. 2c
As a result, the source statement number is added as an access identifier to the element of the array to be checked within each vector processing unit.

For example, FIG. 23 for the purpose of vector processing
The loop 20 of the source statement number #n has an access identifier #n for the element of the array A quoted in the statement 21 in the loop 20.
and statement 2 in loop 20 with source statement number #n+1
The element of array A defined in 2 has access identifier #n+
Set 1.

This will be explained with reference to FIG. In order to output the access information, the compiler executes statements 21,
22, an object code that operates as shown in 26 and 27 of the loop 25 is added. At this time 21
, 22 are assumed to be n and n+1, respectively. For the array element A (I-K) to be inspected in No. 21, the access type "USE" indicating use, the subscript value I-K, the access identifier "n", and the source statement number n. , generates code that outputs the values of array elements as trace data. For A(I) in 22, trace data includes the access type "DEF" indicating that it is a definition, the subscript value I, the access identifier "n+1", the source statement number n+1, and the value of the array element. Generate code to output as . The order of referencing array data when the loop 10 shown in FIG. 26 is executed by a vector computer is equivalent to the case where the loop 10 is divided into a loop 10a and a loop 10b and sequentially executed in this order. Therefore, whether or not loop 10 can be executed correctly on a vector computer depends on loop 1
Relationship between definition and citation of elements of array A in 0 and loop 10
This can be determined by determining whether or not the relationship between definitions and citations of the elements of array A match when a and loop 10b are sequentially executed in this order on a computer.

FIGS. 27A to 27C show the relationship between definitions and references of elements of array A in loop 10, loops 10a and 10b when K=1.

In loop 10, for example, element A(
2) d and A (2) Like u, each element of array A is defined first and referenced later. On the other hand, in the loop 10a, only the definition of each element of the array A is performed, and in the loop 10b, only the citation of each element of the array A is performed, but each element of the array A is first defined in the loop 10a, and then loop 10b
The relationship is cited in In other words, the same relationship as in loop 10 is maintained. Therefore, loop 10 can be executed correctly on a vector calculator.

Next, when loop 20 in FIG. 23 is executed by a vector computer, the order of referencing array data is as follows:
This is equivalent to dividing the loop 20 into loops 20a and 20b and sequentially executing them in this order.

FIGS. 25A to 25C show array A in loop 20, loops 20a and 20b when K=1.
It shows the relationship between definitions and citations of elements.

In loop 20, each element of array A is defined first and referenced later. On the other hand, in the loop 20a, only the quoting of each element of the array A is performed, and in the loop 20b, only the definition of each element of the array A is performed, and each element of the array A is
The relationship is first quoted in loop 20a and then defined in loop 20b. In other words, it has a different relationship from the loop 20. In this case, if loop 20 is executed as is on a vector computer, correct calculation results will not be obtained.

As can be understood from the above, vector processing possibilities of a program can be verified by comparing the source statement number at the time of definition of a certain array element with the source statement number at the time of quoting this array element. can.

Referring to FIG. 10, in step 522aa, the access type of the input array element currently being processed is determined. If the type is definition, the process advances to step 524a. If the type is citation, the process advances to step 522b.

In step 524, the access identifier of the array element currently being processed, ie, the current access identifier NOWID, is stored in the corresponding entry in storage 528. The process then proceeds to step 526c. On the other hand, step 52
2b, the previous access identifier PREID corresponding to the array element currently being processed is read from the storage 528.

In step 522c, the access identifier N
It is determined whether OWEID is greater than the previous access identifier PREID. If so, proceed to step 526b. If not, proceed to step 526a.

In step 526a, it is determined that the display color of the array element currently being processed is color C, and that it is displayed at high brightness for a short period of time. On the other hand, step 52
In step 6b, it is determined that the display color of the array element currently being processed is to be displayed as color B, and that it is to be displayed with high brightness for a short period of time. Furthermore, in step 526c, it is determined that the display color of the array element currently being processed is to be displayed as color A, and that it is to be displayed at high brightness for a short period of time.

The above operation will be specifically explained using the loop 20 shown in FIG.

FIGS. 28A and 28B show the contents of the storage 528 and a screen display example at the time when I=2 and the execution of the statement 21 in the loop 20 is completed.

FIGS. 29A and 29B show the storage 5 at the time when statement 22 in loop 20 is executed with I=2.
28 contents and screen display examples are shown.

FIGS. 30A and 30B show the storage 5 at the time when statement 21 in loop 20 is executed with I=3.
28 contents and screen display examples are shown.

FIGS. 31A and 31B show the storage 5 at the time when I=3 and the statement 22 in the loop 20 is executed.
28 contents and screen display examples are shown.

Hereafter, as a result of similar processing, array element A
Since (I) is displayed in color C on the screen, it is clear that there is a possibility of unauthorized reference. In other words, the order of "definition" and "citation" in the original loop 20 is out of order, so loop 2
It can be easily determined that 0 cannot be subjected to vector processing.

FIG. 32 shows a compiler according to another embodiment of the present invention. In this example, the load module is shown in Figure 1.
It is executed by a sequential computer system as shown in .

[0080] The source program 100 is executed by the compiler 2.
00a and is converted to the load module 300a.

The compiler 200a has an access information addition section 210 and a code generation section 220a that generates a code for calling the trace data display tool 500a.

210 is shown in FIG. 3 or 2 in FIG.
Perform the same operation as 10.

220a is an object code (trace data display tool calling unit 31 in FIG. 33) that calls the tool 500a every time an array element is defined or cited.
0) is generated and added to the load module 300a. Therefore, when the load module 300a output from the compiler 200a is executed, each time the array is accessed, control is transferred to the calling unit 310 as shown in FIG. 33, and the tool 500a is started from now on.

The tool 500a includes an array access information detection section 510a and an array access information processing section 520.

510a detects the type of access (definition or quotation) of the array element currently being processed, the subscript value for each dimension, and the current access identifier NOWID, and passes it to 520 as an access information record for the array currently being processed.

The array access information processing unit 520 operates in the same way as the array access information processing unit 520 of FIG. 8 described above. The embodiment shown in FIGS. 32 and 33 also provides the same results as the embodiment shown in FIG. 3 or 5.

[0087]

[Effects of the Invention] According to the embodiments described above, it is possible to visualize and display the possibility of illegal references to array data that are particularly likely to cause defects in source programs intended to be executed on parallel computers or vector computers. , it becomes easier to debug programs.

Furthermore, since a value other than 0 is set in the access identifier storage for defined or referenced elements, it can also be used to check undefined array elements.

Furthermore, by selecting an array element in each display area, the source program statement number, subscript value, and element value that accessed this element can be displayed. Further, at this time, the corresponding source program can be displayed, and the accessed source statement can be displayed with high brightness.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a sequential computer processing device according to an embodiment of the present invention.

[Fig. 2] A configuration diagram of a sequential computer processing device according to an embodiment of the present invention.

[Fig. 3] Processing configuration diagram of an embodiment in a sequential computer of the present invention

[
Figure 4: Processing configuration diagram of an embodiment in a parallel computer of the present invention

[Fig. 5] Processing configuration diagram of an embodiment in the vector computer of the present invention

FIG. 6 is a conceptual diagram of a trace data display tool according to an embodiment of the present invention.

[Figure 7] Data format diagram of array access information file

[Figure 8] Conceptual diagram of array access information processing unit

[Figure 9] Flowchart of the operation of the array access information processing unit in the parallel processing program

FIG. 10 is a flowchart of the operation of the array access information processing unit in the vector processing program.

[Figure 11] Illustration of a program aimed at parallel processing

[
Figure 12: Conceptual diagram showing the reference relationship of array A in the loop in Figure 11

[Figure 13] Another example diagram of a program aimed at parallel processing

[Figure 14] Conceptual diagram showing the reference relationship of array A in the loop in Figure 13

[Figure 15] Yet another example diagram of a program aimed at parallel processing

[Figure 16] Conceptual diagram of outputting trace data at the reference location of array A in the loop in Figure 15

FIG. 17 is an illustrative diagram of the contents of the access identifier storage storage and screen display in the loop 700a.

FIG. 18 is a diagram showing an example of the contents of the access identifier storage storage and screen display when I=1 in statement 702b.

[
FIG. 19 is a diagram showing an example of the contents of the access identifier storage storage and screen display when I=1 in statement 703b

FIG. 20 is a diagram showing an example of the contents of the access identifier storage storage and screen display when I=2 in statement 702b.

[Figure 2
1] Diagram showing an example of the contents of the access identifier storage storage and screen display when I=2 in statement 703b

[Figure 22
] A diagram showing an example of the contents of storage for storing access identifiers and screen display in loop 700b.

[Figure 23] An example diagram of a program aimed at vector processing

[Figure 24] Conceptual diagram of outputting trace data at the reference location of array A in the loop in Figure 23

[Figure 25] Conceptual diagram showing the reference relationship of array A in the loop in Figure 23

[Fig. 26] Illustration of another program aimed at vector processing

[Figure 27] Conceptual diagram showing the reference relationship of array A in the loop in Figure 26

[Figure 28] An example diagram of the contents of the access identifier storage storage and screen display when I=2 in statement 21

[Fig. 29] A diagram showing the contents of the access identifier storage storage and a screen display example when I=2 in statement 22.

FIG. 30 is a diagram showing the contents of the access identifier storage storage and a screen display example when I=3 in statement 21.

[Fig. 31] A diagram showing the contents of the access identifier storage storage and a screen display example when I=3 in statement 22.

FIG. 32 Compiler configuration diagram of another embodiment of the present invention

FIG. 33 is a conceptual diagram of a trace data display tool according to another embodiment of the present invention.

[Explanation of symbols]

410. Access number, 420. Access type, 43
0.1-dimensional subscript value, 2-dimensional subscript value, 440. Access identifier, 450. Source number, 460. array element value, 5
12. Array access information record currently being processed, 520
．． Processing unit, 522. Comparison section, 524. Update Department, 526.
Display color determining unit, 528. Storage for storing access identifier, 530. Display data

Claims (26)

[Claims] 1. A program verification method for testing a source program whose at least one part is to be converted into a processing part to be executed in parallel by a plurality of processors, comprising:
Translate the source program into an object program,
The object program is executed, and during the execution of the object program, access information is generated each time one or more elements of array data to be inspected are processed as definitions or uses, and the access information includes information about each element. Each dimension includes at least the subscript value of each dimension, the process number assigned to the process part, and whether the process is defined or used, and further,
A program verification method comprising the step of verifying whether the source program portion can be executed by multiple processes based on the access information when each element of the array data to be inspected is processed. Claim 2: In claim 1, when at least one same element of the array data to be inspected is defined with multiple different process numbers, or when the process number that made the definition and the process number that used it are different. A program verification method characterized by detecting that parallel processing is not possible. 3. According to claim 1, in the source program part to be inspected, a source statement in which processing is performed on the array element to be inspected is found, and whether the processing to the array data to be inspected is defined or used is found, and the object program is executed. A program verification method comprising: generating an object program so as to output the access information every time processing is executed, and generating the access information is achieved by executing the object program. Method. 4. A program verification method according to claim 2, wherein the verification step is performed after execution of the object program. 5. The program verification method according to claim 3, wherein the generation step is executed in parallel with execution of the object program. 6. According to claim 4, in the verification step, for each element of the array to be inspected, the previously generated access information and the currently generated access information are used.
A program verification method characterized by verifying whether a source program can be processed in parallel by multiple processors. 7. The program verification method according to claim 6, wherein the previously generated access information regarding one element is the most recently generated access information. 8. A program verification method according to claim 5, further comprising the step of storing access information generated for elements of a plurality of arrays to be inspected in parallel with execution of the object program. 9. In claim 1, display areas corresponding to a plurality of array elements to be inspected are arranged in a one-dimensional or two-dimensional matrix, and in these display areas, it is possible to illegally reference the corresponding array elements to be inspected. A program verification method characterized by displaying information indicating the nature of the program. 10. A program verification method, wherein the one-dimensional or two-dimensional matrix of claim 9 relates to one or two dimensions specified by a user for a multidimensional array to be inspected. . 11. In claim 1, the executing step comprises:
A program verification method characterized in that an object program is executed so that processing parts in the source program are executed sequentially. 12. The object program according to claim 11, wherein the object program includes object code that sequentially executes a plurality of processing parts that each processor is responsible for executing, and the execution step sequentially executes the processing parts of the object program. A program verification method that includes steps to 13. The program verification method according to claim 12, wherein when the source program portion includes a loop, the source program portion is divided into a plurality of loop portions and the loop portions are converted into an object program that is executed sequentially. 14. The program verification method according to claim 1, wherein said executing step executes the object program such that processing portions in said source program are executed in parallel. 15. According to claim 14, in the translation step, when the source program portion includes a loop,
Determine the loop repetition range when executing the loop part by dividing it into different processing parts, convert the source program including this loop part into an object program, add information indicating the determined loop repetition range to the object program, and A program verification method in which different processing parts are executed in parallel in the execution step based on a loop part and an object program part that represents added information. 16. A method for testing a source program to be translated into an object program in which at least one loop included therein is processed by a vector processor, the method comprising: translating the source program into an object program to be sequentially executed on a computer; , this object program is executed sequentially on a computer, and during execution of this object program, access information is generated each time one or more elements of array data to be inspected are processed as definitions or uses, and this access information is contains at least a subscript value, a source statement number to be processed, and whether the process is defined or used for each element, and further includes the access information when each element of the array data to be inspected is processed. A program verification method comprising verifying whether at least one of the source statements that accesses an array to be tested can preclude vectorization. 17. According to claim 16, the verification step excludes vector processing for the same element of the array to be inspected when the source statement number that uses that element is smaller than the statement number that defines that element. A program verification method to detect. 18. In claim 16, at the time of translation, a source statement in which a process is performed on an array element to be inspected is found in the inspection source program portion, and whether the process is a definition or a use is found, and this object program is A program verification method, characterized in that an object program is generated so as to output the access information each time a process is performed when executed, and the generation of the access information is achieved by executing the object program. 19. A program verification method according to claim 18, wherein the verification step is performed after execution of the object program. 20. The method according to claim 19, further comprising the step of storing the access information generated for the elements of the plurality of arrays to be inspected in parallel with the execution of the object program, and the verification step includes the step of storing the access information generated for the elements of the plurality of arrays to be inspected in parallel with the execution of the object program. A program verification method that is executed based on the access information obtained. 21. In claim 16, display areas corresponding to a plurality of array elements to be inspected are arranged in a one-dimensional or two-dimensional matrix, and in these display areas, it is possible to illegally reference the corresponding array elements to be inspected. 1. A method for displaying trace data, characterized by displaying information indicating the nature of the trace data. 22. A trace data display characterized in that the one-dimensional or two-dimensional matrix according to claim 21 relates to one dimension or two dimensions specified by a user for a multidimensional array to be inspected. Method. 23. The trace data display method according to claim 9 or 21, wherein in each display area, distinctions between definitions and uses of corresponding array elements are also displayed. 24. The trace data display method according to claim 9 or 21, wherein the possibility of unauthorized reference is distinguished and displayed by color, and the distinction between definition and use is displayed by a color different from the color. 25. The brightness of each display area is made high for a short time in the order in which the corresponding array element is accessed.
One of the trace data display methods. 26. In a translation method for generating an object program by translating a source program, an access type indicating whether an array element to be inspected is defined or used, a subscript value for each dimension, and an accessed process number or A translation method characterized by additionally generating an object code for calling the verification step according to claim 1 or 16 as a source sentence number and an argument.