JPH04211163A - Integrated circuit - Google Patents

Abstract

PURPOSE: To provide a trench without any groove, spike, or another undesired plane shape on the floor by etching the trench by using the forward spattering of a hard mask. CONSTITUTION: This circuit is composed of silicon oxide, and the silicon is exposed only in a scheduled trench place. Thus, a silicon substrate on which a hard mask in which a limited pattern is decided is provided is prepared. Then, the oxide of the silicon is always deposited on the side wall of the trench during etching, and almost all the oxygen electrons of the silicon on the side wall at the side wall are allowed to come from the hard mask. The etching of the trench is operated by the plasma source of a silicon etching agent ion at the scheduled trench place of the silicon substrate under this condition.

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a trench structure and a method for manufacturing such an integrated circuit. [0002]

BACKGROUND OF THE INVENTION Trenches, ie, etched into the substrate of an integrated circuit, are
Although it is desirable in some aspects of VLSI processing to fabricate trenches with aspect ratios greater than 1, i.e., widths less than 3 microns and depths greater than 1 micron, this manufacturing process suffers from several notable problems. accompanied by difficulties. The present invention addresses this difficulty. Current VLSI trends in CMO8 and bipolar technologies are developing non-intrusive isolation schemes to improve silicon area utilization for fabricating active devices while effectively reducing the risk of latch-up. need to be developed. That is, L.O.
When using GO8 isolation to isolate moat (active device) regions, field oxide grows laterally into the moat region at the same time as it grows to its desired thickness. This is also a problem with other separation techniques. With isolation structures, the spacing required to provide separation between closest active devices can be many times the minimum surface geometry. The need to provide compact isolation is particularly important for CMO8VLSI technology. This is because current doping levels limit the N-P tank spacing to 4-6 microns. To reduce the required spacing between the n+ and p+ regions, a silicon trench dry etch process is used to create deep but narrow silicon wells between the cells, which are later filled with CVD oxide or polysilicon. Backfilling with silicon allows device isolation while maintaining high density and avoiding latch-up.

Another area where trench processing is important is D.
RAM (dynamic random access memory)
This is the case. If the cell area used by planar storage capacitors can be reduced without reducing the capacitance below soft error levels, the backing density of dynamic MOS memories can be increased even further. This can be accomplished by placing the capacitor dielectric on the sidewalls of a silicon trench that is etched deep enough to have the equivalent surface area of a planar capacitor. Note that trenches for these applications, unlike those needed for isolation, do not tend to be long trenches. [0004] However, in such applications, the properties of the silicon trench must be carefully controlled to achieve satisfactory results. The cross-sectional shape of the trench is particularly important. For example, using conventional trench etch processes, it is common to see trench cross-sections that undercut the silicon relative to the patterning mask, or create a "groove" near the bottom of the trench. Ru. Even cross-sections with slightly undercut sidewalls are susceptible to void formation during subsequent CVD backfill operations, which are commonly used for both trench isolation and trench capacitor processing. These voids are problematic because they can act as a reservoir for contaminants. Additionally, subsequent etch-back steps may reopen the voids, creating significant filament problems when subsequent patterning of conductors is attempted. Additionally, etchback to achieve a truly planar surface within the trench, which would be desirable in advanced processes, becomes impossible. "Gulleys" at the bottom of the trench can also be very harmful. This can degrade the dielectric integrity of the trench capacitor, and during thick thermal oxidation,
This may promote high stress-related silicon defect densities. [0005] The ``r-groove'' is believed to be due to non-uniformities occurring at the beginning of the etch process. That is, early in the etch process, the edges of the trench are exposed to bombardment by both straight-in ions and ions that are slightly deflected by hitting the trench sidewalls or hard mask. For this reason, the trench is etched somewhat deeper at its edges than near its center. The complex effects of automatic sputtering carry this non-uniformity into subsequent etching steps, so that trenches etched using conventional methods tend to have grooves at their bottoms and near the sidewalls. Very strong. [0006] Accordingly, it is an object of the present invention to provide a silicon trench etch that produces trenches that do not have grooves or spikes or other undesirable planar features in the trench floor. Another problem in the prior art is the special shape of undercuts, which can be referred to as setback undercuts or curvatures. This is in that the degree of undercut is almost zero in the vicinity of the mask and increases with depth, typically over distances on the order of 1 micron.
It is different from the normal undercut. This retreating undercut is believed to be due to scattering of ions from the mask material at opposing edges of the trench. It is therefore an object of the present invention to provide a silicon trench etch that produces trenches with straight (non-curved) sidewalls and without grooves or other undesirable topography in the trench floor. . [0007] Traditionally, a natural way to control the cross-sectional shape of the trench is to make the etch conditions somewhat less anisotropic, for example by increasing the pressure. However, this method does not work for several reasons. First, a near-layer isotropic etch makes the final width of the trench less controllable. Second, if the sidewalls of the trench are near vertical (which is necessary to preserve the advantages that led to the use of trenches above all else), simply using a more near-isotropic etch will result in There is a tendency to create undercuts near the top of the trench, resulting in voids during backfilling. If the anisotropy is reduced to the point where there are no voids, the "trench" structure becomes very wide,
This eliminates the ability to provide compact isolation, which is the primary purpose of using trenches.

[0008]

SUMMARY OF THE INVENTION The present invention utilizes selective sidewall deposition to eliminate "channels" and provide a steeply angled positive slope that is controllable. The above-mentioned and other problems of the prior art are overcome by providing a silicon trench etch method that produces trenches with trench sidewalls that are reproducible in size. Therefore, the trench obtained by this invention is
Suitable for subsequent successful backfilling without sacrificing line width control. The present invention uses oxide sidewall deposition performed in a slow, continuous-like fashion during the silicon trench etch process. (This is believed to be achieved because during the etch process, a portion of the mask is forward sputtered and a portion of the forward sputtered mask material (possibly in combination with silicon etch products) (This is to create a thinly deposited non-stoichiometric oxide on the sidewalls of the trench as the etch progresses.) Thus, the deeper portions of the silicon etch are covered by the sidewall oxide at the edges of the pattern. Create silicon sidewalls that are defined and sloped as the deposition progresses. Additionally, sidewall deposition prevents "grooving" at the bottom of the trench. This is probably due to depositional shaping of the bottom edge of the trench and/or differences in ion deflection coefficients between oxide and silicon. [0009] Conventionally, silicon oxide is slowly deposited while etching a silicon trench to form a 5i
Experiments have been conducted with compositions that achieve much higher "selectivity" for the 02 mask. 28 I
See the article by Horvitz, ``Reactive Sputter Etching of Silicon with Very Slow Etch Rates of Mask Materials,'' published in EEE Transactions on Electron Devices, Vol. 1320. However, in this conventional attempt, the deposition could not be controlled. This means that the source of the deposited oxide is the gas stream, the location of its deposition is determined by the gas stream, and (as in the present invention)
This is because it is not conveniently and reliably positioned for the etching process. In the prior art of this report,
Sidewall oxide deposition has negative consequences in terms of wall profile and promotes effective undercutting of the mask to a certain degree.

Particular advantages of the processing innovation according to the invention are:
It is possible to create trenches with straight sloped sidewalls without bottom channels or top undercuts, and the slope of the sidewalls is steep but controllable. The process parameters controlled to change the slope of the trench sidewalls are:
The DC self-bias voltage of the silicon etch process and the introduction of minimal species, such as BCl3, which tend to cause oxide etching. That is, introducing 3 to 5 seconds of BC13 into the silicon etch mixture completely eliminates sidewall oxide deposition, and introducing less BC13 eliminates sidewall oxide deposition. The angle of the sidewalls of the etched trench decreases and therefore becomes steeper. To this end, the present invention provides a reproducible method for manufacturing trenches with a controlled sidewall slope of a predetermined angle of 80° to 89° and a flat trench bottom. Furthermore, such trenches can be easily made to depths not previously possible, such as 8 microns or more.

[0011] Since there has been no conventional method for making such an ideal trench, this structure itself is new. The availability of precisely controlled sidewall steepness means that backfill problems can be avoided and that the implant process (if desired) can reach the trench sidewalls. Therefore, it is very advantageous. This may be particularly desirable for trench isolation applications. In such cases, such implants can be used to eliminate leakage paths due to turn-on of parasitic transistors on the sidewall surfaces of the trenches. This can also be useful in trench capacitor applications. in this case,
Such a drive can act as a "high-C" drive or serve other purposes. (In this case, the hard mask is made of a composite material such as oxide/nitride/oxide or polysilicon/oxide, and after removing the throat-choking oxide, some hard mask is removed. (The mask remains to preserve the trench mask pattern for implantation.) [0012] In particular, the present invention allows for the fabrication of trench capacitors using very deep trenches. - The key issue with trench-in-shell capacitors is to make the capacitance of the minimum geometry capacitor high enough. The present invention contributes to solving two aspects of this problem. First, the deeper the trench, the greater its capacitance (for a given specific capacitance on the sidewalls). Second, the present invention allows the trench capacitor to be placed very deep, so that it can pass straight through the lightly doped epitaxial layer in which the active device is formed into the heavily doped substrate. Make it possible to make it. If the substrate is heavily doped,
It is especially important to avoid crescent-shaped bottoms of the trenches. The increase in electric field caused by the geometry makes it more prone to dielectric breakdown there than in more lightly doped regions for two reasons. First, since the depletion width becomes narrower, the electric field in the depletion layer becomes stronger. Second, the presence of significant doping at this location may mean that the quality of the oxide grown will not be quite the same as that grown on more lightly doped silicon. . Third, the ability to exist around the base of the crescent means that the grown oxide will be less thick in this critical area than anywhere else. For example, one embodiment of the present invention provides a DRAM cell using trenches 8 microns deep, but deeper trenches can easily be made. [0013] Thus, in addition to the advantages described herein, the present invention provides at least the following advantages. ■. Very deep trenches can be reproducibly etched with very good shape control. 2. The present invention creates trenches in silicon with straight (non-curved) sidewalls and no grooves or other undesirable topography at the bottom of the trench. 3. The trenches obtained according to the invention are suitable for subsequent successful refill processing without sacrificing linewidth control. 4. The present invention provides trenches with trench sidewalls that have a steep positive slope, the slope of which can be determined controllably and reproducibly. 5. The present invention (embodiments) has a capacitor in a trench with a depth of 6 microns or more,
A DRAM cell is provided that can achieve relatively large capacitance within a trench cell. 6. Embodiments of the present invention include having a capacitor in a trench extending to a heavily doped substrate (below the epitaxial layer from which the active device was made), with a relatively large capacitance in the trench cell. To provide a DRAM cell that can achieve the following. 7. Embodiments of the present invention have vertical transistors overlapping storage capacitors in trenches of 6 microns or more in depth, providing good pass transistor performance as well as good trench backfill properties. To provide a RAM cell in which a relatively large capacitance can be achieved within the trench cell while maintaining the memory capacity of the trench cell. [00141 In the present invention, a patterned hard mask is provided on a silicon substrate such that the material of the hard mask is forward sputtered to induce deposition on the sidewalls of the trench during etching. A method of etching a trench in silicon includes the step of plasma etching an exposed portion of the silicon substrate under suitable etch conditions. [0015] The present invention provides a silicon substrate having a patterned hard mask thereon comprised of silicon oxide and defined to expose the silicon only at the intended trench locations. etching a trench in the silicon substrate at the location of the intended trench, provided that during etching, oxide of silicon is continually deposited on the sidewalls of the trench; A method of etching a trench in silicon such that substantially all the oxygen atoms in the oxide of the silicon come from the hard mask. [00161] The present invention further comprises a dynamic random access memory comprised of an array of memory cells, each cell in the array being individually comprised of a pass transistor in series with a storage capacitor; at least one plate of is formed in silicon in the face of the trench, said sidewalls having a positive sidewall angle in the range of 80° to 89° and having straight sidewalls without curvature or undercuts. , an integrated circuit having a trench capacitor is provided. [0017] The present invention further provides a silicon substrate having a plurality of active device areas therein forming a transistor;
a plurality of trenches separating the active device areas in a predetermined separation pattern, each trench having an angle between 80° and 89°;
An integrated circuit having a trench isolation having straight sidewalls without curvature or undercuts with positive sidewall angles in the range of 0. Next, the present invention will be explained with reference to the drawings. [0018]

[Embodiments] Several embodiments currently considered to be preferred will be described in detail, but since the present invention represents a novel idea that can be applied in a wide range and can be implemented in a wide variety of cases, the following description will be given below. It should be clearly stated that the described embodiments are illustrative and do not define the scope of the invention, which is limited by the scope of the claims. FIG. 1 shows the first steps in carrying out the method of one embodiment of the invention. A silicon dioxide patterned hard mask 12 is in place on the silicon substrate 10, defining openings to expose the substrate 10 at the intended trench locations 16. [0019] Of course, these etching conditions can vary widely. In general, a wide range of conventional conditions can be used, provided they result in forward sputtering (and/or reactive redeposition) of the hard mask. However, the etch configuration previously described has certain advantages. For example, using HCI rather than C12 as the primary source of chlorine means that forward sputtering of the mask is enhanced. This is because the ion bombardment is primarily performed by CI ions rather than CI2 ions, and the C1 ions match the average atomic number of the mask material better, which increases the sputtering yield (or at least the sum of the sputtering yield and the reflection of the ions). ) tends to be higher. In fact, it has been found that using HCI, rather than CI2, as the primary etch feed gas component has a substantial contribution to the success of the method of the present invention. (Generally, when modifying the invention, the ion species of the etchant is one variable that can be adjusted to control the amount of sidewall deposition and thus the resulting trench cross-sectional shape.) ) Some of the benefit from HCI may be due to the fact that it can also be a source of hydrogen atoms that can play a role in sidewall deposition. [00201 Chlorine increases the etch rate considerably, but the presence of even a small percentage of CI2 makes the crescent shape at the bottom of the trench noticeable. Therefore, the preferred etching gas flow is 40 sc
cm of HCI and no chlorine. Using higher pressure to etch the last portion of the trench tends to create a sharp trench bottom. - Using lower layer pressures reduces the etch rate. As the bias voltage is lowered, the sidewall oxide deposition and etch rates slow down and (much lower) begin to approach isotropic etch characteristics. Higher bias increases sidewall oxide deposition and etch rates, increasing oxide mask erosion and, if significant, loss of linewidth control. As mentioned earlier, the introduction of small amounts of inorganic chlorides, such as B C13, facilitates oxide etching and thus suppresses sidewall oxide deposition, thus resulting in steeper sidewalls of the trench. It will be done.

Another factor that influences the extent of forward sputtering and thus the angle of the trench sidewalls is the initial sidewall slope of the hard mask sidewalls. That is, the first
As shown, the sidewalls 14 of the oxide hard mask 12 are preferably not at a full 90° angle. 80° to 89
A degree angle is preferred. Furthermore, a hard mic sidewall with a large slope will generally result in more forward sputtering of the hard mask, but making the sloped sidewall of the hard mask too large will cause the mask to become multifaceted and cause lines to form. There is a loss of width control and the risk of damage to the silicon in the upper corners of the trench. [0022] Since the method of the present invention is a highly dynamic method, the initial sidewall angle of the oxide is important. During the entire silicon etch process, forward sputtering occurs continuously, so that the initial angle of the mask can directly or indirectly influence the etch results over a significant distance. In the presently preferred embodiment, the initial angle of the mask is limited primarily by transfer from the sidewall angle of the photoresist. However, alternatively, the etching conditions of the first etching step can be changed to make the hard mask initially somewhat more polygonal. For example, the currently preferred embodiment uses an initial BC primarily for cleaning and initialization.
13 etch, but alternatively, the conditions used for this first step of the etch (higher bias voltage, use of a different supply gas type, etc.) can be used to achieve the polygonal shape that is initially obtained. I can do it. (Note again, however, that the initial sidewall slope of the hard mask must be steep; otherwise, mask erosion will cause the mask to recede and create a trench with a wide top.) ] FIG. 7 shows sample curves of sputtering yield S(θ) and ion reflection coefficient R(θ) as a function of ion incidence angle θ with respect to the surface. What this curve means for the present invention is that the sidewall angle θ of the mask is θ (the angle of incidence at which ion reflection is negligible) and θ (
(Incidence angle at which sputtering yield becomes negligible)
This means that it should be within the range between . Preferably, the mask angle is not too close to either θ 2 or θ 2 , but should be somewhere in the middle of this range. To widen this central range, the following factors can be adjusted. The following factors enhance the degree of forward sputtering. Increasing the energy of the ions (by increasing the sheath potential of the plasma). Lower the atomic number of the mask material. Lowering the atomic number of the dominant incident ions or reducing the density of the target material. - Reflection of ions into the shell (resulting in a crescent-shaped bottom) occurs at a minimum angle θ defined by the equation: 22/3 π 5πa n Zl 22 ER□−
〇 −□ 2 < z 2/3 +z 2/3 )E
l 2 1 where aO is the Bohr radius of hydrogen, Zl is the atomic number of the ion, Z2 is the atomic number of the target species, n is the density of the target, ER is the lidbarb energy, and El is the ion energy. [0024] The silicon etch conditions used are preferably strongly anisotropic, such that control of the sidewall slope of the trench depends solely on the sidewall deposition characteristics. - If steep sidewalls are desired, this may be achieved by introducing a very small flow of an oxide etchant such as BCla into the feed gas mixture to reduce forward deposition of material on the sidewalls. I can do it. Although the present invention may use silicon etch conditions that are less inherently anisotropic, this is not preferred. During the oxidation etch step that defines the hardmask pattern,
The sidewall shape of the resist is reflected in the sidewall angle of the oxide hardmask. [0025] Next, trench etching conditions will be explained. In this example, the silicon trench etch is performed in a six-electrode vacuum tube type RIE batch reactor under the following conditions. Step 1 (a) HCl 40 sec (b) BC 1310 sec (c) Pressure 15 mTorr (d) Bias -300 volts (e) Temperature 60°C (f) Time 5 minutes Step 2 (a) HCl 40 sec (b) CI2 5 sec (c ) Pressure 15 mTorr (d) Bias -400 Volts (e) Temperature 60°C (f) Time Depends on desired etch depth. For example, it takes about 40 minutes to etch a 3 micron trench. [0026] The first step of the etch cuts away the native oxides that typically form when silicon is exposed to air for even short periods of time. Gas flow rates are expressed in sccm, ie, standard cubic centimeters of 7 minutes. The etch conditions used were an areal power density of about 400 mW/cm2 and an areal power density of about 7 W/cm2.
corresponds to Little's volumetric plasma power density. After the trench is etched to the desired depth, a clean step (depending on the particular device fabrication sequence used) is preferably used to remove the oxide from the sidewalls of the etched trench. This may be, for example, a short wet etch with HF or a short high pressure plasma fluoro etch. The general idea of etching trenches using forward sputtering (or reactive redeposition) of a hard mask is novel in itself and can be implemented with a very wide range of modifications and variations. Please note that it is possible. For example, other hard mask materials such as silicon nitride or photoresist can be used, but for better control of mask erosion and more controlled forward sputtering, oxide Hard masks are highly preferred. In embodiments using HBr, it is believed that the material deposited on the sidewalls contains a significant proportion of nitrogen in the embodiments tested after device formation. It has been found that photoresist masks are more sensitive to the original sidewall angle of the mask material. [00271 Figure 2 shows a sample trench that was etched to a depth of 3 microns and subsequently processed to create a trench capacitor for a 1 megabit dynamic RAM. Figure 3 shows an example of the sidewall deposition for the silicon etch observed immediately after the etch (Figure 3a) and the trench after its removal by dipping in 10% HF for 30 seconds (Figure 3b). ing. FIG. 4 schematically illustrates the effectiveness of removing sidewall deposits during a silicon etch using a modified trench etch method. In the absence of sidewall oxide, significant grooves and moderate undercuts are observed. [00281 FIG. 5 shows a trench structure in accordance with the present invention in which the trench has positively sloped steep sidewalls and a flat bottom.
A DRAM cell as a sample using a capacitor is shown. A pass transistor 104 addressed by a refractory metal gate 106 connects a bit line 118 to a trench
It is connected to the n+ diffusion section 112 forming one plate of the capacitor. The other plate is a polysilicon layer 108. A trench capacitor is formed in trench 120, which trench has straight positive slope sidewalls. Thin oxide 122 serves as the dielectric for the trench capacitor, and oxide 119 backfills the trench. The patterned oxide 116 provides isolation. A trench is etched to a depth of 8 microns. Roughly the top 2 microns of this is required for the pass transistor. The wafer used is p-type on p-decade epitaxial, so the bottom 4 microns of the capacitor has most of the capacitance. [0029] Thus, an advantage of the extremely deep trenches provided by the present invention is that the doping at the bottom of the trench can be significantly different from the doping at the top of the trench. One way to do this is to cut through the active device layers to reach the substrate. for example,
In the presently preferred embodiment, the substrate doping is p-type at about IE19 and the epitaxial layer is about IE19.
It is micron thick. (Updiffusion provides a gradually decreasing doping from a depth of 4 microns to a depth of about 2 microns.) The channel region of the active device has a p-type doping of about IE16 at a depth of 1.5 microns. (in this example) overlaid by a buried n overlayer that is doped to approximately IE20 to a depth of 1 millimeter and forms the bit lines of the DRAM array. However, the advantage of a higher doping concentration at the bottom of the trench can also be achieved in other ways, such as by implantation or by diffusion from a solid source or gas phase dopant source species. [00301 Although the present invention provides a high quality trench capacitor, its use is of course not limited to DRAM, which uses a grounded capacitor with substantially direct current to perform the charge pumping action. It is not limited to circuits of any shape. The advantage of large capacitance per unit surface provided by the present invention may also be very useful in many capacitor switched filter geometries. Many other DC and RF filter configurations use capacitors to ground and benefit from the inclusion of the trench capacitor of the present invention. In filter applications, the tens to hundreds of fF of capacitance typically provided by a single trench is usually too small, so many trench capacitors may be connected in parallel to provide sufficient It is preferable to form a capacitor with low KT/C noise characteristics. Furthermore, the trench capacitor to ground according to the present invention may also be very useful for creating RF ground in RF integrated circuits. [00311 In the presently most preferred embodiment, the present invention is used to etch trenches 3 to 10 microns deep, but the present invention can alternatively be used to etch deeper trenches. The embodiment described here uses a capacitance obtained from a capacitor of minimum size to
Since it is sufficient for M cells, it is approximately the smallest shape. However, the invention can also be used to etch deeper trenches with the same aspect ratio. For example, a trench 6 microns square on top can be etched to a depth of 40 microns or more using the present invention. Of course, when etching very deep trenches, it is desirable not to allow the trench to taper to a single point. For this reason, the depth is typically chosen such that the bottom of the trench remains flat. Similarly, -
Shallow trenches can also be etched using the present invention. This becomes preferred if sub-micron features are more widely used for patterning. The capacitor of the presently preferred embodiment is DRAM
Note that it is preferably a capacitor to ground, as used in circuits. However, this is not an inherent limitation. For example, in SOI structures or epitaxial structures with deep junction isolation, an isolation trench may be placed around the trench capacitor to take advantage of very significant doping at the level of the lower portion of the capacitor trench. It is possible to access the potential of the lower plate of the capacitor while making the most of the potential. [0032] The trenches of the present invention can also be highly advantageous for vertical logic structures. The DRAM cell described here has one transistor in a trench, with current flow perpendicular to the substrate surface. However, in logic circuit applications, it may be advantageous to have more than one active device within one trench. Again, the superior control over the sidewall profile provided by the present invention is extremely useful. Particularly in manufacturing streams that rely on long etchbacks to create buried planar surfaces, the void-free feature provided by the present invention can be a deciding factor. [0033] - Within the shell, the trench according to the invention is also very advantageous for isolation techniques. FIG. 6 shows an example of a CMO3 structure using trench isolation. in this case,
n+ diffusion part 202 of NMOS transistor 204 and PM
The possible spacing between p-diffusions 206 of OS transistor 208 is reduced by using oxide filled trenches 210 for isolation. The trench has steep sidewalls of positive slope and a flat bottom. [0034]

As can be seen from the above description, the present invention provides, among other things, silicon trench sidewalls with a positive slope without undercuts, facilitates the subsequent backfilling process, and improves patterning. positive slope of the sidewalls without sacrificing control of the dimensions of the trench, eliminating the "channel" problem commonly found at the bottom of the trench, and instead providing a flat bottom of the trench. This provides several important advantages over the conventional method. [00351 Although the present invention has been described with reference to various sample embodiments, the novel idea of the present invention is susceptible to a very wide range of modifications and changes, and therefore the scope of the present invention extends beyond the scope of the claims. Please be aware that you are limited only by: [00361 In connection with the above description, the following sections are further disclosed. (1) In a method of etching trenches in silicon, a patterned mask is provided on a silicon substrate, and the material of the mask is sputtered forward to deposit onto the sidewalls of the trench during etching. A method comprising the step of plasma etching exposed portions of the silicon substrate under etch conditions that induce positions. [0037] (2) In a method of etching trenches in silicon, a hard mask comprised of silicon oxide and defined in a defined pattern to expose the silicon only at the intended trench location. During etching, an oxide of silicon is continuously deposited on the sidewalls of the trench, and substantially all the oxygen atoms in the oxide on the sidewalls are removed from the hard mask. etching a trench in the silicon substrate at the location of the intended trench with a plasma source of silicon etchant ions under conditions such that the trench is etched in the silicon substrate at the location of the intended trench. [0038] (3) In the method described in item (1), the mask is composed of substantially silicon oxide, and the trench etch is plasma etching in an etch gas containing a chlorine-bearing species. A method in which the chlorine-containing species is mainly composed of hydrogen chloride. [0039] (4) In the method described in paragraph (1), the mask is made of substantially silicon oxide, and the trench etch is an etch that is a source of CI ions in a larger amount than CI ions. - A method that is plasma etching in gas. [0040] (5) The method described in paragraph (1), wherein the trench etch is performed at a total pressure within the range of 1 to 100 mTorr.

(6) The method of paragraph (1), wherein the mask opening has a sidewall angle in the range of 80° to 89° before the trench etch. [0042] (7) The method described in paragraph (1), wherein the trench etch is performed using a bias voltage in the range of 250 to 550 volts. [0043] (8) In the method described in paragraph (2), the mask is composed of substantially silicon oxide, and the trench etch is plasma etched in an etch gas containing a chlorine-bearing species. A method in which the chlorine-containing species is mainly composed of hydrogen chloride. [0044] (9) In the method described in item (2), the mask is made of substantially silicon oxide, and the trench etch is an etch gas that is a source of CI ions in a larger amount than CI ions. The method consists of plasma etching in the interior. [0045] (10) The method described in paragraph (2), wherein the trench etch is performed at a total pressure within the range of 1 to 100 mTorr. [0046] (11) The method of paragraph (2), wherein the opening in the mask has a sidewall angle in the range of 80° to 89° before the trench etch. [0047] (12) The method of paragraph (2), wherein the trench etch is performed at a bias voltage in the range of 250 to 550 volts. [0048] (13) In the method described in item (2), the trench etching plasma includes a small percentage of oxide etching species, and the non-receiving percentage is the sidewall oxide etchant. A preselected method for adjusting the speed of a position. [0049] (14) The method described in paragraph (2), wherein the plasma etching is performed at a volumetric power density within the range of 5 to 10 watts/liter. [00501 (15) The method described in paragraph (2), wherein the trench etching comprises plasma etching in an etch gas comprised of hydrogen chloride. [0051] (16) The method described in paragraph (1), wherein the trench etch comprises plasma etching in an etch gas comprised of hydrogen chloride. [0052] (17) In an integrated circuit having a trench capacitor,
A dynamic random access memory comprising an array of memory cells, each cell in the array comprising a pass transistor in series with a storage capacitor, at least one plate of the storage capacitor being An integrated circuit formed in silicon in the plane of a trench, said trench having straight sidewalls without curvature or undercuts, with a positive sidewall angle in the range of 80 to 89 degrees. [0053] (18) having a dynamic random access memory comprised of an array of memory cells, each cell in the array being comprised of a pass transistor in series with a storage capacitor; at least one plate is formed in silicon at the face of the trench, the trench having straight sidewalls with a positive sidewall angle in the range of 80° to 90° and no curvature or undercut; An integrated circuit having a trench capacitor, wherein the bottom of the trench does not have any crescent shape. [0054] (19) A dynamic random access memory comprised of an array of memory cells, each cell in the array being individually comprised of a pass transistor in series with a storage capacitor, each pass transistor is connected in a charge-transfer manner to an insulated storage plate within a trench, the trench having straight sidewalls with a positive sidewall angle in the range of 80° to 90° and no curvature or undercuts. an integrated circuit having a trench capacitor, wherein the bottom of the trench does not have any crescent shape. [0055] (20) a plurality of active capacitors connected to a plurality of substrates, each configured with an insulated storage plate in a trench, and a circuit format intended to include trench capacitors for at least some of the substrates; having a device;
the trench has straight sidewalls without curvature or undercuts with a positive sidewall angle in the range of 80° to 89°;
An integrated circuit having a trench capacitor, wherein the bottom of the trench does not have any crescent shape. [0056] (21) In the integrated circuit described in paragraph (17),
An integrated circuit in which the depth of the trench is between 6 and 20 microns. [0057] (22) In the integrated circuit described in paragraph (17),
The trench extends through the active device layer to a layer below it, and the trench extends between 3 and 10,000 mm of the active device layer.
An integrated circuit that has an equilibrium carrier concentration of 0x. [0058] (23) In the integrated circuit described in paragraph (17),
A portion of the semiconductor material adjacent to the bottom of the trench covers 3 to 1 of the channel region of the pass transistor.
An integrated circuit with an equilibrium carrier concentration of 00 times. [0059] (24) In the integrated circuit described in paragraph (17),
An integrated circuit in which the pass transistors are configured to provide substantially vertical current flow, each pass transistor overlapping a capacitor in a respective trench. [00601 (25) In the integrated circuit described in paragraph (18),
An integrated circuit in which the depth of the trench is between 6 and 20 microns. [00611 (26) In the integrated circuit described in paragraph (18),
The trench extends through the active device layer to a layer below it, and the trench extends between 3 and 10 of the active device layer.
An integrated circuit with an equilibrium carrier concentration of ゜000 times. [0062] (27) In the integrated circuit described in paragraph (18),
A portion of the semiconductor material adjacent to the bottom of the trench covers 3 to 1 of the channel region of the pass transistor.
An integrated circuit with an equilibrium carrier concentration of 00 times. [0063] (28) In the integrated circuit described in paragraph (18),
An integrated circuit in which the pass transistors are configured to provide substantially vertical current flow, each pass transistor overlapping a corresponding capacitor in the trench. [0064] (29) In the integrated circuit described in paragraph (19),
An integrated circuit in which the depth of the trench is between 6 and 20 microns. [0065] (30) In the integrated circuit described in paragraph (19),
The trench extends through the active device layer to a layer below it, and the trench extends from three to ten of the active device layer.
An integrated circuit with an equilibrium carrier concentration of ゜000 times. [0066] (31) In the integrated circuit described in paragraph (19),
A portion of the semiconductor material adjacent to the bottom of the trench covers 3 to 1 of the channel region of the pass transistor.
An integrated circuit with an equilibrium carrier concentration of 00 times. [0067] (32) In the integrated circuit described in paragraph (19),
An integrated circuit in which the pass transistors are configured to provide substantially vertical current flow, each pass transistor overlapping a respective capacitor in the trench. [0068] (33) In the integrated circuit described in paragraph (20),
An integrated circuit in which the depth of the trench is between 6 and 20 microns. [0069] (34) In the integrated circuit described in paragraph (20),
The trench extends through the active device layer to a layer below it, and the trench extends from 3 to 10 layers below the active device layer.
An integrated circuit with an equilibrium carrier concentration of ゜000 times. [00701 (35) A silicon substrate including a plurality of active device areas forming a transistor and a plurality of trenches separating the active device areas in a predetermined isolation pattern, each trench having an angle between 80° and 89°. have straight sidewalls without curvature or undercuts with a positive sidewall angle within the range of
Integrated circuit with trench isolation.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the first step in carrying out the method of one embodiment of the present invention.

FIG. 2 shows a sample of etched 3 micron deep trenches that are later processed to create trench capacitors for a 1 megabit dynamic RAM.

[Figure 3] Figures a and 3 are immediately after etching (Figure 3a) and 3.
Figure 3 shows an example of sidewall deposits on a silicon trench observed after removing sidewall deposits by soaking in 10% HF for 0 seconds (Figure 3b).

[Figure 4] Silicon etching using a modified trench etch method
FIG. 3 schematically illustrates the effect of eliminating sidewall deposition during etch, where in the absence of sidewall oxide, significant grooves and moderate undercuts are observed.

FIG. 5 is an example of a DRAM cell using a trench capacitor, where the trench has positive sloped steep sidewalls and a flat bottom according to the present invention.

FIG. 6 is an example of a CMO8 structure using trench isolation;
By using oxide-filled trenches with steep positive slope sidewalls and a flat bottom, the n+ to p+ spacing is reduced.

FIG. 7: Sputtering yield S(θ) and ion reflection coefficient R(
9 is a graph showing an example of a curve of θ).

[Explanation of symbols]

10 Silicon substrate 12 Hard mask

[Figure 1]

[Figure 2]

[Figure 3]

[Figure 4]

[Figure 6]

[Figure 5]

[Figure 7]

Claims (10)

[Claims] 1. An integrated circuit having a sidewall formed in a surface of a single crystal substrate, comprising: (a) a first portion of the sidewall having a positive slope; (b)
A second portion of the sidewall that is substantially vertical and without curves or undercuts; (C) material contacting at least a portion of the sidewall. [Claim 2] In the integrated circuit of Claim 1,
an integrated circuit having an angle of substantially 85°-87° with respect to the surface. [Claim 3] In the integrated circuit of Claim 1: the second
an integrated circuit having an angle of substantially 89°-90° with respect to the surface. 4. The integrated circuit of claim 1, wherein said material is part of a device. 5. The integrated circuit of claim 4, wherein said two devices are capacitors. 6. The integrated circuit of claim 5, wherein said capacitor has one plate adjacent said portion of said sidewall and another plate extending along said plate. . 7. The integrated circuit of claim 6, wherein said other plate includes a polycrystalline layer. 8. The integrated circuit of claim 7, wherein said other plate is separated from said portion of said sidewall by an insulating layer. 9. The integrated circuit of claim 8, wherein said one plate is adjacent said second portion. 10. The integrated circuit of claim 9, wherein a pass transistor is associated with said first portion.