JPH04209390A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To change a word length and address even after assembling and to reduce the quantity of kinds of stocked articles by connecting unused terminal to the internal circuit and deciding the word length and the quantity of addresses by an impressed voltage level. CONSTITUTION:The unused terminal 10 is utilized for a selection of the word length and the quantity of addresses without serving for the essential function in the unconnected state. For instance, in the case the word length is taken as 4 bits and the quantity of addresses is taken as 1,256K words when the output of an inverter 30 is in the high level, the word length becomes 1 bit and the quantity of addresses becomes 1M words at the time of low level. The output of inverter 30 is thus controlled by the input level supplied to the terminal 10. So, the user can select the word length and the quantity of addresses by the input level of terminal 10 and can change the word length and the quantity of addresses even after assembled. Thus, the use of the same parts is extended and the quantity of kinds of stocked articles can be reduced, and also the countermeasure to the rapid variation of demand is made easy to consider.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a technique for changing the word length and number of addresses of stored data according to specifications.

[Prior Art] The terminal arrangement of a conventional semiconductor memory is shown in FIGS. 3(a) and 3(b). Figures 3(a) and 3(b) show a 1 megabit dynamic RAM, which has a word length of 4 bits and an address count of 256 words (Figure 3(a)).
This is a dynamic RAM (FIG. 3(a)) with a word length of 1 bit and an address count of 1 megaword. Figure 3 (a
) (b), it is clear that even if the word length and number of addresses are different, not all terminal connections will be different;
The functions assigned to the 18th pin and the 26th pin are the same. In the past, there were only a few types of dynamic RAM, so if the word length and number of addresses were different, the diffusion process had to be created differently from the beginning in order to achieve an optimal design.

However, as the number of dynamic RAM types increases, it becomes necessary to reduce the number of design evaluation steps. Functions are now selected by whether or not to connect between fixed terminals and pads during bonding in the initial process, and functions are now determined in later processes with the same basic design. It has become.

FIGS. 4(a) and 4(b) show bonding options. 110 is a semiconductor chip, 100 is a power terminal lead frame, 120 is a power bat and bonding wire 1
40 connects the power terminal lead frame 100 and the power pad 120. 130 is an optional pad, and if this is not bonded to the power supply terminal lead frame 100 as shown in FIG. 4(a), the word length will be 4 bits,
It has a word configuration with 256 addresses. On the other hand, when bonding is performed using the bonding wire 141 as shown in FIG. 4(b), the word length is 1 bit and the number of addresses is 1M words. FIGS. 5(a) and 5(b) show the internal circuit. When the output of the inverter 30 is at a high level, the word length is 4 bits and the address WIi 256 is a word, and when the output is at a low level, the word length is 1 bit and the address number is IM word.

Option pad 130 power terminal lead frame 10
If it is not bonded to 0, it will look like Figure 5 (a),
The output of the inverter 30 becomes high level due to the pull-down resistor 20. On the other hand, when bonding, Figure 5(b)
The input of the inverter 30 is the electric R terminal 100.
The output of 5 becomes low level.

However, in conventional semiconductor memory devices, (word length x number of addresses) is determined at the time of bonding, so there was a problem that the word length and number of addresses could not be changed after assembly. .

However, the ups and downs of semiconductor memory devices are rapid, and if the word length and number of addresses have already been determined when the device is in stock, there is the inconvenience that it will not be possible to respond if the user's request differs from expectations. arise.

[Means for Solving the Problem] The gist of the first invention of the present application is to provide a plurality of external connection terminals including unused terminals, and an internal circuit that determines the word length and number of addresses of a memory cell according to the supplied voltage level. In the semiconductor memory device having the above, the unused terminal is connected to the internal circuit, and the word length and the number of addresses are determined by the voltage level applied to the unused terminal.

The gist of the second invention of the present application is to provide a semiconductor memory device that includes a plurality of external connection terminals including unused terminals and an internal circuit that determines the word length and number of addresses of a memory cell according to a supplied voltage level. a high voltage detection circuit that detects a high voltage supplied to a predetermined external connection terminal and outputs a detection signal;
A voltage supply circuit that is provided along with the internal circuit and determines the voltage to be supplied to the internal circuit according to the voltage applied to the unused terminal, and a detection circuit that is interposed between the unused terminal and the voltage supply circuit. It has a gate transistor that is turned on by a signal.

[Operation of the Invention] In the configuration of the first invention of the present application, the user applies a voltage corresponding to a desired word length and number of addresses to unused terminals.

In the configuration of the second invention of the present application, when the manufacturer applies a high voltage to a predetermined external connection terminal after assembly, the high voltage detection circuit
Turn on the gate transistor and connect the unused terminal to the voltage supply circuit. The manufacturer decides to use the semiconductor memory device by applying a voltage corresponding to the desired word length and number of addresses to the unused terminals.Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an input section of a first embodiment of the present invention. As is clear from FIGS. 3(a) and 3(b), terminal No. 5 has no connection in any of the semiconductor memory devices and does not contribute to its original function.

Therefore, this terminal 5 is used to select the word length and the number of addresses.When the output of the inverter 30 is high level, the word length is 4 bits and the number of addresses is 256 words. The word length is 1 bit and the number of addresses is 1M words. 20 indicates a pull-down resistor. - The input terminal 10 corresponds to the fifth terminal, and the output of the inverter 30 is controlled by the input level supplied to the input terminal 10 from the outside. Therefore, the user can change the word length,
You can select the number of addresses. If the input terminal 10 is used as an oven or a low level voltage is applied, the word length becomes 4 bits and the number of addresses becomes 256 words.If a high level voltage is applied to the input terminal 10, the word length becomes 1 bit and the number of addresses becomes 1M words. . In this embodiment, the user can select the word length and the number of addresses after shipment, but it is necessary to specify the application of a high level voltage to the input terminal 10 when the word length is 1 bit and the number of addresses is 1M words.

FIG. 2 shows a second embodiment of the invention. Input terminal 1
1 corresponds to terminal No. 22 (see FIGS. 3(a), (b) and e). 50 is a NOR gate, and 40 is a high voltage detection block. Normally, the output of the high voltage detection block 40 is at a low level, and the NOR gate 50 internally transmits the input from the input terminal 11 (terminal 22). When a high voltage (7.0 to r) exceeding the maximum normal operating range of 5.5 V is applied from the input terminal 11, the high voltage detection block 40 outputs a high level.

The role of the inverter 30, as in FIG. 1, is to determine the word length and number of addresses based on this output level. Input terminal 10 is 58
Although it is a terminal, the transfer gate N-type transistor 80 is normally turned off because the output of the high voltage detection block 40 is at a low level. The input terminal 10 is normally non-connected. Fuse 70 is a pull-up resistor 90
It has a sufficiently low resistance value compared to , and will break if a high current is applied. In the initial stage, the current flowing through the fuse is suppressed to a sufficiently low level by the 90 pull-up resistor, so the output of the 30 inverter is at a high level, resulting in a word length of 4 bits and an address number of 256 words. However, when a high voltage is applied from the input terminal 11, the transfer gate 80 is turned on, and when a high voltage is applied from the input terminal 10, a large current flows to the fuse 70, cutting the fuse 70.

When the fuse 70 is cut in this way, the output of the inverter 30 becomes low level, and the word length is 1 bit and the number of addresses is 1.
It becomes the M word. This allows the word length and number of addresses to be changed after assembly, and the user does not have to worry about changing specifications. The pull-up resistor 90 and fuse 70 constitute a voltage supply circuit.

[Effects of the Invention] As explained above, in the semiconductor memory of the present invention, the word length and the number of addresses can be changed after assembly, so that the following effects can be obtained.

(1) In a situation where the user selects the word length and number of addresses, the applications of the same part are expanded, the number of products in stock can be reduced, and it becomes easier to respond to sudden changes in demand.

(2) In situations where the manufacturer side changes the word length and number of addresses, this can be done even after assembly, making it easier to respond to sudden changes in importance.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Figs. 3 (a) and (b) are semiconductors with different word lengths and numbers of addresses. a top view of a memory device;
Figures 4 (a) and (b) are plan views showing the selection of word length and number of addresses depending on the presence or absence of bonding;
) is a circuit diagram showing the difference in internal circuitry depending on the presence or absence of bonding. 10.11... Input terminal, 12...
・・・・・・Power terminal, 20・・・・・・・・・Pull-down resistor, 30・・・φ・・・φ・Inverter, 40・・・・・・・・・High voltage detection Block, 50・
・ ・ ・ ・ ・ ・ ・ NOR gate, 60・
......Protection resistor, 70...Fuse, 80...N-type transistor for transfer gate, 90...Pull-up resistor , 100...
...Power terminal lead frame, 110...Semiconductor chip, 120...Power pad, 130...Option pad, 140.141
...bonding wire. Patent applicant: NEC Corporation

Claims (2)

[Claims] (1) In a semiconductor memory device equipped with a plurality of external connection terminals including unused terminals and an internal circuit that determines the word length and number of addresses of a memory cell according to the supplied voltage level, the unused terminals are A semiconductor memory device, characterized in that the word length and the number of addresses are determined by the voltage level applied to an unused terminal connected to the internal circuit. (2) In a semiconductor memory device equipped with a plurality of external connection terminals including unused terminals and an internal circuit that determines the word length and number of addresses of a memory cell according to the supplied voltage level, a predetermined external connection terminal A high voltage detection circuit that detects the high voltage supplied to the terminal and outputs a detection signal, and a high voltage detection circuit that is attached to the internal circuit and determines the voltage that is supplied to the internal circuit according to the voltage applied to the unused terminal. A semiconductor memory device comprising: a voltage supply circuit; and a gate transistor interposed between an unused terminal and the voltage supply circuit and turned on by a detection signal.