JPH04208565A - Ferromagnetic memory - Google Patents

Abstract

PURPOSE:To make it excellent in memory preserving property and prevent the deterioration of stored information by providing upper electrodes, where the first electrode, to which the voltage to generate a domain wall is applied, the second electrode, which suppresses the shifting of the domain wall, and the third electrode, to which the voltage to surround this domain wall is applied, are made in succession, and writing in and reading out information by the shifting of the domain wall. CONSTITUTION:When voltages VS, VT, and VD are applied to upper electrodes 17-19, the regions 21-23 corresponding to the upper electrodes 17-19 are polarized, and simple domain polarizations 26-28 are made. The writing operation is equivalent to applying voltage VD between the electrode 19 and the common lower electrode 20. When the voltage value is reset to VT>0, VD1>0 (but, VD>VD1>0), the condition 26 of the polarization of the region 21 is inverted as if the domain wall 30 has shifted to the domain wall 31, and causes 180 deg. inversion of polarization, and becomes reverse polarization. Hereby, it becomes excellent in memory preserving property and the deterioration of stored information becomes little.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a ferroelectric memory having a switching function.

(Prior Art) Conventionally, regarding ferroelectric memory, J. Merz & J.
, R, ^nderson; BELL LABOR
ECORD 5tep, 1955PP335-PP34
2 was proposed.

The structure of this ferroelectric memory is shown in FIG.

This is achieved by forming stripe electrodes 102 and 105 perpendicular to both main surfaces of the BaTiO3 single crystal thin plate 101, and by using the intersection of the picture electrodes as one memory cell 104, the hysteresis shown in FIG. It uses the same characteristics as the aTfO3 ferroelectric 01E hysteresis characteristic, and aims to realize a nonvolatile memory that corresponds to residual polarization of +Pr to "0" and -Pr to "1". Ta. However, there were some problems.

First, the hysteresis curve is not stable over time, and the value (position) of Vc shifts along the voltage axis. Second, the coercive voltage is large. Thirdly, due to the simple matrix configuration, crosstalk is large and the storage states of other memory cells are destroyed during writing/reading.

However, with the improvement of ferroelectric thin film manufacturing technology, the second problem has been resolved, and the first problem has improved. The third problem is being solved by various active matrix type memory structures.

That is, for example, JP-A-1-15869 shown in FIG.
The third problem can be solved by using an active matrix type memory structure as disclosed in Japanese Patent Publication No. 1. However, in the active matrix type memory structure, new problems such as memory retention and durability arise with respect to the first problem, and all problems have not been solved yet. The active matrix method is being researched and developed as an optimal method for practical use of ferroelectric memories.

An example of the configuration of the ferroelectric memory shown in FIG. 11 mentioned above will be explained.

In this memory cell, the ferroelectric capacitor cell 202 and the semiconductor switch 204 constitute one cell memory. In fact, in order to reduce the voltage shift due to the passage of time, which is the first problem, the reference voltage or the signal from the reference cell is input to the sense amplifier 206 as an input signal. However, the semiconductor switch 204 and the ferroelectric capacitor 2
Since one cell is composed of a pair of 02, it is necessary to match the manufacturing process of the ferroelectric thin film.

Further, FIG. 12 shows a cross-sectional view of a configuration example of the ferroelectric memory shown in FIG. 11.

As shown in the figure, the dimensions of the facing surfaces of the ferroelectric capacitor 202 and the semiconductor switch 204 do not match. Therefore, if it were simply a matrix structure, a higher density memory could be achieved and the manufacturing process would be simpler.

(Problem to be Solved by the Invention) However, in the conventional ferroelectric memory configuration, the voltage VC of the hysteresis curve shifts due to the above-mentioned temporal instability, and changes in coercive voltage and crosstalk become large. In addition, it is difficult to solve problems such as destroying the memory state of other memory cells during writing/successive writing, and unless these problems are solved, it will be difficult to realize a ferroelectric memory that does not require semiconductor switches. That's what I guessed.

(-: The purpose of the present invention is to provide a ferroelectric memory that does not require a semiconductor switch for driving, has low crosstalk and coercive voltage, has excellent memory retention, and has little deterioration of stored information. With the goal.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a ferroelectric thin film that stores information, a striped lower electrode formed on one main surface of the ferroelectric thin film, A first electrode that applies a predetermined generated voltage that generates a 180-degree domain wall to the other main surface of the ferroelectric thin film, and movement of the 180-degree domain wall that is generated by application of the predetermined voltage from the first electrode. a second electrode that applies a predetermined control voltage to suppress or encourage the 180 degree domain wall that has moved, and a third electrode that applies a predetermined surrounding voltage to surround the 180 degree domain wall that has moved; The ferroelectric body includes an upper electrode that is formed adjacent to each other with the second electrode in between, and a surrounding electrode that is formed so as to surround the entire upper electrode. It is possible to provide a ferroelectric memory in which information is written and read by moving the walls.

(Function) In the ferroelectric memory configured as described above, the cell structure itself serves both as an active switch and a capacitor cell, and a write line and a call line are provided separately, so that the memory state of other cells is not affected.

Furthermore, since the memory cell of the present invention does not include a switching FET, the device configuration is simplified, and since the dielectric thin film of the memory cell has a structure that is continuous in the plane direction, the above-mentioned problem can be avoided. Can provide body memory.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(e) show a schematic structure of a ferroelectric memory according to the present invention, and will be described in detail.

This nonvolatile ferroelectric memory has a structure in which a ferroelectric single crystal thin film is sandwiched between two electrodes. For example, the ferroelectric single crystal thin film 1 is a thin film formed by sputtering PbTiO2, and both sides of its main surface are upper electrode 2a, lower electrode 2b
is formed (the substrate is not shown). Further, the film thickness direction is in the crystal axis (100) direction, which coincides with the C axis (easy polarization axis).

First, in FIG. 1(a), an applied voltage Vap which is much larger than the coercive voltage Vc on the hysteresis curve of the ferroelectric thin film shown in FIG. 1(e) is applied. After applying the applied voltage Vap for a sufficiently long time, when the applied voltage Vap-0 is set, the entire thin film becomes in the same direction remanent polarization (Pr) state 3, that is, a single domain state.

Next, in FIG. 1(b), when an applied voltage -Vap having the opposite polarity to that in FIG. is generated in a wedge shape to form the domain wall 6. When the reverse applied voltage -Vap is applied more than that, the wedge-shaped domain 5 grows further, and the domain wall 6 moves to the domain wall 7.

The domain wall 6 or 7 in the state shown in FIG. 1(b) is very unstable, and after returning the applied voltage to Vap-0, the tip 8 of the domain wall is It either returns to the nucleus 4 side or reaches the rear surface 2b side as it is.

In FIG. 1(C), the application time of the reverse applied voltage -Vap is longer than the application time of FIG. 1(b), although the application time of the applied voltage Vap of FIG. 1(a) is not specific. When a reverse applied voltage -Vap is applied between both electrodes, a columnar domain 9 is formed. At this time, the domain wall 10 has a reverse applied voltage of −V
When the application time of ap is made longer, the domain wall 11 moves along the thin film surface. Even in the state of the domain wall, the domain wall 10 or the domain wall 11, when the reverse applied voltage is -vap-□v, unlike the case of the domain wall 6, it is stabilized at that position. However, the total polarization amount of the thin film is the reversed polarization 1
Since it corresponds to the sum of 2 and the polarization 13 of the uninverted portion of the original polarization Pr3, it is a small value.

That is, it is in a state where it has depoled to the value of P shown in FIG. 1(e).

Further, FIG. 1(d) shows a structure in which the ferroelectric thin film has a region in which no electrode is formed. This figure (d) shows the reverse applied voltage -Vap shown in figure (C).
The application time is further increased. The resulting domain wall moves to the end of the electrode, and when the reverse applied voltage -Vap continues to be applied, the domain wall 14 moves to the part 15 (where there is no electrode) (
It moves in the direction of the arrow).

The movement of domain walls as described above has been confirmed, a domain wall movement device has been proposed, and a report confirming the operation of the device has been made.

The present invention also utilizes the domain wall moving operation shown in FIGS. 1(c) and 1(d). Generally this type of domain wall (180
The movement of the 90'' domain wall does not cause distortion around the wall, unlike the movement of the 90'' domain wall, so it is possible to move at high speed, and the maximum speed reaches the transverse sound velocity of the material. .

Therefore, the transverse sound velocity of the ferroelectric material used is 3000 m
/sec, and the maximum domain wall movement distance of the device is 1
When it is 0μm, 10XIO-6/3000-3.3nsec...(1
), and high-speed operation is possible.

The above transverse wave sound speed is BaTiO3, PbTiO3
This value can be achieved by using a belobumakite-based ferroelectric material such as PZT. In addition, the operation time on the order of n5ec is short compared to the switching time of existing semiconductor devices such as DMO8, but in reality, there is a problem with pinning due to defects in the thin film crystal, non-inversion of polarization that exists on the surface or at the interface with the electrode. Nuclear pinning slows domain wall migration times by an order of magnitude, or is comparable to the behavior of current devices.

Next, the operating principle of the nonvolatile ferroelectric memory will be explained with reference to FIGS. 2(a) and 2(b).

FIGS. 2(a) and 2(b) show a common lower electrode 20 and an upper electrode 17 separated into three regions on the ferroelectric thin film 16.
18 is a cross-sectional view of one memory cell consisting of 18.19 cells. FIG.

First, as shown in Part 2(a), each upper electrode portion 17.1
8.19, voltages Vs, VT, and VD are made positive voltages, and their memory states are applied simultaneously. As a result, the area 2 of the thin film corresponding to each of the upper electrode portions 17, 18° 19
1.22.23 are polarized to form a single domain polarization 26°27.28 pointing in the direction shown. Among the non-electrode formation regions, the region 25 sandwiched between domain regions facing the same direction on both sides is polarized in the same direction as the single domain polarization 27° 28 from FIG. 1(d). I understand.

On the other hand, area 2 is sandwiched between domains facing in different directions on both sides.
4 is not polarized because the influences from both sides cancel each other out. The memory state is determined by the direction in which the polarization 28 of the region 23 faces.

For example, when a negative voltage is applied to the voltage VD and the polarization 28 is in the state of the arrow, it is defined as "0°," and when the polarization is in the opposite direction, the voltage (2) is defined as "]". That is, they correspond to FIGS. 3(e) and 3(a), which will be described later.

Therefore, the write operation corresponds to applying the voltage VD between the electrodes 19 and 20.

The polarization state of each region in FIG. 2(a) is determined by the voltage Vs
, VT, and V are maintained even if they are set to "OV".

Next, the voltage value is V5 > 0. When a voltage that makes vT<Q, vD ``0'' is applied, each polarization state 26, 27°28 remains almost unchanged. However, from a certain point on, the voltage value suddenly changes to VT>Q, Vrx>O(( BL, VD>VDI>0
) is reset to the voltage (voltage ■, is, ■, 〉0
The polarization state 26 of the region 21 is reversed as if the domain wall 30 or the domain wall 31 had moved (shaded region).

Since the domain wall 30 does not move when the voltage VT<0, the voltage V(0) serves as a trigger signal for movement of the domain wall. Note that the voltage VD+ is as shown in FIG. 1 (e
) is the critical voltage that changes from the linear system change region to the nonlinear system change region in the hysteresis curve shown in FIG. 5, which will be described later.
This is a voltage that does not cause any change in the polarization state 28 of the region 23 even if the voltage is suddenly changed by VDIl.

As mentioned above, the domain wall 30 or the domain wall 31 that was in the area 21
When it moves again, the meshed portion in FIG. 2(b) undergoes 1000 polarization inversion and becomes polarized in the opposite direction. Then, as shown in FIG. 2(a), let the polarization of the region 23 after writing "0" be Pl, and as shown in FIG. 2(b), the total polarization of the region 23 after moving to the domain wall 30 or domain wall 31. If the polarization amount is P2, the polarization change amount ΔP is P1+P2
becomes. Assuming that it takes Δ seconds to move from the position of the domain wall 30 or 32 to the position of the domain wall 31, a current of l-ΔP/Δt flows through the terminal 33 of the electrode 19. It turns out.

In addition, in FIG. 2(a), if reverse polarity is written, polarization reversal will not occur, so the polarization change amount ΔP
-0, that is, the current becomes i-0. In this case, the domain wall 31
or not formed.

The above-mentioned operation will be explained in more detail below with reference to FIGS. 3(a) to 6. Figure 3 (a) to (h)
2 is a top view of the nonvolatile ferroelectric memory shown in FIG. 2, viewed from above.

Here, in FIGS. 3(a) to (d), -, Ps (corresponding to "1°) is written (a), and "1° is stored (b).
, "1" is read out (C), and rewritten (d). 3(e) to (h, ) are 10Ps (“
Write (e) “0” (corresponding to
) shows the operation.

First, in FIG. 3(a), the domain wall 3 surrounds the source electrode 17, the trigger electrode 18, and the drain electrode 19.
3 are placed on this electrode, to prevent the domain wall that has moved from overrunning into adjacent cells, or to prevent the domain wall under each electrode from seeping significantly and affecting neighboring cells. In order to prevent this from happening, a large negative voltage is always applied.

And the terminals 35, 36.37 are each electrode 17°18.19
A source terminal voltage S, a trigger terminal voltage T, and a drain terminal voltage R are applied to each of the terminals. The positive and negative (+, -) signs are for the respective terminals 35 and 3.
6.37 shows the polarity of the voltage applied.

In the same figure (a), when a voltage of the polarity shown is applied to each terminal (writing "1"), the area surrounded by the dotted line 34 is +Ps, and all other areas are -Ps. .

Next, even if only the train terminal voltage is set to OV, or even if all including the source terminal voltage S5 and trigger terminal voltage T are set to OV, the state does not change. Also, the memory retention of the “1” state, “
Regarding the writing of 0゛ (e) and the memory retention of ``0'' (f), the polarity of the voltage supplied to the D terminal is different.
The area surrounded by the dotted line + Ps area or two locations (34°38
), it is no different from writing “1”.

Next, the read operation will be explained.

FIGS. 3(c) and 3(g) show the operation of switching the T terminal from a negative voltage to a positive voltage. With this switching operation,
The zone wall 34 passes under the electrode 18 and moves to a position under the D electrode 39 or 40. At this time, the aforementioned voltage +V 2o is applied to the above terminal.

If the voltage is +V2D-0, the movement of the domain wall becomes slow, the read current ID becomes small, and the switching time increases, making it impossible to achieve a high-speed operation of 100 μsec or less. Furthermore, when "0" is read, the area surrounded by the dotted line in FIG. 3(g) is all 10 Ps, so no read current flows. That is, when the voltage applied to the electrode is changed from -V to +VT, "]" and "0" are determined based on whether or not a current is detected at the D terminal. As shown in the same figure (C), when reading from the "1" state, the "1" state is destroyed and becomes the "0" state, so rewriting the "1" state To do this, since the readout detection current 1D always flows when the device is destroyed, -VD should be automatically applied to the D terminal when the readout detection current 1D is detected. °When reading, “○
There is no need to reapply the voltage because the state of " is not destroyed.

Furthermore, since the detection current iD does not flow, the "1" rewriting circuit may remain as it is.

Next, FIG. 4 shows that each terminal has a voltage V5. V-cho.

This is a time chart showing a state in which Vo is applied, and the fifth
The figure shows a hysterin curve when that voltage is applied. FIG. 6 shows the voltage V3 when processing is performed in the order of "1" write, hold, "1" read, and rewrite. V
FIG. 2 is a time chart showing the readout detection current iD and a time chart regarding the power supply voltage and VD. FIG. If an attempt is made to write a new "1" into the cell' in which "0" has been stored, an inversion current will flow, but since the polarity is opposite to the inversion current id that flows when reading "1", no rewriting operation will occur.

An example of actually forming a non-volatile ferroelectric memory as described above is shown in the top view of the cell structure (a
) and the cross-sectional view (b).

This cell structure is, for example, S'i (100),
kigo (100), S'rT i○, (100)
- A lower stripe electrode 44 of platinum or the like is formed by sputtering or the like on a single crystal substrate 42 of sapphire (100) or the like.

If the film is formed without heating the substrate 42 to about 800° C. during this formation, the platinum also becomes (1,OO) oriented. Furthermore, Pb(ZR+-x T,
3 (Here X, 屹 6-100) Form a film. If the substrate heating conditions and heat treatment conditions are set appropriately here, the ferroelectric thin film 43 becomes (100) oriented. moreover,
Upper electrodes 45°46.47.48 are formed. Since the upper electrode 45 is electrically connected to the upper electrodes 45 of all cells, after forming the entire upper electrode, the region 53 is removed by reactive ion etching (RIE) or the like.

Next, an SIO2 insulating film 49 is formed by CVD or the like, and after contact holes are opened, word lines are formed.

Wiring lines 50, 51 and 52 corresponding to drive lines and bit lines are formed.

FIG. 8 shows a wiring diagram when one cell in FIGS. 7(a) and 7(b) is configured as an nXn bit memory.

In the wiring diagram of FIG. 8, a word line (trigger line) 51 is common to all cells. Also, drive line 53° bit line 5
2 is commonly connected in each row, and the ground wire is commonly connected in each column. Furthermore, electrodes are additionally formed in all regions other than the memory cells, and a voltage VSR<'0 is applied thereto. This voltage V
Crosstalk between cells can be completely eliminated by applying SR.

Next, the operation of the memory configured in this way will be explained.

First, reset all cells and set them to the initial state.

That is, the memory state is set to "0". In this case, select cells sequentially and apply voltage +y to the row lines (S', D lines).
, ', +Vo is applied, the column line (E line) is grounded, a voltage -VT is applied to the T line, and a negative voltage is applied to the voltage VsR. Also, the voltage element vT.

vSR is similarly applied when selecting any memory cell.

Next, for example, a case in which "1" is written to the memory cell 541 will be described.

First, the memory cell 541 is
Select. Then, voltages VS and VD with polarities as shown in FIG. 3(a) are applied to the wirings 3S and 3D, and the wiring E4
is at ground potential. As shown in FIGS. 4 and 6, during writing, VT is always set to O. Unselected line ID.

2D, El, E2. E3 and the like are made to have a floating potential with respect to the ground potential.

Next, when reading the state "1" of the memory cell 541, the row line 3 of the decoders 55, 56 and 57 is
S, 3D are selected on the column line E4, and voltages Vs, VD, DT having polarities as shown in FIG. 3(c) are applied at the same timing as in FIG. 6. At this time, a positive voltage is applied to the voltage VT,
A positive voltage VDl is applied to the voltage VD, and a polarization inversion current flowing through the 3D line is detected. The pulser 58 generates a positive voltage when writing "0°" or "1", or voltage -■1 when rewriting, and voltage P1 when reading.Then, the polarization inversion current generated when reading "1" is detected by the inversion current detector 59, and generates a rewrite signal Vf when it is equal to or greater than a predetermined value.

The rewrite signal Vf is a write signal (Luther 5).
8, and 1'' is immediately rewritten during selection of the read cell.

Next, FIG. 9 shows a memory system constructed using the above-mentioned memory cells, and will be described in detail.

First, an address for a specific memory cell is received at the address terminal 66. This may be parallel input. Furthermore, this memory system is activated by inputting a low-level chip enable signal CE to the terminal 63.

The chip enable signal CE is also sent to circuits 55, 56 and 57.

A read/write command (R/W) signal is input from the terminal 64 of this memory stem. Further, an output enable signal CE is inputted from the terminal 65 to put the memory system on standby so that it can be read and output. Further, the address signal (ADD signal) is transmitted to the source line, decoder line decoder and ground line decoder 57 via the terminal 66.
and enter it. The ADD signal supplies pulse voltages from the drive circuits 67 and 58 to the memory cells.

Further, the R/W command signal operates a circuit 68 that supplies a trigger signal to the trigger line.

The chip enable signal CE is transmitted via a terminal 66 to
It is input to the sense timing control circuit 61 and each circuit 55, 56, and 57. Similarly, read/write command (R
/W) signal is input to the sense timing control circuit 61 via the terminal 64, and the output enable signal CE is input to the sense timing control circuit 61 via the terminal 65. The output from the sense timing control circuit 61 is input to five sense amplifiers, and the sense amplifier 59 is further supplied with a reference voltage input via a line 69. The sense amplifier 59 produces the required data state on the drain line 70 for a read operation. The read/write signal is further sent to the data input/output and decoder circuits via the terminal 7. Further, the output enable signal CE is inputted to a circuit 60 via a terminal 65, and input data is inputted to the circuit 60 from a terminal 73.

As described above, the feature of the present invention is that, unlike the conventional simple matrix structure, the write line and the call line are separate, so that the storage state of other cells is not destroyed during reading.

That is, the cell structure itself serves both as an active switch and a capacitor cell, and is similar to the case where one cell is composed of one set of FET switch 24 and capacitor 22 in FIG. 11. In other words, does the terminal T correspond to the word line 28?
The terminal S corresponds to the drive line 26, and the terminal T corresponds to the bi-soto line 30.

Furthermore, since the ferroelectric memory of the present invention does not require an external switching FET, it is simpler than the conventional device configuration shown in FIG. 12 described above.

Furthermore, the memory cell of the present invention requires selective etching or selective growth in order to continuously form the ferroelectric thin film portion of the conventional memory shown in FIG. 12 in the desired shape and dimensions in the plane direction. be.

In the case of selective etching, the etching process for the ferroelectric film becomes complicated, and in the case of selective growth, a wet film forming process such as a sol-gel method, which forms a good ferroelectric thin film, cannot be used.

However, in the structure of the present invention, since the dielectric thin film is continuous in the plane direction, both problems can be avoided.

Furthermore, the present invention is not limited to the one embodiment described above, and it goes without saying that various modifications and applications can be made without departing from the gist of the invention.

[Effects of the Invention] As detailed above, according to the present invention, the drive semiconductor switch is eliminated, the relo talk and coercive voltage are small, the memory retention is excellent, and the stored information is less likely to deteriorate. can be provided.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are diagrams showing a schematic configuration of a ferroelectric memory according to the present invention, and FIGS. 2(a) and (b) are one cell of the ferroelectric memory of FIG. A cross-sectional view showing the cross-section of
3(a) to (h) are top views of the nonvolatile ferroelectric memory shown in FIG. 2, and FIG. 4 shows each of the nonvolatile ferroelectric memory cells shown in FIG. Voltage V5. V
□. Figure 5 is a time chart showing the state in which VD is applied, Figure 5 is a diagram showing the hysteresis characteristics when each voltage shown in Figure 4 is applied, Figure 6 is a diagram showing the applied voltages and the voltages when processing is performed in a predetermined sequence. Time chart of readout detection current, Fig. 7(a)
7(b) is a top view showing the top surface of the nonvolatile ferroelectric memory cell actually formed; FIG. 7(b) is a sectional view showing the cross section of the nonvolatile ferroelectric memory cell shown in FIG. 7(a); 8 is a wiring diagram showing a memory configuration of nxn bits in one cell shown in FIG. 7(a), FIG. 9 is a configuration diagram showing a memory system configured using the memory cells shown in FIG. 8, 10th
The figure is a block diagram showing the structure of a conventional ferroelectric memory.
1 is a block diagram showing the active matrix type memory structure of a conventional ferroelectric memory, and FIG. 12 is a sectional view showing a cross section of the example structure of the ferroelectric memory shown in FIG. 11. 1... Ferroelectric single crystal thin film, 2a... Upper electrode. 2b: lower electrode, 3: single domain state, 4: domain-inverted nucleus, 5... domain-inverted nucleus in the opposite direction, 6, 7, 10°11
... Domain wall, tip of domain wall 8.9... Columnar domain, 1
2... Polarization, 13 Polarization of uninverted part, 14... Domain wall,
15... Part without electrode, 42... Single crystal substrate, 45° 46.47.48... Upper electrode, 4 pieces 5102 Insulating film, 50... Word line, 51... Drive line, 52...・
Bit line, area 53° Applicant's representative Patent attorney Jun Tsuboi lt3 Figure 3 (a) Figure 3 (b) Figure 3 (c) Figure 3 (d) Figure 3 (e) Figure 3 (f) ) Figure 3 (9) Figure 3 (h) j [Figure 4 Figure 7 (b) Katama Figure 6] Figure 0 Figure 11

Claims (1)

[Claims] 1. A ferroelectric thin film for storing information; a striped lower electrode formed on one main surface of the ferroelectric thin film; and on the other main surface of the ferroelectric thin film, A first electrode that applies a predetermined generated voltage that generates a 180-degree domain wall, and a predetermined control voltage that suppresses or promotes movement of the 180-degree domain wall that is generated by application of the predetermined voltage from the first electrode. A second electrode for applying voltage and a third electrode for applying a predetermined surrounding voltage for surrounding the moved 180 degree area wall are arranged such that the first and third electrodes are adjacent to each other with the second electrode in between. It is composed of an upper electrode formed in series and a surrounding electrode formed to surround the entire upper electrode, and writes and reads information by moving the 180 degree domain wall within the ferroelectric body. A ferroelectric memory characterized by: 2. A plurality of first electrodes extending in a direction perpendicular to the stripe length direction of the striped lower electrode with the ferroelectric thin film interposed therebetween, and formed so as to electrically connect the first electrodes of the memory cells lined up in that direction. The wiring row, a plurality of second wiring rows similarly formed to conduct the second electrodes to each other, and a plurality of third wiring rows similarly formed to conduct the third electrodes to each other are each arranged in a stripe shape. 2. The ferroelectric memory according to claim 1, wherein the ferroelectric memory has a wiring configuration in which the plurality of second lines are commonly connected to one predetermined terminal. 3. Claim 1, wherein the ferroelectric thin film has a belobukite shape and is C-axis oriented in the thickness direction.
Ferroelectric memory described. 4. The ferroelectric thin film is made of Pb (Zr_1_-_xTi_
4. The ferroelectric memory according to claim 3, wherein x) O_3 (x=0.6 to 1.0). 5. The memory content to be stored in the ferroelectric memory is determined by the polarization direction of the drain electrode portion, and the write operation is determined by the polarity of the voltage applied to the drain electrode, and the write operation is determined by the polarity of the voltage applied to the drain electrode, and the write operation is determined by the polarization of the voltage applied to the drain electrode. 2. The ferroelectric device according to claim 1, further comprising readout determining means for determining whether the ferroelectric device is in one of the binary storage states based on whether or not a current accompanying polarization inversion flows to the drain terminal when the wall moves. body memory. 6. The 180 degree domain wall movement can be promoted by making the polarity of the voltage applied to the trigger electrode the same as the voltage polarity applied to the source electrode, and the domain wall movement can be suppressed by applying a voltage of a different polarity. 2. The ferroelectric memory according to claim 1, further comprising control means for controlling the ferroelectric memory by controlling the ferroelectric memory.