JPH04208080A - Driver for monolithic piezoelectric element - Google Patents

Driver for monolithic piezoelectric element

Info

Publication number
JPH04208080A
JPH04208080A JP2336600A JP33660090A JPH04208080A JP H04208080 A JPH04208080 A JP H04208080A JP 2336600 A JP2336600 A JP 2336600A JP 33660090 A JP33660090 A JP 33660090A JP H04208080 A JPH04208080 A JP H04208080A
Authority
JP
Japan
Prior art keywords
piezoelectric element
time
transistor
turned
time constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2336600A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Watabe
嘉幸 渡部
Junichi Watanabe
純一 渡辺
Takahiro Sometsugu
孝博 染次
Shigeru Sadamura
定村 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP2336600A priority Critical patent/JPH04208080A/en
Publication of JPH04208080A publication Critical patent/JPH04208080A/en
Pending legal-status Critical Current

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  • General Electrical Machinery Utilizing Piezoelectricity, Electrostriction Or Magnetostriction (AREA)

Abstract

PURPOSE:To improve reliability and to provide excellent durability by forming a circuit for reducing a time constant at the time of falling an applied voltage smaller than a mechanical resonance time constant of a piezoelectric element. CONSTITUTION:At the time of Vi2=0 at Vi1=5V, a transistor 3 is turned ON, and a transistor 4 is turned OFF. Accordingly, since a current flows to a laminated piezoelectric element 1 through resistors Ru, Rc, the applied voltage V of the element exhibits a value substantially equal to VD. Then, at the time of Vi2=5V at Vi1=0, the transistor 3 is turned OFF, and the transistor 4 is turned OFF. Accordingly, charge stored in the element 1 is discharged through the resistors Rc, Rd. In this case, in order to prevent an erroneous operation by switching, a pause time Tc is provided at the time of switching input voltages Vi1 and Vi2. Thus, simultaneous ON of the transistors is prevented. Further, VP rises when the Vi1 rises, and VP starts, on the contrary, to fall when the Vi2 rises.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、微少位置決め機構やマスフローコントローラ
等に用いられる、積層型圧電素子の駆動回路に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit for a laminated piezoelectric element used in a minute positioning mechanism, a mass flow controller, and the like.

〔従来の技術〕[Conventional technology]

従来、積層型圧電素子の駆動回路は第2図の如く、例え
ばトランジスタ等により構成し、その印加電圧を制御し
ていた。
Conventionally, as shown in FIG. 2, a drive circuit for a laminated piezoelectric element has been constructed of, for example, a transistor, and the applied voltage has been controlled.

以下、第2図に従って、従来の技術について託述する。The conventional technology will be described below with reference to FIG.

トランジスタ2のコレクタ端子には、積層型圧電素子1
が接続されており、かつコレクタには、抵抗Ruを介し
て、積層型圧電素子2を直接駆動するための電圧VDが
印加されている。−船釣にこのVDはおよそ100〜1
50Vが普通であるが、積層体1の仕様により、400
V程度の高電圧が印加される場合もある。今、制御電圧
v1がゼロの時、トランジスタ2のコレクターエミッタ
間は開放状態になっている為、積層型圧電素子2には、
はぼVDと等しい電圧が印加されている。次に、vlを
上昇させると、それに応じて、エミッタ電流ieが流れ
るため、圧電素子2の印加電圧は下がる。
A multilayer piezoelectric element 1 is connected to the collector terminal of the transistor 2.
is connected to the collector, and a voltage VD for directly driving the multilayer piezoelectric element 2 is applied to the collector via a resistor Ru. -This VD for boat fishing is about 100-1
50V is normal, but depending on the specifications of laminate 1, 400V
A high voltage on the order of V may be applied. Now, when the control voltage v1 is zero, the collector-emitter of the transistor 2 is in an open state, so the stacked piezoelectric element 2 has
A voltage approximately equal to VD is applied. Next, when vl is increased, the emitter current ie flows accordingly, so that the voltage applied to the piezoelectric element 2 decreases.

以上の構成により、圧電素子2の印加電圧は、入力電圧
Viに依存して変化するよう構成されている。
With the above configuration, the voltage applied to the piezoelectric element 2 is configured to change depending on the input voltage Vi.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上述の方法では静的な状態で積層型圧電
素子を駆動する際には、何ら問題はないが、ステッピン
グ波形等で駆動する際には、その時定数が素子の寿命に
太き(影響を与える。
However, with the method described above, there is no problem when driving a stacked piezoelectric element in a static state, but when driving with a stepping waveform, etc., the time constant increases (impacts) the life of the element. give.

本来、積層型圧電素子は機械的な共振周波数を持ち、そ
れよりも高周波で駆動する場合に、積層型圧電素子には
、大きな圧縮荷重と引っ張り荷重がかかる。特に、積層
型圧電素子は積層構造ゆえに、圧縮荷重には非常に安定
しているが、引っ張り荷重には極めて弱く、長期の使用
に渡っては、積層体間で剥離を生じたり絶縁破壊につな
がる。
Originally, a laminated piezoelectric element has a mechanical resonance frequency, and when driven at a higher frequency than that, a large compressive load and a large tensile load are applied to the laminated piezoelectric element. In particular, because of its laminated structure, laminated piezoelectric elements are extremely stable under compressive loads, but extremely weak under tensile loads, and over long-term use, this can lead to delamination between the laminated bodies or dielectric breakdown. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、上記問題点を解決すべく、積層型圧電素子の
駆動回路において、印加電圧の立ち下がり時の時定数が
、概圧電素子の機械的共振時定数よりも小さくなるよう
回路を構成したことを特徴とする駆動回路である。
In order to solve the above-mentioned problems, the present invention has a drive circuit for a multilayer piezoelectric element configured such that the time constant when the applied voltage falls is approximately smaller than the mechanical resonance time constant of the piezoelectric element. This is a drive circuit characterized by the following.

C実施例〕 本発明の1実施例を第1図に示す。C Example] One embodiment of the invention is shown in FIG.

第1図では、圧電素子にステッピング波形を印加すべく
、電圧上昇、下降時に単独でその電圧をスイッチング出
来るよう2石のトランジスタを用いた。以下、図に従っ
て説明する。
In FIG. 1, in order to apply a stepping waveform to the piezoelectric element, two transistors are used so that the voltage can be switched independently when the voltage rises or falls. The explanation will be given below according to the figures.

RI+−10にΩ、R1□;10にΩ なるベース抵抗
をトランジスタ3.4のベース端子に夫々接続し、かつ
、1ヘランジスタ3のエミッタとトランジスタ4のコレ
クタを共通化した。さらに、その接続点より、保護抵抗
Rcを介して、積層型圧@素子1を接続した。本回路の
動作原理について記述する。
Base resistors of Ω to RI+−10 and Ω to R1□;10 were connected to the base terminals of the transistors 3 and 4, respectively, and the emitter of the 1 helang transistor 3 and the collector of the transistor 4 were made common. Further, the multilayer pressure element 1 was connected to the connection point via the protective resistor Rc. The operating principle of this circuit will be described.

Vi、=5Vで、V1□=ゼロの時、1〜ランジスタ3
はON状態、4はOFFになっている為、電流は、Ru
、Rcを介して、積層型圧電素子1に流れ込むため、圧
電素子の印加電圧VpはほぼVDと等しい値を示す。次
に、V iH=ゼロで、■+2=5Vとした時、トラン
ジスタ3はOFF、4がONになる為圧電素子1に蓄え
られた電荷は、Re、Rdを介して放電される。この際
に、スイッチングによる誤動作を防ぐために、第3図の
如く入力電圧Vi1とVi2との切り換え時に、休止時
間TCを設けた。これにより、トランジスタが同時にオ
ンすることを防いでいる。
When Vi = 5V and V1□ = zero, 1 to transistor 3
Since 4 is in the ON state and 4 is in the OFF state, the current is Ru
, Rc into the multilayer piezoelectric element 1, the voltage Vp applied to the piezoelectric element has a value approximately equal to VD. Next, when ViH=zero and (2)+2=5V, transistor 3 is turned off and transistor 4 is turned on, so that the charge stored in piezoelectric element 1 is discharged via Re and Rd. At this time, in order to prevent malfunctions due to switching, a pause time TC is provided when switching between input voltages Vi1 and Vi2 as shown in FIG. This prevents the transistors from turning on at the same time.

さらに、本回路の電圧動作波形を第4図に示すが、vi
lの立ち上がり時にVpも立ち上がり、Vi2の立ち上
がり時に、逆にVpは下降し始める。このVpの立ち上
がり、下降時の時定数は、積層型圧@素子lの静電容量
をCOとした場合に、立ち上がり時  Tu=Ru−R
c−C。
Furthermore, the voltage operation waveforms of this circuit are shown in FIG.
When l rises, Vp also rises, and when Vi2 rises, Vp begins to fall. The time constant at the rise and fall of this Vp is as follows: Tu=Ru-R
c-C.

下降時     Td=Rd−Rc−G。When descending Td=Rd-Rc-G.

となる。本実施例は、圧電素子2にPZT系の素子5m
m X 5mm X 40mmのものを用い、その静電
容量はlμFであった。更に、機械共振周波数を調べた
ところ、およそ20kHzであった。従って、この素子
の機械共振時定数は、 TM=1/20xlO’=50μsecとなる。
becomes. In this embodiment, the piezoelectric element 2 is a PZT-based element 5m.
The capacitance was 1 μF. Furthermore, when the mechanical resonance frequency was investigated, it was approximately 20 kHz. Therefore, the mechanical resonance time constant of this element is TM=1/20xlO'=50 μsec.

本回路では、故意にこの時定数よりも立ち下がりの時定
数を小さくするため、回路中のRc= Rd=短絡とし
た。また、Ruは2にΩ一定とした。
In this circuit, in order to intentionally make the falling time constant smaller than this time constant, Rc=Rd=short circuit in the circuit. Further, Ru was set to be constant at 2Ω.

これにより、立ち上がり及び立ち下がりの時定数は夫々 Tu=Ru−Rc−G。As a result, the time constants for rising and falling are respectively Tu=Ru-Rc-G.

=2xlO”xlXIO’ =0.002=2msec Tdは、短絡状態となるため、はぼ静電容量のみの放電
定数で決定されるが、 Td=txto ’=lμsec と近似した。
=2xlO''xlXIO' =0.002=2msec Td is determined by the discharge constant of only the capacitance since it is in a short circuit state, but it was approximated as Td=txto'=lμsec.

上記の条件で、印加電圧の繰り返し周期を3秒3秒のデ
ユーティで駆動した。その結果、第5図(a)の様な結
果が得られた。上記の回路で、駆動試験を106回行っ
たところ、サンプル数30ケの内、25ケが、クラック
や火花放電等の不良を起こした。この結果より、立ち下
がり時定数が機械的時定数よりも小さいと、不良が発生
し易いということがわかる。
The device was driven under the above conditions with a repetition period of applied voltage of 3 seconds and a duty cycle of 3 seconds. As a result, results as shown in FIG. 5(a) were obtained. When the above circuit was subjected to a drive test 106 times, 25 out of 30 samples had defects such as cracks and spark discharge. This result shows that if the falling time constant is smaller than the mechanical time constant, defects are likely to occur.

次に、本発明の妥当性を証明する上で、以下の条件の駆
動試験を行った。
Next, in order to prove the validity of the present invention, a driving test was conducted under the following conditions.

(1)共通事項 最大印加電圧・・150■ 繰り返しデユーティ・・3sec:3secRu=2に
Ω (2)パラメータ (i)Rc−短絡 Rd=50Ω (ii)Rc=短絡 Rd=IKΩ とした場合、(i)の際に、その立ち下がりの時定数は Td=50X IX 10 ’=50μsecとなり、
積層型圧電素子の機械共振時定数と等しくなる。また(
11)では Td=l X 103X I X 10 ’=I X 
10−”=1msecと、明かに、積層型圧電素子のそ
れよりも大きくなる。この条件により、首記と同様の実
験を行ったところ、第5図(b)の結果が得られた。い
ずれの値も、その不良発生率は、大きく改善されている
ことがわかる。
(1) Common items Maximum applied voltage: 150 ■ Repeat duty: 3 sec: 3 sec Ru = 2 to Ω (2) Parameter (i) Rc - short circuit Rd = 50 Ω (ii) Rc = short circuit Rd = IKΩ In case of i), the time constant of the fall is Td=50X IX 10'=50μsec,
It is equal to the mechanical resonance time constant of the laminated piezoelectric element. Also(
11), Td=l x 103X I x 10'=I
10-" = 1 msec, which is clearly larger than that of the laminated piezoelectric element. Under these conditions, an experiment similar to that described above was conducted, and the results shown in Figure 5 (b) were obtained. It can be seen that the value of , as well as the defect rate, has been greatly improved.

従って、積層型圧電素子の信頼性を向上させるためには
、印加電圧の特に立ち上がりの時定数を素子の機械共振
時定数よりも太き(すればよい。
Therefore, in order to improve the reliability of the multilayer piezoelectric element, the time constant of the applied voltage, especially the rise, may be made thicker than the mechanical resonance time constant of the element.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、従来不充分であった積層型圧電素子の
信頼性がより向上し、耐久性に優れた圧電アクチュエー
タを供給することができる。
According to the present invention, the reliability of the laminated piezoelectric element, which has been insufficient in the past, is further improved, and a piezoelectric actuator with excellent durability can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る駆動回路の一実施例を示す電気回
路図、第2図は従来の回路図、第3図は本発明に係る駆
動回路に人力する制御電圧のタイムチャート図、第4図
は本発明に係る駆動回路内の動作を示すタイムチャート
図、第5図は本発明に係る駆動回路を用いた場合の不良
発生を示す図である。 1積層型圧電素子、2トランジスタ、3トランジスタ、
4.トランジスタ。 第1図 n 第2図 第3図 第4図 一ヨ     VP 第5図 (G) (b) 駿動回数(回)  (ii)
FIG. 1 is an electric circuit diagram showing an embodiment of the drive circuit according to the present invention, FIG. 2 is a conventional circuit diagram, and FIG. 3 is a time chart diagram of the control voltage manually applied to the drive circuit according to the present invention. FIG. 4 is a time chart showing the operation within the drive circuit according to the present invention, and FIG. 5 is a diagram showing the occurrence of defects when the drive circuit according to the present invention is used. 1 stacked piezoelectric element, 2 transistors, 3 transistors,
4. transistor. Figure 1 n Figure 2 Figure 3 Figure 4 1yo VP Figure 5 (G) (b) Number of flight movements (times) (ii)

Claims (1)

【特許請求の範囲】[Claims]  圧電磁器板を多層化し、電圧を印加することにより、
変位を得るべく構成した積層型圧電素子を駆動するため
の回路であつて、印加電圧の立ち下がり時の時定数が、
圧電素子の機械的共振時定数よりも小さくなるように構
成したことを特長とする積層型圧電素子の駆動回路。
By layering piezoelectric ceramic plates and applying voltage,
This is a circuit for driving a laminated piezoelectric element configured to obtain displacement, and the time constant when the applied voltage falls is
A drive circuit for a laminated piezoelectric element, characterized in that it is configured to be smaller than the mechanical resonance time constant of the piezoelectric element.
JP2336600A 1990-11-30 1990-11-30 Driver for monolithic piezoelectric element Pending JPH04208080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2336600A JPH04208080A (en) 1990-11-30 1990-11-30 Driver for monolithic piezoelectric element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2336600A JPH04208080A (en) 1990-11-30 1990-11-30 Driver for monolithic piezoelectric element

Publications (1)

Publication Number Publication Date
JPH04208080A true JPH04208080A (en) 1992-07-29

Family

ID=18300832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2336600A Pending JPH04208080A (en) 1990-11-30 1990-11-30 Driver for monolithic piezoelectric element

Country Status (1)

Country Link
JP (1) JPH04208080A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096554A1 (en) * 2007-02-09 2008-08-14 Konica Minolta Opto, Inc. Driver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096554A1 (en) * 2007-02-09 2008-08-14 Konica Minolta Opto, Inc. Driver
US7969063B2 (en) 2007-02-09 2011-06-28 Konica Minolta Opto, Inc. Driver

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