JPH0420300B2 - - Google Patents

Description

Claim 1: Generates an output signal having a bit period and a frequency of either a selected primary frequency or a secondary frequency that is 1/2 of the primary frequency, encodes an input signal, and encodes a serial digital signal. The frequency modulates the output signal while serially modulating multiple bursts of digital data bits at the primary frequency during each predetermined bit period to provide differential phase encoding of one input signal in the form of data bits. A communication system 10 characterized in that the system 10 receives a series of digital data bits and responsively provides a start control signal, the digital data bits being transmitted during the first half of any one of the bit periods. a control means 12 for providing a stop control signal in response to a non-reception and for providing a plurality of data control signals (CR, CD) during each received period; and coupled to the control means 12; The second half of the output signal that occurred just before in response to the start control signal
generate a 1/2 cycle output signal with the same frequency as the data control signal (CR,
1/2 cycle of the output signal at the primary frequency and in phase with the preceding 1/2 cycle of the output signal in response to one of the data control signals (CR or CD); generates 1/2 cycle of said output signal at a secondary frequency with no change in phase with the preceding 1/2 cycle of the output signal in response to only the data control signals of frequency generator means 18 for generating a stop control signal for generating a 1/2 cycle output signal at a primary frequency with no change in phase with the preceding 1/2 cycle of the output signal in response to not receiving digital data; 20, 22, 2
4, 26, 28, 30, 32, 34, 36, 3
8, 40, and 42. A communication system 10 having digital differential phase modulation.

2. The frequency generation means further includes first and second terminals, and the control means 1.
2; a first switching means having a first terminal coupled to a second terminal of said first switching means 18; and a first impedance having a second terminal; a first terminal of a first polarity coupled to a first terminal of said first switching means 18 and a second terminal of a second polarity connected to a reference voltage; a supply means 26; a second switching means 20 having a first terminal coupled to a first terminal of the first supply means 26, a control terminal coupled to the control means 12, and a second terminal; , a first terminal coupled to a second terminal of said second switching means 20 and a second terminal coupled to a second terminal of said first impedance means 28.
a second impedance means 30 having terminals of
a third switching means 22 having first and second terminals coupled to the control means 12 and a control terminal; a first switching means 22 coupled to the second terminal of the third switching means 22; a third impedance means 34 having a terminal and a second terminal; a first terminal of a first polarity type coupled to a first terminal of said third switching means 22; and a first terminal of a first polarity type coupled to a reference voltage. a second supply means 32 having a second terminal of a second polarity type; a first terminal coupled to the first terminal of said second supply means 32; and a first terminal coupled to the control means 12; a first terminal coupled to the second terminal of the fourth switching means 24; and a first terminal coupled to the second terminal of the fourth switching means 24, and a third impedance. a fourth impedance means 36 having a second terminal coupled to a second terminal of the means 34; and a fourth impedance means 36 coupled to the second terminals of the first, second, third and fourth impedance means. one integrator 38,
40, 42. A communication system having digital differential phase modulation according to claim 1, characterized in that the communication system includes: 40, 42.

TECHNICAL FIELD The present invention relates generally to digital communication systems, and more specifically to conventional digital differential phase shift systems.
The present invention relates to a communication system with digital differential phase modulation using digital frequency shift keying (DPSK) or digital frequency shift keying (FSK) modulation.

BACKGROUND OF THE INVENTION Telephone data transmission typically uses conventional digital differential phase (DPSK) for two-wire cable pairs.
or in a continuous mode system using digital frequency (FSK) modulation. Other techniques for achieving full duplex bidirectional transmission that have advantages over continuous mode systems are also known. The disadvantage of continuous mode systems in full-duplex bidirectional transmission arises from the separation of both data streams. Typically frequency separation or algebraic cancellation
cancellation) is used to separate data. However, frequency separation can be cumbersome to implement and is both bandwidth and distance limited. Algebraic cancellation is not accurate for all applications and can cause significant echo problems from various harmonics and transmission line reflections. Therefore, a promising alternative to continuous mode operation is time compressed multiplexing (TCM) systems, also known as burst mode or ping pong systems. Burst mode systems separate the two directions of transmission by separating them in time, so that at any point in time there is only one transmission.
become the direction. A disadvantage resulting from using a burst mode system is that the transmission frequency is considerably higher. This is because the data must be burst at a frequency that is at least twice the frequency of the data entering the system to ensure sufficient time separation. Using DPSK or FSK modulation in burst mode systems results in a very wide spectral content.
Yet another drawback arises with FSK modulation, as DC balance is not always maintained for each burst of data, and extra bits are required to maintain DC balance. . If digital burst mode transmissions are not DC balanced bit by bit, inter-symbol interference may result and destroy the meaning of the transmitted data. With phase modulation, DC balance is necessarily maintained, but harmonic energy will be released into other communication channels.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a communication system with digital differential phase modulation.

Another object of the invention is to provide a communication system with digital differential phase modulation that allows operation in burst mode operation with low spectral content.

Yet another object of the present invention is to provide a communication system with digital differential phase modulation using hybrid DPSK modulation for burst mode operation.

Yet another object of the present invention is to provide an improved communication system using a hybrid DPSK modulated signal that is DC balanced and has significantly reduced harmonic energy in a burst mode system.

To achieve the above and other objects and advantages of the present invention, control means are provided in one form for receiving sequential digital data having a first frequency. The control means provides a first control signal in response to each received digital data having a first predetermined value, or provides a second control signal in response to each received digital data having a second predetermined value. Another form of the invention uses only one control signal having a first or second value depending on the value of the digital data. There are frequency generator means coupled to the control means and parallel to each other. The first frequency generator provides one complete cycle of the output signal at the first frequency each time the first control signal is received. The second frequency generator generates 1/2 cycle of the output signal at a second frequency that is 1/2 of the first frequency and in phase with the previous 1/2 cycle of the output signal each time the second control signal is received. give. The communication system may operate in continuous mode operation, but may also use burst mode operation. In burst mode operation, the control means provides a starting control signal at the beginning of a new burst giving a half cycle of the output signal of the first frequency and being phase coded with respect to the last data bit of the previous burst. . The control signal also provides a stop signal at the end of the burst, providing a 1/2 cycle of the output signal at the first frequency and of opposite polarity to that of the previous 1/2 cycle.

The above and other objects, features and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings.

[Brief explanation of drawings]

FIG. 1 graphically depicts an example of a DPSK modulated signal well known in the prior art.

FIG. 2 graphically depicts an example of an FSK modulated signal well known in the prior art.

FIG. 3 is a block diagram of a communication system illustrating a preferred embodiment of the present invention.

FIG. 4 is a schematic block diagram of a communication system constructed in accordance with a preferred embodiment of the present invention.

FIG. 5 is a graphical representation of signals associated with the communication system of FIG.

FIG. 6 shows the triangular approximation of the output signal shown in FIG. 5 in a graphical form.

FIG. 7 is a schematic diagram of one example of a controller that produces the triangular approximation shown in FIG. 6 and may be used with the communication systems of FIGS. 3 and 4.

FIG. 8 shows in graphical form signals associated with the controller shown in FIG.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of conventional digital differential phase keying (DPSK) used for high speed digital data transmission over standard two-wire telephone lines. The example shown is of a digital byte represented as "1101". The frequency of the DPSK signal is the frequency of the carrier frequency of the transmitted data. For illustrative purposes only, a logic "1" is
Assume that it is represented by a phase unchanged from the previous cycle. Therefore, a logic "0" is represented by a phase change from the previous cycle, such as a 180° phase shift. The typical data transmission frequency for an input carrier signal operating in a burst mode system is
It is 256KHz. Unfortunately, the 180° phase in conventional DPSK generates a large amount of second harmonic energy that is never used in the modulation process. Furthermore, the second harmonic energy is radiated into other communication channels causing interference. To eliminate this problem, the second harmonic must be filtered before transmission. Since the phase information is carried at harmonic numbers, the information is rapidly attenuated by the inherent attenuation properties of the transmission means and is more susceptible to destruction by noise.

FIG. 2 shows an example of conventional digital frequency modulation (FSK) used for high speed digital data transmission over standard two-wire telephone lines.
The illustrated example is for the same digital byte of "1101". For purposes of illustration only, it is assumed that a logic "1" indicates a first predetermined frequency. Therefore, a logical 0 indicates a second predetermined frequency. A disadvantage of FSK modulation is that DC balance may be lost. Due to the nature of twisted pair wires, the wires must be DC balanced to prevent bias distortion and inter-symbol interference.
Unfortunately, a DC bias exists after a byte transmission, such as the byte transmission shown in FIG. For cycles 1, 2 and 4 there is only a DC signal and the sum is not balanced. Cycle 3 is DC
Balancing is performed, but the overall signal on a bit-by-bit basis is
There is no DC equilibrium. To avoid having a large DC bias on the transmission line, a DC balancing bit must be inserted during the byte burst to balance the DC bias for the entire burst. The disadvantages of using balanced bits are:
The time required to transmit the balanced bits is lost,
As a result, distance is limited.

Illustrated in FIG. 3 is a block diagram of a communications system 10 that includes a controller 12 for providing first and second control signals to a primary frequency generator 14 and a secondary frequency generator 16, respectively. Communication system 10 is a transmission system that can operate in continuous mode or burst mode operation.
Communication system 10 employs an improved hybrid digital differential phase shift modulation that has substantial advantages over conventional DPSK and FSK modulation.

Illustrated in FIG. 4 is a communications system 10 constructed in accordance with a preferred embodiment of the present invention.
The control device 12 of the communication system 10 is the transmission gate 1
8, 20, 22 and 24 control inputs. In a preferred form, transmission gate 1
8, 20, 22 and 24 are control signals C _R1 , which respectively control the speed and polarity direction of the output signal.
It is a conventional MOS transmission gate clocked in a conventional manner by C _R2 , C _D1 and C _D2 . An embodiment of the control device 12 is shown in more detail in FIG. Although in the preferred form controller 12 is shown as providing two control signals,
The invention may also be practiced with a controller that provides only one signal to control the rate of the output signal. If one control signal is used, no phase change will occur when a speed change occurs. Each of transmission gates 18 and 20 are connected together and connected to voltage source 2
It has an input coupled to a negative potential terminal of 6.
The positive potential terminal of voltage source 26 is coupled to a reference voltage, such as ground. The output of transmission gate 18 is resistor 2
The output of the transmission gate 20 is connected to the first terminal of the resistor 30. Transmission gates 22 and 24 each have an input connected together and coupled to the negative potential terminal of voltage source 32. The positive voltage terminal of voltage source 32 is coupled to a reference or ground voltage. The output of transmission gate 22 is connected to a first terminal of resistor 34, and the output of transmission gate 24 is connected to a first terminal of resistor 36. Each of resistors 28, 30, 34 and 36 has a second terminal connected together and coupled to the inverting input of operational amplifier 38. The non-inverting input of operational amplifier 38 is coupled to a reference or ground voltage. A feedback capacitor 40 is connected to a first plate coupled to an inverting input of operational amplifier 38 and to an inverting input of operational amplifier 38.
a second plate coupled to the output of the second plate. Input and feedback capacitor 40 coupled to a first plate of feedback capacitor 40
A transmission gate 42 is coupled in parallel with feedback capacitor 40, having an output coupled both to the second plate of the amplifier 38 and to the output of operational amplifier 38. A clear integrator control signal, shown in FIG. 8, is coupled to transmission gate 42, which zeros out the charge on feedback capacitor 40 between bursts of data. Transmission gate 42 is not required for continuous mode operation.

In operation, the signals shown in FIG.
It is clear how to give a DPSK modulated signal.
For illustration purposes, assume that data transmission is in progress. Both input data and output signals have distinct bit periods. The control signals C _R1 , C _R2 , C _D1 and C _D2 occur during a control period corresponding to each of said bit periods but preceding that bit period by at least one half of a bit period. . In the preferred embodiment, control signals C _R1 and C _R2 occur on 1/2 cycle boundaries of the bit period, and C _D1 and C _D2 occur on 1/4, 1/2 and 3/4 cycle boundaries to form a triangular approximation. to occur. If only one control signal is used, as described above, that one control signal controls the speed of the output signal, and the phase or direction of the output signal is automatically fixed by the controller 12. , never changes at the 1/2 cycle boundary. At the starting point of observation, a digital "0" is being received at the input of the control device 12. Assume that the controller 12 is programmed such that when a "0" is received during the control period, the output signal is frequency shifted to 1/2 the frequency of the input carrier at the 1/2 cycle boundary of the output signal. do. “1” is the control device 12
remains at the input carrier frequency, the output signal is not frequency shifted at the 1/2 cycle boundary of the preceding bit period. Therefore, the improved hybrid DPSK modulation is actually a frequency modulation of a phase encoded signal. In order to provide control signals C _R1 , C _R2 , C _D1 and C _D2 giving information as to whether to change or not change the frequency, the sequential digital data is processed by the controller 12 at least earlier than 1/2 of the bit period. must be received. In the illustrated embodiment, during the bit period of the output signal labeled A', the illustrated output signal changed in frequency by one-half of the input carrier frequency. It should be noted that the "0" for bit period A' was received at least by the middle of the preceding bit period. By at least the middle of bit period A', an input "1" for bit period B' is received. bit period
By the middle of A', the controller 12 has
The control signal C _R1 required to frequency shift the output signal for B′ back to the frequency of the input carrier,
Generate C _R2 , C _D1 and C _D2 . bit period
By the middle of B', no input signal has been received and
The controller 12 is configured such that a single 1/2 cycle at a carrier frequency of 256 KHz of opposite polarity to the first 1/2 cycle of bit period B'
A stop signal is generated, indicated by a single star in FIG. 5, to indicate that it should occur during the cycle. This is the end of the burst of signal energy and there is no data on the line for a finite amount of time. Between bursts, transmission gate 42 is closed by a clear integrator control signal;
All charge on capacitor 40 becomes zero and the voltage at the output of operational amplifier 38 is held at the reference or ground voltage.

When another burst of signal energy is received, controller 12 generates a start signal, indicated by two stars in FIG. 5, which remains active only during the first half of bit period C'. Generate an output signal. The first half cycle of the output signal for a new burst has the same frequency as the second half bit period of the previous burst, which is the primary frequency. The controller 12 provides, for the first 1/2 cycle, a 1/2 cycle of the output signal where the first "0" is out of phase with the last cycle of the preceding burst, and the first "1" 1/2 of the output signal in phase with the last cycle of the preceding burst
programmed to give cycles.
Since a ``0'' is received first, the first half of bit period C' is opposite in phase to the output signal of the last bit period, which was B'. By the middle of bit period C', the input bit for the next bit D' must be received and in response the control signals C <sub>R1</sub> ,
C <sub>R2</sub> , C <sub>D1</sub> and C <sub>D2</sub> must occur.
A ``1'' is received for bit period D', so the output signal does not shift in frequency at the 1/2 cycle boundary of bit period C'. By the middle of bit period D', the input bit for the next bit E' must be received and control signals _CR1 , _CR2 , _CD1 and _CD2 must be generated in response. “0” for bit period E′ is received;
Therefore, an output signal indicating a frequency change to 1/2 of the carrier frequency is generated during the second half of bit period D' and the first half of bit period E'. By the middle of bit period E', the input bit for the next bit period F' has been received and the control signal is activated in response.
C _R1 , C _R2 , C _D1 and C _D2 must occur. A ``0'' is received for bit period F', so that an output signal representing a frequency half that of the input carrier is received during the second half of bit period E' and during bit period E'.
It occurs during the first half of F′. Therefore, the frequency of the output signal remains the same from the 1/2 cycle boundary of bit period D' to the 1/2 cycle boundary of bit period F'. By the middle of bit period F', the input bits for the next bit period G' have been received, for which control signals _CR1 , _CR2 , _CD1 and _CD2 must be generated. “1” for bit period G′
is received, and thus an output signal exhibiting a frequency equal to the input carrier is generated from the 1/2 cycle boundary of bit period F' to the 1/2 cycle boundary of bit period G'. By the middle of the bit period G′, the bit period G′
Input bits for H' are received and control signals _CR1 , _CR2 , _CD1 and _CD2 must be generated in response. “1” for bit period H′
is received, and therefore an output signal is generated again which exhibits a frequency equal to the input carrier and has a bit period of 1/2 G′.
It is given from the cycle boundary to the 1/2 cycle boundary of the bit period H'. Until the middle of the bit period H',
No further bits for the input signal are received and controller 12 generates a stop signal, indicated by a single star, as described above for the end of the previous burst. The control signal indicated by one star is 1 during the second half of bit period H'.
Generates two 1/2 cycle signals. This one half cycle signal has the opposite polarity to the first half of the bit period H' of the output signal. The frequency of the last half cycle of bit period H' is the input carrier or primary frequency. This is the end of another burst and no further output signals are generated until another burst is received.

Shown in FIG. 6 is an output signal corresponding to the example shown in FIG. 5 and an approximation of the triangular waveform of the output signal. The transmission gates that need to be closed and opened to generate triangular waveforms of various slopes are specified in FIG.

FIG. 7 shows a communication system 1 including a control device 12.
0 in more detail, the system can be easily implemented by conventional logic and includes triangular ramp rates and transmission gates 18, 2.
0, 22, and 24 to provide the output signal shown in FIG.
Controller 12 includes a D-type flip-flop 44 whose D input is coupled to input sequential data and whose clock input is clock 1.
The S input is coupled to the Control 3 signal. The Q output of flip-flop 44 provides a ramp rate signal and is coupled to the first inputs of AND gates 46 and 48. A D-type flip-flop 50 has an S
input and a reset input coupled to the control two signals. Inverter 52 has an input coupled to the Q output of flip-flop 50 and an output coupled to the D input of flip-flop 50. The Q output of flip-flop 50 provides ramp direction control and is coupled to the second input of AND gate 46, the control input of transmission gate 20, and the input of inverter 54. The output of inverter 54 is coupled to both the second input of AND gate 48 and the control input of transmission gate 22. Clock generator 56 has an input and an output coupled to the input sequential data and provides a clock 2 signal to the clock input of flip-flop 50.

In this configuration, gates 18, 20, 22, and 24 are switched to function as a primary frequency generator and generate one complete cycle of the output signal at a primary frequency of 256 KHz. Selectively opening gates 18 and 24 in response to input data provides a secondary frequency that is one-half the primary frequency and in phase with the primary frequency. Operational amplifier 3
8 and integrating capacitor 40 function as an integrator and provide the triangular waveform of FIG. 6 by integrating the current summed to the non-inverting or negative input of operational amplifier 38. In the preferred form, resistors 28, 30, 3
4 and 36 are used, but the impedances can be freely substituted to achieve the same function.

In FIG. 8, signals related to the operation of the control device 12 are shown. The first burst of data is shown. A control 3 signal is generated at the beginning of the burst. Control 1 or control 2 signal is generated according to the following Boolean formula: Control 1 = [D _I・P+ _I・]・Control 3 Control 2 = [D _I・+ _I・P]・Control 3 However, D _I = Logic value that the first cycle of the burst is intended to represent (logic “1” or logic “0”) P = If the polarity of the second half of the last cycle of the previous burst is positive, P = 1, the previous burst A Boolean variable such as P=0 if the polarity of the second half of the last cycle of is positive.

Clock generator 56 generates a clock 2 signal that varies as shown in FIG. 8 in response to the logic state of the input data. The Clock 1 signal occurs every 1/2 cycle boundary. The ramp speed and ramp direction signals thus control transmission gates 18, 20, 22 and 24 to provide output signals.

The hybrid DPSK modulated output signal is
DPSK modulation has a lower amount of second harmonic energy than the corresponding output signal generated. modulation
Because the DPSK signal has phase information carried at a lower frequency, it provides a stronger receivable signal than the corresponding signal produced by conventional DPSK modulation. It should also be clear from the foregoing discussion that a modulated output signal of a selected primary frequency having a zero current component is provided for each bit. This output signal can be decoded by conventional DPSK modulation techniques, leaving the modulation process unchanged. This variation of conventional digital differential phase modulation can be used for high speed digital data transmission over standard telephone lines in continuous mode or burst mode operation. When continuous mode is present, controller 12 operates in the same manner as described above, except that the control signals indicated by one and two stars are not generated.

Although the present invention has been described using preferred embodiments,
It will be obvious to those skilled in the art that the invention may be varied in many ways and may take the form of many embodiments other than those specifically shown and described above. It is therefore intended that the appended claims cover all modifications of the invention that fall within its true spirit and scope.