JPH04200147A - Dtmf signal reception circuit - Google Patents

Abstract

PURPOSE:To reduce number of signal lines in comparison with a conventional circuit by using a shift register circuit so as to output a DTMF recognition signal and a decoded DTMF signal to a same signal line. CONSTITUTION:A detection circuit and code converter 24 detects a DTMF signal and gives an enable signal to a steering circuit 7 when the DTMF signal is detected so as to set the mode for signal interrupt enable and a binarized DTMF signal is decoded and it is converted into a 4-bit data being remote control information. Then a DTMF recognition signal is outputted to a signal line 100 from a steering circuit 26. While a decoded DTMF signal is outputted, a DTMF recognition signal is outputted and it is discriminated by a host microprocessor 12. Thus, the DTMF recognition signal and the decoded DTMF signal are outputted through one signal line 101.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a DTMF signal receiving circuit, particularly a decoded DTMF signal receiving circuit.
This invention relates to a circuit that outputs a signal to a microprocessor.

[Prior Art] Telephones with an answering machine function enable remote control of various devices by operating from an external telephone.
MF (Dual Tone Multiple Pr
This is done by transmitting and receiving (equiency) signals between the receiver and the host microprocessor.

As shown in FIG. 4, between the DTMF signal receiving section 10 and the host microprocessor 12, the DTMF recognition signal and the decoded DTMF signal are transferred to the DTM
The F signal receiving unit 10 outputs the signal to the host microprocessor 12, and the read L7 shift pulse is conversely output from the host microprocessor [2] to the DTMF signal receiving unit [O].

FIG. 5 shows the output waveform of the above-mentioned signal. For example, when the DTMF signal shown in FIG.
The DTMF recognition signal shown in is output. When the host microprocessor 12 receives the DTMF recognition signal, it outputs a shift pulse for reading serial data as shown in FIG. Then, the decoded DTMF signal (decoded data) shown in FIG. Predetermined control will be performed.

[Problems to be Solved by the Invention] However, in the conventional DTMF signal receiving circuit, as described above, the receiving section 10 and the host microprocessor 12
In order to receive the DTMF signal, three signal lines are used between the terminal and the interface, and this has the problem of wasting the number of terminals.

The present invention has been made in view of the above problems, and its purpose is to reduce the number of signal lines between the DTMF signal receiver and the microprocessor, thereby reducing the number of terminals.
An object of the present invention is to provide a TMF signal receiving device.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a DTMF signal receiving circuit that receives a DTMF signal, decodes the DTMF signal, and outputs the decoded DTMF signal to a microprocessor.
The present invention is characterized in that a shift register circuit is provided that outputs the recognition signal and the decoded DTMF signal to the same signal line.

[Operation] According to the above configuration, when the receiving circuit receives a DTMF signal, a high output, for example, is continuously sent to the microprocessor as a DTMF recognition signal indicating that. Then, a read shift pulse is sent from the microprocessor, the DTMF recognition signal is turned off, and a decoded DTMF signal is sent to the microprocessor on the same signal line in synchronization with the read shift pulse.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a DTMF signal receiving circuit, and as shown, an input filter 14 for amplifying and filtering a received signal (including a DTMF signal) is provided, and this input filter 14 is composed of an input buffer, a 60H2 removal filter, an AGC circuit, an anti-aliasing filter, a dial tone filter, etc. This input section filter 14
The next stage is a high group filter 1 which is a bandpass filter.
6 and a low group filter 18 are provided, and the DTMF signal is divided into a low frequency group signal and a high frequency group signal. Zero-cross comparators 20.22 are connected to both filters 16.18, respectively.
The DTMF signal is converted into a binary signal.

A conventionally well-known detection circuit and code converter 24 is connected to the next stage of the comparator 20.22, and detects whether a DTMF signal is received or not. The two received DTMF signals obtained by the filter 16 and the low group filter 18 are decoded and converted into 4-bit decoded data. A steering circuit 26 and a shift register circuit 28 are connected to this detection circuit and code converter 24, and when the detection circuit and code converter 24 are enabled and detect a TMF signal, they output an enable signal to the steering circuit 26. Therefore, this steering circuit 26 is controlled by the DTM by the enable signal.
The F recognition signal is output to the shift register circuit 28 (signal line 100).

FIG. 2 shows the internal configuration of the shift register circuit 28, and this circuit has a 4-bit shift register 30.
, AND circuits 31, 32, OR circuit 33, inverter 3
4, an output terminal 18a and an input terminal 28b.
Only one terminal is provided. That is, the input terminal 28b
is a shift pulse input terminal (ACK terminal) for reading serial data as in the conventional case, but the output terminal 28a is a DT
This terminal is shared by the MF recognition signal output terminal (EST terminal) and the decoded DTMF signal output terminal (SD terminal).

The embodiment has the above configuration, and its operation will be explained below based on FIG. 3.

The received signal including the DTMF signal shown in FIG. 3(a) is input to the input section filter 14, further divided into low frequency band and high frequency band signals by the high group filter 16 and the low group filter 18, and further divided into signals in the low frequency band and high frequency band by the comparator 20. After being binarized at .22, it is output to the detection circuit and code converter 24. This detection circuit and code converter 24 detects the DTMF signal, and when the DTMF signal is detected, it supplies the steering link circuit 7 with a Hay Enable signal to make the signal interrupt possible. The digitized DTMF signal is decoded and converted into 4-bit data that becomes remote control information.

Next, the DTMF recognition signal is outputted from the steering circuit 26 to the signal line 100, or this DTMF recognition signal is inputted to the AND circuit 31 in FIG. 2 as a high level signal, for example. In this state, since the select signal 200 is not output, the inverter 34 also outputs the old gh level signal to the other terminal of the AND circuit 3], and therefore, the signal of the old GH level is output from the AND circuit 31 to the OR circuit 33. An h level signal is input. As a result, the OR circuit 33 outputs the DTMF recognition signal shown at A in FIG. 3(C) from the output terminal 28a (
signal line 101).

Conventionally, as shown in FIG. 5 above, the DTMF recognition signal was output for the period when the enable signal was active, or in the present invention, the DTMF recognition signal was output until the decoded DTMF signal was output. to output,
This can be determined by the host microprocessor 12.

Then, the host microprocessor 12 that has received the DTMF recognition signal supplies the shift pulse for reading serial data shown in FIG. 3(b) to the shift register circuit 28 (signal line 102), which causes the shift The register circuit 28 transfers the decoded DTMF signal B shown in FIG. 3(C) from the 4-bit shift register 30 to the AND circuit 3 in synchronization with the read shift pulse.
Output to 2. On the other hand, the select signal 200 shown in FIG. 3(d) is output from the readout shift pulse of FIG. 3(b) to the AND circuit 32, and in this case, the output of the other AND circuit 31 is Low. Because the level
A DTMF signal decoded by the read shift pulse is output via the AND circuit 32 and the OR circuit 33 (signal line 101).

As described above, the DTMF recognition signal and the decoded DTMF signal are output from the − signal lines 101, and are sent to the shift register circuit 28 and the host microprocessor 12.
Only two signal lines are required between the terminals and the number of terminals is two.

[Effects of the Invention] As explained above, according to the present invention, the DTMF recognition signal and the decoded DTMF signal are outputted to the same signal line by the shift register circuit. The number of lines can be reduced, and the number of input/output terminals between the receiving circuit and the microprocessor can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a DTMF signal receiving circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing the internal structure of a shift register circuit of the embodiment, and Fig. 3 shows the operation of the embodiment. FIG. 4 is an explanatory diagram showing the state of signal transmission and reception between a conventional receiving circuit and a host microprocessor, and FIG. 5 is a signal waveform diagram showing the operation of the conventional device. 10... DTMF signal receiving section 12... Host microprocessor 24...
Detection circuit and code converter 26 ... Steering circuit 28 ... Shift register circuits 31, 32 ... Ant circuit 33 ... OR circuit

Claims (1)

[Claims] In a DTMF signal receiving circuit that receives a DTMF signal, decodes the DTMF signal, and outputs the decoded DTMF signal to a microprocessor, the DTMF recognition signal and the decoded DTMF signal are output to the same signal line. Characteristic DTMF signal receiving circuit.