JPH04199726A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To allow operation diagnosis without damaging an electrode pad by a method wherein it is made possible that the diagnosis starting instruction is given from outside and the diagnosis results is fed to outside, with non- contacting state by means of an interface section contained in a diagnosis circuit. CONSTITUTION:A plurality of a circuit to be diagnosed 3A and a circuit for diagnosis 3B that allows this operational diagnosis of the circuit to be diagnosed 3A are formed on the same wafer. A circuit for diagnosis 3B is formed, including a memory section 5 storing the information for diagnosis, a logic circuit section that makes evaluation of acceptance or rejection by comparing the output result from the circuit to be diagnosed 3A with its expected value when the information for diagnosis is given to the circuit to be diagnosed 3A, and an interface section 90 that allows the taking in of the diagnosis start instruction signal from outside and the output of the diagnosis results to outside with non-contacting state with respect to the wafer 1, thereby making it possible to perform operational diagnosis without damaging an electrode pad such as bonding pad.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit in the form of a wafer or a chip that includes a circuit to be diagnosed and a diagnostic circuit that makes it possible to diagnose the operation of the circuit, and furthermore, This invention relates to a technology that enables non-contact diagnosis equivalent to a wafer probing test of a circuit to be diagnosed.

[Conventional technology]

Operational diagnosis of semiconductor integrated circuits involves manually applying diagnostic information such as test patterns or signals to the semiconductor integrated circuit to be diagnosed, and comparing the output value from the semiconductor integrated circuit with the expected value to determine the function of the semiconductor integrated circuit. Wafer blobbing tests are used to judge the quality of wafers and measure input/output signals. This wafer blobbing test
This is a test in which the electrical characteristics are measured by mechanically contacting a probe to the bonding pad of a semiconductor integrated circuit in the wafer state before chip cutting. is required. With this wafer prober, it is possible to input and output signals from the test equipment and supply power through the probe button that is in contact with the bonding pad, and by sequentially moving the probe, multiple semiconductors on the wafer can be detected. Accumulation 1
Circuits can be tested one after another.

An example of a document describing a wafer blobbing test is rLSI Handbook J published by Ohm Rei on January 30, 1982.

Problems to be Solved by the Invention] According to the inventor's study of the above-mentioned prior art, the following problems were found.

In the above-mentioned wafer probing test, the probe comes into contact with the bonding pad, which may cause damage to the bonding pad. Also,
Only one semiconductor integrated circuit, which is currently in contact with the probe 1, can be tested at the same time, and the probe must be moved each time the test is completed. It takes a long time to complete testing of semiconductor integrated circuits.

An object of the present invention is to provide a technique that can complete the operation diagnosis of all semiconductor integrated circuits on one wafer in a short time without damaging the electrode butts.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when a plurality of circuits to be diagnosed and a plurality of diagnostic circuits that enable operation diagnosis of the circuit to be diagnosed are formed on the same wafer, a storage section that stores diagnostic information, and a memory section that stores diagnostic information, A logic circuit unit that makes it possible to judge whether the circuit to be diagnosed is good or bad by comparing the output result of the circuit to be diagnosed with its expected value when given to the circuit to be diagnosed, and the reception of a diagnosis start instruction signal from the outside. and an interface section that enables external output of diagnostic results to the wafer in a non-contact state, thereby forming a two-legged diagnostic circuit. In a more specific embodiment, the interface section may include a light receiving section that senses a diagnosis start instruction optically given from the outside and a light emitting section that optically outputs the diagnosis result. At this time, in order to eliminate the need for external power supply to the semiconductor integrated circuit during operation diagnosis, it is preferable to provide the wafer with a solar cell that serves as a power source for operation diagnosis. After the operation diagnosis, the above-mentioned diagnostic circuit is unnecessary except in special cases, so it can be formed so that it can be cut out as a separate chip from the circuit to be diagnosed. If you want to make the above interface part actively available even after
Alternatively, if the inclusion of the interface section does not cause any particular problem, one diagnostic circuit and the corresponding diagnostic circuit can be cut out from the wafer as one semiconductor chip.

[For production]

According to the above-mentioned means, the interface unit included in the bipedal diagnostic circuit is capable of receiving an external diagnosis start instruction and external recognition of the diagnosis result while in specific contact with the wafer containing the semiconductor integrated circuit. This enables operation diagnosis without damaging electrode pads such as bonding pads.

In addition, a plurality of the above-mentioned diagnostic circuits are formed corresponding to the circuits to be diagnosed, thereby making it possible to diagnose multiple circuits to be diagnosed simultaneously, which makes it possible to diagnose the operation of all semiconductor integrated circuits on one wafer. It acts to shorten the time required.

〔Example〕

FIG. 1 shows an LSI according to an embodiment of the present invention.

In the figure, 1 is a wafer, and this wafer 1 includes a circuit 3A to be diagnosed.

A plurality of diagnostic circuits 3B are formed to enable the operation diagnosis of the circuit 3A to be diagnosed. The circuit to be diagnosed 3A and the corresponding diagnostic circuit 3B are formed so as to be cut out as one semiconductor chip 2 by dicing, which will be described later, as shown in an enlarged view in FIG.

The circuit 3A to be diagnosed is, although not particularly limited, a logic section formed by a gate array method, and the circuit 3A for diagnosis is coupled to the circuit 3B for diagnosis by an aluminum wiring layer AI.

The diagnostic circuit 3B is configured as follows, although it is not particularly limited.

A solar cell 4 is used as a power source in the operation diagnosis of the diagnostic circuit 3A, and generates a predetermined potential by receiving light of wavelength α from the outside. The generated potential is LSI
It is possible to apply it to each part.

5 is a ROM (read-only memory) in which test pattern information and expected value information as diagnostic information are stored.
The test pattern information can be transmitted to the circuit to be diagnosed 3A, and the expected value information can be transmitted to the logic section 6. The logic unit 6 compares the output of the circuit to be diagnosed 3A with its expected value when the test pattern information is given to the circuit to be diagnosed 3A.
enables operation diagnosis. This logic unit 6 is coupled with an interface unit 90 that allows external input of diagnostic instruction signals and external output of diagnostic results to the wafer 1 in a non-contact state. This interface section 90
includes, but is not particularly limited to, a light receiving section 7 that is sensitive to light of wavelength β, and a light emitting section 8 that can generate light of wavelength γ. The light receiving section 7 includes a light receiving element such as a light receiving diode 70.
The light emitting section 7 has a light emitting element such as a light emitting diode 80 and a driving circuit thereof. The light receiving diode 70 and the light emitting diode 80 can be manufactured using the same process as LSI manufacturing. The wavelength in that case is determined by the material of the diode. For example, in the case of Ga1-xAlxAs system, A
By controlling the I mixing ratio, the wavelength can be set in the range of 750 to 905 nm. When the light receiving section 7 receives the light having the wavelength β, the logic section 6 starts diagnosing the operation of the circuit 3A to be diagnosed. If it is determined in this operation diagnosis that the operation of the circuit to be diagnosed 3A is normal, the light emitting section 8 is driven by the logic section 6, thereby causing the light emitting section 8 to emit light of wavelength γ.

FIG. 2 shows the operation diagnosis in this embodiment.

In the figure, 9 is an 8-1 light source that generates light 10 of wavelength α, 11 is a second light source that generates light of wavelength β, 1
4 is a camera sensitive to light 13 of wavelength γ, 2o
is a dicing device that cuts the wafer 1 described above. Above 1st. The second light sources 9 and 10 are placed at positions where they can illuminate the wafer 1, and the camera 14 is placed at a position where the wafer 1 can be photographed. Information photographed by this camera 14 is taken into the dicing device 20 at the subsequent stage. The dicing apparatus 20 includes a coordinate calculation unit 21 that calculates the positional coordinates of the light emitting diode 80 emitting light of wavelength γ on the wafer 1 based on the photographic information of the camera 14, and In addition to dividing the chips into individual chips, the coordinate calculation section 21
The chip cutting section 22 extracts only the semiconductor integrated circuit including the light-emitting diode 80 that is lit based on the calculation result.

In this embodiment, the operation diagnosis and chip extraction of the circuit to be diagnosed 3A are performed as follows.

FIG. 3 shows the flow of the above operation diagnosis.

When the first light source 9 is turned on, light 10 of wavelength α is
is irradiated onto the wafer 1 (step ST''-). The potential generated by irradiating the solar cell 4 with this light 10 is supplied to each part of the circuits 3A and 3B, thereby enabling each part to operate. Incidentally, the irradiation with the light 10 having the wavelength α is continued until the operation diagnosis of the plurality of circuits to be diagnosed 3A on the wafer 1 is completed.

Next, light 12 of wavelength β is emitted from the second light source 11 to the wafer 1.
is irradiated. The diagnostic circuit 3B is operated by the light received by the light receiving diode 80.
As a result, the operation diagnosis of the circuit to be diagnosed 3A is started (
Step 5T2).

In this operation diagnosis, patterns (for example, ABCD) are input from the pattern ROM 5 to the circuit to be diagnosed 3A in a predetermined order.

Then, the value output from the diagnostic target circuit 3A and its expected value (Z) are compared in the logic section 6 (step 5T3). In this comparison, if it is determined that the output of the diagnostic target circuit 3A matches the expected value (YES), this means that the diagnostic circuit 3A is operating normally, so the logic section at that time The light emitting diode 80 is driven based on the diagnosis result of step 6, and light of wavelength γ is thereby generated from the diode 80 (step ST 4 ). In addition, if it is determined in the comparison in the two-legged logic unit 6 that the output of the diagnostic circuit 3A does not match the expected value (IO), the light emitting element 8
0 is not driven, so the light 13 of wavelength γ is not generated (step 5T5).

The above-mentioned operation diagnosis is started almost simultaneously in all the diagnostic circuits 3B in the wafer 1- by irradiating the wafer 1- with the light 10 from the first light source 9. In other words, since the diagnostic circuit 3B is provided corresponding to all the circuits to be diagnosed 3A on the wafer 1, all the circuits to be diagnosed on the wafer 1 are irradiated with the light 10 from the first light source 9. 3Δ are started individually and almost simultaneously.

Then, when the second operation diagnosis is completed, the wafer is photographed by the camera 14, and the image information is input to the dicing apparatus 20. Thereby, in the dicing apparatus 20, the coordinate calculation section 21 calculates the position coordinates of the light-emitting diode 80 that is lit, and chips are cut out based on the obtained coordinate information. The fact that the light emitting diode 80 is lit means that the circuit 3B to be diagnosed including the diode 80 is a good product that operates normally. Therefore, only good products are taken out when the chips are cut out by the dicing device 20. .

According to this embodiment, there are the following effects.

(1) When the first light source 9 is turned on, the light 10 of wavelength α is irradiated onto the wafer 1, and the potential generated by the irradiation of the light 10 onto the solar cell 4 is applied to the circuit 3A.
, 3B, thereby enabling each part to operate. In this state, the wavelength β is emitted from the second light source 11.
The light 12 of
is operated, thereby starting the operation diagnosis of the circuit 3A to be diagnosed. The result of this operation diagnosis is light emitting diode 80
This makes it possible to output the diagnostic results to the outside, thereby making it possible to understand the diagnostic results. By making it possible to exchange information optically in this way, it is possible to diagnose the operation of the circuit 3A to be diagnosed in a non-contact state with respect to the wafer 1. There is no risk of damage to the probe by the probe, and no undesirable stress is applied to the tool 1.

(2) In addition, the diagnostic circuit 3B and the interface section 9 correspond to all the diagnostic target circuits 3A on the wafer 1.
0 is provided, and the operation diagnosis of all the circuits 3A to be diagnosed on the wafer 1 is started individually and almost simultaneously by the irradiation of the light 12 from the second light source. Operation diagnosis of all the circuits to be diagnosed 3A in [1-C] can be performed in a short time.

(3) After the operation diagnosis is completed, the wafer 1 is photographed by the camera 14, and the image information is input to the dicing device 20. In the dicing device 20, the position coordinates of the light-emitting diode 8o that are lit are determined and obtained. Since a chip containing the light emitting diode 80, that is, a chip that is considered to be a good chip, is cut out based on the coordinate information, it is possible to automate the process from diagnosing the operation of one circuit to cutting out a good chip.

(4) Since one diagnostic circuit 3A and the corresponding diagnostic circuit 3B are cut out as one semiconductor chip, the operation of the circuit to be diagnosed 3A can be diagnosed again by using the diagnostic circuit 3B after cutting out the chip. It is also possible to do so.

(5) By providing solar cells 4 on the wafer.

Since probe contact for supplying power during diagnosis is also unnecessary, the effect of (1) above is more pronounced.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the diagnostic target circuit 3A and the diagnostic circuit 3
However, if the diagnostic circuit 3B is deemed unnecessary after the operation diagnosis, the chip size of the diagnostic circuit 3A can be reduced by cutting them out as separate chips. You may try to do so.

Further, in the embodiment described above, the interface unit 90 is configured so that the operation diagnosis results can be optically recognized externally, but it is also possible to use an electron beam test technique that uses an electron beam (EB) as a probe.

According to this technology, it is possible to directly measure the wiring potential in a circuit using the potential contrast observed with a scanning electron microscope, and if this is used, the light emitting part 8 in Figure 1 can be omitted. can do.

Furthermore, if an ultrasonic transducer capable of generating ultrasonic waves is provided in place of the light emitting unit 8, the quality of the circuit to be diagnosed 3A can be recognized based on the presence or absence of ultrasonic output from the transducer. Even if we use the above electron beams and ultrasound,
It is possible to diagnose the operation of the circuit to be diagnosed in a non-contact state with respect to the chip, and the same effects as in the above embodiment can be obtained.

Furthermore, in order to reduce the size of the chip, the solar cell 4 may be placed on the circuit to be diagnosed 3A or the diagnostic circuit 3B, or the solar cell 4 may be placed on the edge of the chip or other portions that do not contribute to circuit formation. A battery may be formed and used as a common power source for each circuit in the chip.

In the above explanation, the invention made by the present inventor was mainly applied to the logic LSI that is the background thereof, but the present invention is not limited thereto.
It can be applied to various LSIs such as one-chip microcomputers including semiconductor memories and the like. The present invention can be applied to conditions where at least a plurality of circuits to be diagnosed and circuits for diagnosis thereof are formed on the same wafer.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the internal input part included in the diagnostic circuit enables external diagnosis start instructions and external recognition of diagnosis results to be made in a specific contact state with respect to the wafer containing the semiconductor integrated circuit. Operation diagnosis is possible without causing damage. In addition, a plurality of the above-mentioned diagnostic circuits are formed corresponding to the circuits to be diagnosed, thereby making it possible to diagnose the multiple circuits to be diagnosed simultaneously. Therefore, the time required to diagnose the operation of all semiconductor integrated circuits on one wafer is can be significantly shortened.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of a wafer on which an LSI according to an embodiment of the present invention is formed and its main parts, Fig. 2 is an explanatory diagram of the operation diagnosis of the LSI shown in Fig. 1, and Fig. 3 is the above-mentioned diagram. It is a flowchart of operation diagnosis. 1... Wafer, 2... Chip, 3A... Diagnosis target circuit, 3B... Diagnostic circuit, 4 - Solar cell, 5... RO
M, 6. Logic section, 7.. Light receiving section, 8. Light emitting section, 70.
・・Light receiving diode, 80・Light emitting diode, 90・Interface section.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit in which a plurality of circuits to be diagnosed and a plurality of diagnostic circuits capable of diagnosing the operation of the circuit to be diagnosed are formed on the same wafer, the diagnostic circuit is It is possible to determine whether the circuit to be diagnosed is good or bad by comparing the storage unit that stores information with the output result of the circuit to be diagnosed and its expected value when this diagnostic information is given to the circuit to be diagnosed. What is claimed is: 1. A semiconductor integrated circuit comprising: a logic circuit section that performs a diagnostic start instruction signal from the outside; and an interface section that allows receiving a diagnosis start instruction signal from the outside and outputting a diagnosis result to the wafer in a non-contact state. 2. The semiconductor integrated circuit according to claim 1, wherein the interface section includes a light receiving section that senses a diagnosis start instruction optically given from the outside, and a light emitting section that optically outputs the diagnosis result. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the wafer is provided with a solar cell serving as a power source for operation diagnosis. 4. The semiconductor integrated circuit according to claim 1, 2 or 3, wherein the diagnostic circuit and the corresponding diagnostic target circuit are formed so as to be cut out as separate chips from each other. 5. A semiconductor integrated circuit comprising one diagnostic circuit and a corresponding diagnostic circuit cut out as one semiconductor chip from the semiconductor integrated circuit according to claim 1, 2, or 3.