JPH0419790A - Information device with display device composing screen - Google Patents

Abstract

PURPOSE:To display external video data on a screen only by a necessary amount at need by constituting a multi-window screen where the external video data is displayed in a specified window on the screen, and compressing or enlarging the external video data according to the size of the window and displaying the compressed or enlarged data. CONSTITUTION:This device is equipped with a means which sets an area to be displayed on the screen of a display equipment 10 on a 1st video RAM 3, a means which sets an area to be displayed on the screen of the display equipment 10 on a 2nd video RAM 5, and a means which specifies the window on the screen on the display equipment 10. Further, this device is equipped with a function which outputs the display data on the 2nd video RAM 5 from a display dot selecting circuit 8 and displays the display data in the specified display area on the 2nd video RAM 5 in the window on the screen when display scanning enters the range of the window on the screen of the display equipment 10. Namely, the external video data 18 is displayed in the specified window on the screen, and further compressed or enlarged according to the size of the window and then displayed. Consequently, the external video data can be displayed at need.

Description

[Detailed Description of the Invention] [Industrial field of application] Application to information equipment having a display function configured with a multi-screen.

[Prior Art] FIG. 12 shows the configuration of screen composition in a conventional information device. First video RAM 3 and second video R 18M 1
23, connect the data bus 12 of the arithmetic device 1 to the first video RA rVI control circuit 2, and go to the first video R0. access.

Analog video signal 18 from the outside is converted to A/D converter 1
21 and generates a digital video signal 124. The digital video signal 124 and the first video RAM 3
The display data from the second video RA is input to the second video RAM 123;
Set the area to write the display data 15 of A/C,
Write to the second video RAS1 through the write data bus 125. The second video RAM 123 is simply scanned to extract display data 12G, which is then input to the D/A converter 9 to generate a CRTM image signal 23 and display it on the CRT10.

[Problems to be solved by the invention] In conventional display bodies, at least one display data is A/
After D conversion, there is no function to enlarge the display data via a latch circuit or to compress the display by thinning out the display data addresses, so the display data input from the outside can be enlarged to the display core the size of Kyogen. , could only be compressed.

Therefore, the purpose of the present invention is, first, to display external video data in a specified window on the screen, and to compress or compress the external video data depending on the size of the core.
Second, it has a function to carefully set the display area for external video data, and extracts the necessary parts of the external video data. The video data can be displayed on the screen and combined with the display data of the first video RAM on the screen.

[Means for Solving the Problems] The present invention provides a first video RAM for storing display data.
a second video RAM; an arithmetic device capable of reading and writing N1 display data into the first and second video R4; inputting the display data of the first video RAM to a palette circuit; A few bits of color information for each of R, G, and B are extracted from the display and display dots are selected.The second video R A\1 here is a circuit for A/D converting and inputting an external analog video signal, and a circuit for inputting the analog video signal from the outside by A/D conversion. ．． a mechanism for inputting the take of the first video RA:\1 into the display select circuit; a mechanism for displaying the output take of the display select I circuit on a display device; and a screen of the display device in the first video RA:\I. Up;
means for setting an area for displaying the second video R;
．． means for setting an area to be displayed on the screen of the display device at the angle of T), means for specifying a window on the screen of the display device, and means for scanning the display within the range of the window on the screen of the display device. When I entered,
It has a function of displaying the display data of the second video R Ai'vl in eight display dots, and displaying the display data of the specified display area of the second video R Ahl in a window on the screen. The present invention is further characterized in that, when the number of display data in the window of the screen of the display device is smaller than the number of display data in the designated display area of the second video RAM,
In the process of extracting display data from the specified display areas of the second videos RA to I, the addresses of the display data are thinned out and extracted, and the display data of the display area of the second video RAM M is The present invention is further characterized in that the number of display data at the center of the screen of the display device is equal to or less than the specified number of data of the second video RA. If the number of display data is larger than the number of display data in the display area, the display data is retrieved from the display area of the second video RAM, the cycle is slowed down, the same display data is displayed in several dots on the screen, and the display data is displayed in the window. The present invention is characterized by having a function of enlarging and displaying the specified display area of the second video RAM in an overlapping manner.

[Embodiment] FIG. 1 is a simple block diagram of an embodiment of the present invention. It has a first video RAM 3 and a second video RAM 5, and the arithmetic device 1 accesses the first video RAM through the first video RAM control circuit 2. The address bus 11 and data bus 12 of the arithmetic unit 1 are connected to the first video RA.
1 control circuit 2, converted into a first video RAM ats 13 and first video RAM parallel data 14, and connected to a first video RAM 3. First video R
The display data of A\13 is inputted from 88\■ to the first video as serial data 15 and input to the palette circuit 4. Serial data] Select the palette register built in the circuit and obtain 8-bit data 20 each for R, G, and B as color data.

The color data 20 of 8 bits each of R, G, and B is input to the display dot data selection circuit 8.

On the other hand, analog video signal 18 from external television camera 7
is input to the second video RAM control circuit 6, A/D converted by the A/D converter in the second video RAM control circuit 6, and the video information from the external television camera 7 is stored in the second video RAM 5. . The address bus 11 and data bus 12 of the arithmetic device 1 are connected to the second video RAM control circuit 6, and the arithmetic device 1 and the second video R are accessed through the second video RAM control circuit ya6. Between the second video RAM control I/roll circuit 6 and the second video RAM, a second video R
AM address bus 16 and M data bus 1 to Kaji Video R
The display data 2 of the second video RAM 5 is transferred to the second video R through the N1 data bus 17.
Input the display data latch circuit 25 here. The latch signal 27 of the second video R4)1 display data is output from the second video RAM control circuit 6. The data 26 latched by the latch circuit 25 is input to the display dot 7 circuit 8, and in the display dot 7 circuit 8, the data 20 and the data 26 are selected by the display dot set control signal 21, Data 22 is output as the selection result. data 2
2 is converted into an analog signal 23 by a D/A converter 9, and inputted to a CRT 10 for display.

FIG. 2 is a block diagram illustrating the first video RAM control circuit 2 shown in FIG. 1, which is an embodiment of the present invention. Address bus 11 and data bus 1 of arithmetic unit 1
2 to the first video RAM3 a!・Conversion to Shisuhas 13 and parallel data bus 14! It shows the I yield.

The address address 11 of the arithmetic unit 1 is input to the arithmetic unit address conversion circuit 201, and the RA S
Address and C88S address: This conversion circuit 1 is output as the video Rpe\1 address 204 for the arithmetic unit, and the address cut (9 times) 182031 is input.Display output output circuit 202 generates a display address 205 based on the display timing signal 19 and inputs it to the address switching circuit 203.The address switching circuit 203 switches between the video RAM address 204 for the arithmetic unit and the display address 205, and The data bus 12 of the arithmetic unit 1 is connected to a data conversion circuit 206 and an internal register 207, and the data conversion circuit 206 generates address 13 of the first video RAM 3. , the data 12 of the arithmetic unit 1, the data 208 of the internal register 207, and the read data 14 from the first video RAM, and is output to the parallel data bus 14 of the first video RA7S1.

FIG. 3 is a timing chart explaining the operation of the second country. The display address generation circuit generates a display address based on the horizontal synchronization signal 209 and the display timing signal of the first video RAM blank signal 210. First video RA
In this embodiment, a multi-baud 1-RAM is used in step 1, and the serial register (SAM) of the multi-baud RAM is
Display address 20 when performing a data transfer cycle to
5 as two points. The area B shows the timing when the display address 205 is required, and the area A shows the timing when the arithmetic device 1 can freely access it. In area A, address 1 of the arithmetic unit! is output to the address bus 13 of the first video RAM 3. 1st video RAM blank 1 word, 1st video RAM
Display data is output from the serial data bus 15 of h=I3. In the area, the access data with the arithmetic unit 1 is the data bus]. This shows that H is appearing.

FIG. 4 is a block diagram illustrating the pallet circuit 4 of FIG. 1, which is an embodiment of the present invention. Each block is R.
G. B Each palette and register group R
ED butt register group 40G. GREEN bullet register group 407. BLUE palette register group 40
8 1, and a butt register address generation circuit 402 that generates a pallet register address 412 for selecting a pallet register from the address bus 11 of the arithmetic unit 1 or the serial data 15. The data on the data bus 12 of the arithmetic unit 1 is transferred to the data distribution circuit 401 to the input data path 403 of each palette register.

404 and 405 to enable pallet register settings from the playback device 1. The R.
G. B Color data 409 of 8 bits each.

410, 411 or is output as color data 20.

FIG. 5 is a block diagram illustrating the second video RAM control circuit 6 shown in FIG. 1, which is an embodiment of the present invention. Analog video footage from outside No. 18. Δ． /
D-convert. A/D conversion circuit 501 is provided, and the A/D conversion circuit 501 is provided.
The data switching circuit 50 converts the output data 506 of the conversion circuit 501 and the data via the data bus 12 from the arithmetic unit @1.
4, is set by the data switching circuit 504, and is output to the data bus 17 of the second video RAM 5. The data in the second video RAM 5 is output to the data bus 12 of the arithmetic unit 1 through the second video RAM control circuit 6. Arithmetic device 1 is the second video R1
An address 508 for accessing 15 is generated in the arithmetic unit address generation circuit 503, and a display address generation circuit F502 generates a display address for retrieving display data.

The address switching circuit 505 switches between the real brother address 507 and the Hama 1E device address 508 to generate address 16 of the second video RAb.15.

The display address generation circuit 502 generates a display dot data switching control signal 21 and a display data latch signal 27.

FIG. 6 is a block diagram roughly explaining the display address generation circuit explained in FIG. 5. Display address generation circuit 5 0 2! It has a register 602 for setting a display area in N13 to the second video R8 and a register 602 for setting a Z (area) for displaying the second video RAM on the display screen and the display timing signal 19. In addition to knowing the display scan position of the screen that changes from time to time, when the display scan enters the window area, the start address of the display area is generated based on the value 604 of the display area setting register 601, and the display area is sequentially , a display address generation unit 603 that generates a display address 507 for the display area.
has.

Compare the capacity of the display head of the second video RAM and the window capacity of the screen, and if the window is smaller, query the display area and output (display address intermittently within the display area) and display on the screen. indicate. If the capacity of the window is larger than the second video RA display area, the cycle for extracting display data from the display area is slowed down, and the latch cycle of the display data latch signal 27 is slowed down to increase the number of screens. Display the same data on the dots. 1. Set the second video RAM. 1. Correlate the display area with the center of the screen.

Figure 7; Second video RA on the screen explained in Figure 6
FIG. 6 is a block diagram showing the relationship between Z for displaying M and a display area set on the second video RAM.

Display area 70 on the entire area 701 of the second video R08N1
2, and a window 704 is set on the entire screen 703. The display timing is determined by the horizontal synchronization signal 209, and the second video RAM blank signal 705 is used to determine the display timing.
Start displaying. Screen areas other than 8 are blank and the display data of the first video RAM is displayed. This switching is performed by a display dot data switching circuit 8 and controlled by a display dot data switching control signal 21.

FIG. 8 is a timing chart illustrating access to the second video RAM. Horizontal synchronization signal 209 and blank signal 705 for second video R0 are controlled from here,
Display data is output to the data bus 17 in area E,
In area F, the access data of the arithmetic device 1 or data obtained by A/D converting the external video signal 1B is output.

The timing chart of FIG. 9 shows a state in which the display area of the second video RAM of FIG. 8 is narrowed on the screen due to the window setting. To the second video R1, a core area is designated on the screen by a %l blank signal 705.

If the capacity of the core is smaller than the capacity of the display area of the second video RA 15, the data in the E area appearing on the data bus 17 is not continuously taken out from the display area of the second video F<A M 5, but is thinned out. The data will be based on the address written.

Figure 10 shows that the capacity of the core is the same as the second video RA.
3 is a timing chart showing an operation when the capacity of the display area is larger than the set capacity of the display area. The display data (area E) does not appear in short cycles as shown in Figures 8 and 9, and
K, L, M, N, O appear at long intervals and 2"L. Display data latch signal 27 Display data that appears at two intervals (,!, K, L)
, N1. N, 0) and outputs it as display data 26 after launch.

FIG. 11 is a block diagram showing the relationship between the first video R1 13, the second video R1 15, their display areas 111 and 112, and the screens 10 and 3113 according to an embodiment of the present invention. The display area 111 specified for the first video 18M3 corresponds to the display of most of the screen 10, and the display area 112 specified for the second video RArv15 is displayed here in the window 113 of the screen 10. .

Display area 11 depending on the capacity of display areas 112 and 2113
2 is compressed or expanded and displayed in the window 113.

[Effect of the invention No. 11] It is possible to configure a multi-screen that displays video data from the outside in a designated area on the screen, and also compresses or expands the video data from the outside depending on the size of the window. Second, it is possible to set the display area for displaying the video data from the outside in two or more windows. It has the following functions: 1. It is possible to extract and carefully display a necessary part of video data from the outside, and to combine it with the display data of the first video R0 to 1 and display it on the screen. Third, the second video R can be accessed from the computing device, and the computing device can convert and display the video imported from the outside.Fourth: The first video RA hl!, is completely independent from the second video RARI, so it can be accessed from the computing device at high speed even while video information is being fetched from the outside.

[Brief explanation of the drawing]

FIG. 1 is a simple block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a first video RAM control circuit 2 which is an embodiment of the present invention, and FIG. 3 shows the operation of FIG. 2 according to the present invention. 4 is a block diagram of the pallet circuit 4 shown in FIG. 1 according to the present invention; and FIG. 5 is a block diagram of the second video RA shown in FIG. 1 according to the present invention.
A block diagram of the M control circuit 6, FIG. 6 is a block diagram of the display address generation circuit 502 which explains the present invention in detail, and FIG. A block diagram showing the first system between the window displaying the 2nd video RAM and the display area set on the second video RAM 1, FIG. 8 is a timing chart explaining access to the second video RAM of the present invention, and FIG. 9 is a timing chart explaining access to the second video RAM of the present invention, 10r:! J is a timing chart showing the operation when the capacity of the window is larger than the capacity of the display area set on the second video RAM 5 of the present invention, and FIG.
FIG. 12 is a block diagram showing the relationship between the AM5, the display areas 111 and 112, the screen 10 of the display device, and the window 113. FIG. 12 is a block diagram showing a screen composition method in a conventional information device. 1. 2. 3. 4. Oo. 6. 7. 8. 9. 10゜] 1゜12゜13゜14゜Arithmetic unit first video R1λN1 Control I/Roll circuit first video R
48\I Palette circuit to second video R0 M second video RA T control circuit External TV camera display dot data switching circuit D/A converter RT Address bus of arithmetic unit 1, data bus of address arithmetic unit 1, Data 1st video RAM address bus, address 1st video RA b・i data bus, data 15, , 1st video RAM serial data bus, serial data 16, 18N1 to 7 to 2nd video Tres bus, address 17, second video RA/I data bus, data 1B, external analog video Lt signal 19, display timing signal 20, R, G, B each from the palette circuit. 8-bit color data 21013 display dot data switching control signal 22.1
1 Display dot data 23 output from the display dot switching circuit, . . . Video signal 24 after D/A conversion, . . Internal storage circuit 25, . . Latch circuit for display data from the second video RA'%1. 26, 27, 201 of the display data from the second video RAM after latching the display data from the second video RAM
゜202゜204゜205゜207゜210゜401゜402゜403゜404゜405゜406゜407゜408゜Latch signal, arithmetic unit address conversion circuit 2nd video RA ``S, 1 display address generation circuit , A) ζSwitching rotation yg , display address of video RA for arithmetic unit, second video R1behl, data conversion circuit internal register internal register data horizontal synchronization signal first video RAM flank No. 18 Data distribution circuit Bar Atto register Address generation circuit Palette register input data Hasper Atto register input data bus Bullet register input data bus RED Palette register group GREEN Palette register group BLUE Palette register group 409°411°412°501° 502゜504゜505゜506゜507゜508゜601゜602゜603゜604゜, RED 8-bit color data, GREEN 8-bit color data, BLL!E 8-bit color data, palette register address , to/D conversion circuit, display address generation circuit for second video RA'%I address generation circuit for arithmetic unit data switching circuit address switching circuit, output data for second video R
AM display address arithmetic unit address register for setting a display area in the second video RAM M5, register for setting a window (area) for displaying the second video RA Tvl on the display screen, second video RAM Display address generation unit, value of display area setting register 601 605°701°702°703°704°705°111°112°121°l 22°123°124°125°l 26°, register 602 specifying window value, the entire area of 1 to the second video RA, the display area on the second video R1 to I, the full screen of the display device, Z on the full screen 703, the second video RAM flank signal, the first video RA 1 display area, second video RA display area, window set on the display device screen, A/D converter, second video R control I/roll circuit, second video R1 1 , digital video signal, write data bus, second video R48M display data bus, display data Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki et al. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 10 Figure 11

Claims (3)

[Claims] (1) A first video RAM and a second video RAM that store display data; an arithmetic unit that can read and write the display data of the first and second video RAM; and a calculation device that can read and write the display data of the first video RAM. A mechanism for inputting color information into a palette circuit, extracting several bits of color information for each of R, G, and B from the palette circuit and inputting it to a display dot select circuit; and A/D converting an external analog video signal to the second video RAM. a circuit for converting and inputting data; a mechanism for inputting data from the second video RAM into the display dot select circuit; a mechanism for displaying output data from the display dot select circuit on a display device; means for setting an area to be displayed on the screen of the display device; means for setting an area to be displayed on the screen of the display device in the second video RAM; a means for specifying, and when the display scan enters the range of the window on the screen of the display device,
The display data of the second video RAM is output from the display dot select circuit, and the display data of the second video RAM is output to the window on the screen.
An information device having a display device that performs screen composition, characterized in that: a function of displaying display data in the designated display area; (2) If the number of display data in the window of the screen of the display device is less than the number of display data in the specified display area of the second video RAM, the display data is displayed from the specified display area of the second video RAM. Claim 1 characterized in that it has a function of thinning out and extracting the addresses of the display data in the process of extracting it, and compressing and displaying the display data in the display area of the second video RAM by superimposing it on a window of the screen. An information device having a display device that performs screen compositing as described above. (3) If the number of display data in the window of the screen of the display device is greater than the number of display data in the designated display area of the second video RAM, the cycle for retrieving display data from the display area of the second video RAM; slow down so that the same display data is displayed in several dots on the screen, and enlarge and display the specified display area of the second video RAM by superimposing it on the window. An information device comprising a display device for screen composition according to claim 1.