JPH04195346A - Pseudo trouble generating method - Google Patents

Abstract

PURPOSE:To verify a trouble process sufficiently by providing an address comparing function of hardware, an EIJ trigger address table, an EIJ injection program address table, and an EIJ inspection program. CONSTITUTION:Such a data pattern that a parity error signal of a data bus (n) is generated in an EIJ kind specification register 25 as the program is executed is set. Consequently, a data bus nEIJ signal is transmitted as a signal 306 to an AND 27 by passing the set data pattern through a decoder 26. Then the output signal 307 of the AND 27 can invert the parity signal 308 of the data bus by an EOR 28 in EIJ enable mode and a check latch 30 can be turned ON by supplying the output signal 309 of the EOR 28 and data bus (n) data 310 to a parity checker 29. Consequently, the verification accuracy of a trouble processing part can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for verifying a fault handling function of an information processing device, and particularly relates to a method for generating a pseudo fault to efficiently generate a pseudo fault under desired conditions. .

[Conventional technology]

Conventionally, methods for detecting failures that occur in information processing equipment in advance or diagnosing the repair status of equipment that has caused fixed failures include methods using an independent maintenance computer and methods using hardware microprograms. There are two methods: a method using a software diagnostic program, and a method using a software diagnostic program.

For example, in the device described in Japanese Patent Application Laid-Open No. 59-35244, a microprogram (
EIJ is generated when the address of the microprocessor (hereinafter abbreviated as μp) and the address of the instruction word executed by the microprocessor match.

With this method, it is difficult to sufficiently verify fault handling, for example, it is impossible to generate an EIJ when the address of a microprogram is passed n times. Also,
In order to externally supply the μp address that causes the failure, it is necessary to modify the external test parameters in conjunction with the change of μp.

[Problem to be solved by the invention]

In the above conventional technology, since the method is to generate EIJ when it is desired to execute the μp address given from the outside, the EIJ
There are problems in that there are limits to the occurrence conditions, making it impossible to sufficiently verify fault handling, and that each time the μp is changed, the μp address given from the outside must be changed.

An object of the present invention is to provide a method for generating a simulated failure that can improve these problems and sufficiently verify failure handling by generating various simulated failures under various operating environments of information processing equipment. Our goal is to provide the following.

[Means to solve the problem]

In order to achieve the above object, the pseudo failure generation method of the present invention provides a portion (E
The IJ enable latch, EIJ type designation register, etc.) and the interrupt section (E IJ - trigger address register, conveyor circuit, etc.) are made independent and controlled by μp.

That is, in a pseudo fault verification system composed of an EIJ verification processing device and an EIJ generation processing device, the EIJ
A table (EIJ trigger address table) for registering the required number of points of E engineering J trigger addresses to generate J, a register (EI J trigger address register) for setting the trigger addresses 1 to 1, and the trigger address and A means for comparing the instruction execution addresses of the EIJ generation processors and notifying the program if they match (conveyor circuit, address conveyor match interrupt request signal), and a register for setting EIJ generation parameters (EIJ type specification). register) and the desired E
EI for performing EIJ injection processing when IJ generation conditions are met
It is equipped with an J injection program and a table (E I J injection program address tape) for registering the execution start address of the program, data is set in the EIJ type specification register, and external (E I J verification The EIJ trigger address in the address table is determined from the selection code given from the
, is set in the EIJ trigger address register, and if the contents of that register match the instruction execution address of the EIJ generating processor, that processor is contacted with an address conveyor match interrupt request signal from the conveyor circuit, and that processor is separately From the selection code given by E
Find the execution start address in the IJ injection program address table, execute the EIJ injection program, and determine the desired EIJ generation condition.
By injecting the causes of occurrence, hardware EIJ and software EI such as program logic contradictions and forced busy for a certain period of time can be detected.
It is characterized by generating J.

[Effect]

In the present invention, the EIJ trigger address in the EIJ trigger address table is determined from the EIJ trigger address selection code given from the outside, and is set in the EIJ trigger address register.

When the program execution address and the contents of the EIJ trigger address register match, the EIJ injection program address table E-J injection program is executed from the EIJ injection program and selection code given separately from the outside, and the target is determined. The conditions for the occurrence of EIJ are determined, and the E
When IJ generation conditions are met, EIJ is generated by injecting a hardware or software EIJ factor.

Therefore, for example, when passing a certain address n times, EIJ
"," EI when buffer busy is detected n times
This makes it possible to verify the occurrence of EIJ under complex conditions such as 'generating J', the occurrence of software failures, etc., and it is expected that the verification accuracy of the failure processing unit will be improved.

In addition, since the method performs verification by specifying a selection code from the outside, it is possible to reduce the influence of changes in the microprogram etc. on the verification program and reduce the number of verification steps.

[Example]　゛ An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a configuration diagram of an EIJ verification system according to an embodiment of the present invention.

In FIG. 2, 1 is an EIJ verification processing device that monitors ELJ generation requests and EIJ generation, and 2 is an EIJ generation processing device that generates EIJ in accordance with EIJ generation requests. Consists of equipment.

Further, 21 is a processor that controls program execution;
22 is an EIJ connected by a processor bus 301
Trigger address register 23 is the output 303 of the EIJ trigger address register 22 and the conveyor circuit 302, 2
4 is an EIJ enable latch that allows EIJ injection; 3
05 is an enable signal, 25 is an EIJ type designation register for determining which EIJ is generated, and 26 is an E
Target EI from the contents of the I'J type specification register 25
A decoder 27 takes out the J generation signal 306, and 27 is an AND circuit (A
ND), 28 is an exclusive OR circuit (FOR) of the E-IJ enable signal 305 and the parity signal 308, 29 is a parity checker, and 30 is a check clutch.

Further, 304 is an address conveyor interrupt signal which is an output signal of the match result of the conveyor circuit 23, and 3o7 is an AND2
7 (7) output, 309, EOROR availability inversion signal 10 is data bus data.

Here, the tables and programs used for EIJ generation processing will be described.

FIG. 3 is an explanatory diagram of a table and a program used for EIJ generation processing in an embodiment of the present invention.

In Figure 3, (a) takes into consideration the EIJ verification items,
Select any address on the program executed by the EIJ generation processor and set the EIJ trigger address (1) to (
EIJ trigger address table stored as n), (
b) is the EIJ injection program (1) to (n
) execution start address (EIJ injection program (1) ~
(n) Address) is the EIJ injection program address and stable, and (c) is the EJ injection program address when the EIJ generation condition is met.
EIJ injection program (1) to (n
).

Next, EIJ generation parameters (input data) given from the ErJ verification processing device W1 to the EIJ generation processing device [2]
Let's talk about.

"FIG. 4 is an explanatory diagram of EIJ generation parameters in one embodiment of the present invention.

In FIG. 4, 401 is EIJ mode identification information;
2 is an EIJ trigger address selection code for finding the EIJ trigger address in the EIJ trigger address table shown in FIG. 3, and 403 is an EIJ injection program selection code for finding the start address of the EIJ injection program in the EIJ injection program address table. .

Further, details of the EIJ mode identification information 401 will be described next regarding EIJ input cover parameter processing and address match interrupt processing when the EIJ generation method of the present invention is applied.

FIG. 1 is a flowchart showing EIJ input cover parameter processing in one embodiment of the present invention, and FIG. 5 is a flowchart showing address match interrupt processing in one embodiment of the present invention.

In this embodiment, the EIJ generation parameters shown in FIG. 4 are transferred from the EIJ verification processing device 1 to the EIJ generation processing device 2.
as a command. In the EIJ generation processing device 2,
It receives this as a command and analyzes and processes it as shown in Figure 1.

That is, as a result of determining the command, if it is an EIJ command and the EIJ mode identification information 401 of the EIJ generation parameter is an EIJ mode setting request, the EIJ
mode and set the EIJ enable latch 24 (101 to 103).

Next, if the EIJ mode identification information 401 is valid for the E/J trigger address (105), the process proceeds to step 106, and the EIJ trigger address shown in FIG. Trigger address (1) to (n) from the table
), and select one of the EJ trigger address registers 22.
(106).

This trigger address is held in the EIJ trigger address register 22 and compared by the conveyor circuit 23 with the instruction execution address of the EIJ generating processor. As a result, if there is a match, an address conveyor match interrupt request signal 304 is given to the processor 21 to generate an interrupt.
Execution of the interrupt processing shown in FIG. 5 is started.

In the interrupt processing shown in FIG. 5, it is determined whether it is an address conveyor interrupt (501), and if so, the EIJ injection program valid bit is checked (502).

If it is valid, the EIJ injection program selection code 403 of the EIJ generation parameter selects the EIJ injection program from the EIJ injection program address table shown in FIG. 3(b).
The J injection program finds one of the addresses (1) to (n) (503) and branches to the execution address.

In this step 503, if it is assumed that the EIJ injection program to be executed is a hardware failure program that causes a parity error on data bus n, the execution of the program causes the EIJ type specification register 25 in FIG. Set a data pattern that will generate a parity error signal. As a result, by passing the set data pattern through the decoder 26, the data bus nEIJ signal is transmitted as a signal 306 to the AND 27. If EIJ is enabled, the output signal 307 of AND27 converts the parity signal 308 of the data bus into EO.
The check clutch 30 can be turned on by applying the output signal 309 of the EOR 28 and the data bus n data 310 to the parity checker 29.

In addition, in step 105 of FIG. 1, when the EIJ trigger address valid flag is off (immediate mode), the trigger address is not set and immediately steps 107 to 1
09 to inject the fault.

Note that the conveyor circuit 23 can also share an existing circuit, thereby suppressing an increase in the amount of hardware.

〔Effect of the invention〕

According to the present invention, by providing a hardware address conveyor function, an E/J trigger address table, an EIJ injection program address table, and an EIJ injection program, it is possible to verify the occurrence of EIJ under complex conditions and the occurrence of software failures. This makes it possible to improve the verification accuracy of the failure processing unit.

Furthermore, since verification is performed by specifying a relative selection code without directly specifying the EIJ trigger address or EIJ generated data, changes in the microprogram etc. can have less impact on the verification program, reducing the number of verification steps. can.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing EIJ input parameter processing in an embodiment of the present invention, FIG. 2 is a configuration diagram of an EIJ verification system in an embodiment of the present invention, and FIG. 3 is a flowchart showing EIJ input parameter processing in an embodiment of the present invention. FIG. 4 is an explanatory diagram of the table and program used for processing, FIG. 4 is an explanatory diagram of EIJ generation parameters in an embodiment of the present invention, and FIG. 5 is a flowchart showing address-adversary infiltration processing in an embodiment of the present invention. . 1: EIJ verification processing device, 2: EIJ generation processing device, 21: Processor, 22: EIJ trigger address register, 23: Conveyor circuit, 24 2 EIJ enable latch, 25: EIJ type specification register, 26: Decoder, 27: logical product circuit (AND), 28: exclusive OR circuit (FOR), 29 parity checker, 30: check clutch, 301: processor bus, 302: instruction address bus. 303: Output of E/J trigger address register 22, 3
Q4 Near address conveyor interrupt signal, 305: Enable signal, 306: EIJ generation signal. 307: AND27 output, 308: Parity signal, 3
09: FOROR availability inversion signal 10: Data bus data, 401: EIJ mode identification information, 402
:EIJ trigger address selection code. 403: EIJ injection program selection code. Figure 3 (Part 1) Q to (a). Figure 5

Claims (1)

[Claims] 1. In a simulated failure generation method of a simulated failure verification system that verifies the failure handling function of an information processing device by generating a simulated failure, a table for registering a simulated failure trigger address in a preselected processing program, and a table for registering the trigger address in a preselected processing program are provided. a register for setting, a means for comparing the trigger address and an instruction execution address of the pseudo-failure processor, and notifying the program if they match;
It includes a register for setting parameters for specifying a pseudo fault, a pseudo fault injection program for performing pseudo fault injection processing when a target pseudo fault occurrence condition is met, and a table for registering the execution start address of the program. , data is set in the parameter setting register, the pseudo-failure trigger address in the trigger address table is determined from the externally given selection code, and set in the trigger address register, and the contents of the register and the instructions of the processor in which the pseudo-fault has occurred are determined. If the execution addresses match, the comparison/communication means contacts the processor, and the processor uses the selection code separately given from the outside.
Find the execution start address in the above injection program address table, run the pseudo-fault injection program, and when the condition is satisfied by determining the target pseudo-fault occurrence condition, inject pseudo-fault causes including hardware and software to simulate the problem. A pseudo failure generation method characterized by generating a failure.