JPH04194605A - Inspecting method for line width of printed circuit board - Google Patents

Abstract

PURPOSE:To enable a line width of a printed circuit board to be inspected in a short time by turning the line width into a histogram and referring to its extremes and then obtaining a reference value needed for determining whether the line width is proper or not stably and automatically. CONSTITUTION:Printed circuit boards 11 and 11s are sent in a transport direction Y while the image is read in the order of scanning lines by a reading device 20 for each in a line direction X. Then, the read image data is sent to binary coding circuits 21a and 21b. The circuit 21a generates a hole image original HIS0 and the circuit 21b generates a pattern image original signal PIS0. Both these signals are fed to a pattern inspection circuit 30. The circuit 30 inspects a wiring pattern and a relative position relationship between this and a through-hole and gives the result to a central processing unit MPU 50. The MPU 50 controls the entire device through a control system 51. A CRT 60 receives commands from the MPU 50 and displays each operation result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for inspecting line widths of printed circuit boards, and more particularly to a method for determining reference values of line widths.

[Conventional technology]

As electronic components become smaller, lighter, and have higher performance, the wiring patterns of printed circuit board circuits are also becoming finer and more dense, creating demands for thinner lines and smaller diameter through holes.

Inspection and management of the width of such thin lines has become even more important than before.

When inspecting and managing the line width of this wiring pattern, it is necessary to know in advance the standard dimensions. That is, a certain tolerance value is set for this reference value, and lines with dimensions within this range are considered good, and lines with dimensions outside the range are judged to be defective.

However, generally this line width is, for example, 80 to 400 μm.
Although it is within a range of about m, it varies depending on the type of printed circuit board to be inspected. In addition, a single printed circuit board may have several types of line widths, and in this case, standard values for these line widths are determined in advance depending on the type of each board or line type. It is necessary to find out.

For this reason, conventionally, a worker visually measures the line width of a sample board of the same type as the printed circuit board to be inspected using a tool such as a magnifying glass or a microscope, and obtains a reference value.
The line width was determined by inputting it into an automated printed circuit board inspection device.

[Problem to be solved by the invention]

However, determining the line width standard value in this way not only has the problem of introducing measurement errors due to inherent individual differences and time differences, but also changes in the type of board to be inspected. Since this method requires manual labor each time, there is a problem in that it prevents automation of the entire printed circuit board inspection and makes it difficult to shorten the time required for printed circuit board inspection. Therefore, if it is possible to automatically determine the reference value of this line width, we will advance automation in the inspection of printed circuit boards.
This will greatly contribute to shortening the time required for the inspection.

This invention was made in consideration of the above-mentioned circumstances, and it is possible to stably and automatically obtain the reference value necessary for determining the pass/fail of the line width, thereby making it possible to inspect the line width of printed circuit boards. The purpose of this invention is to provide a method for inspecting line widths of printed circuit boards that can be performed in a short time.

[Means to solve the problem]

In this invention, based on image data read pixel by pixel by photoelectrically scanning a printed circuit board having a wiring pattern,
In inspecting the width of the lines in the wiring pattern, first, (a) obtain the image data of the sample board, and obtain an image of the wiring pattern on the sample board based on the image data;

Then, (b) the line width is determined for each line portion in the image of the wiring pattern determined in step (a), and (c) the line width is converted into a histogram.

Next, (d) a reference value for the line width is determined with reference to the extreme values of the histogram.

When inspecting the line width of a printed circuit board to be inspected, the above reference value is used as a comparison standard for the line width detected for the printed circuit board.

Note that the sample board may be one (or more than one) of the printed circuit boards to be inspected, or may be prepared separately.

[Effect]

In this invention, by converting the line width into a histogram and referring to its extreme values, information about the standard value of the line width of the sample board can be obtained, and this standard value is used to compare the line width of the printed circuit board to be inspected. Used as a standard.

〔Example〕

A. Overall configuration and general operation FIG. 2A is a block diagram showing the overall configuration of a pattern inspection apparatus to which an embodiment of the present invention is applied.

On the stage 10 is a printed circuit board 11 to be inspected.
Alternatively, sample substrate IIs is placed.

Substrate 11. IIs is sent in the transport direction Y while its image is sequentially read in the scanning line by the reading device 20 in each line direction X. The reading device 20 has a plurality of CCDs each having several thousand elements arranged in series in the line direction X, and reads the pattern of the substrate 11.11s for each pixel. The read image data is sent to the binarization circuit 21a.
, 21b. The binarization circuit 21a generates a hole image original signal Hrso, which will be described later, and the binarization circuit 21b generates a pattern image original signal PIS, which will be described later. generate. Both the signals H1s and PISo are input to the pattern inspection circuit 3o.

The pattern inspection circuit 3o has a function described later, inspects the wiring pattern (including lands) and the relative positional relationship between this and the through-hole, and sends the results to the central processing unit (MP).
U) Give 50.

The MPU 50 controls the entire device via a control system 51. The control system 51 generates an XY address and the like for specifying the address of data obtained by the pattern inspection circuit 30. The XY address is also given to the stage drive system 52 to control the transport mechanism of the stage 10.

The CRT 60 receives instructions from the MPU 50 and displays various calculation results, such as a hole image. The keyboard 70 is used to input various commands to the MPU 50.

The option section 80 includes a defect confirmation device 81. A defective product removing device 82, a defective position marking device 83, and the like are arranged. The defect confirmation device 81 is a device for enlarging and displaying a detected defect on, for example, a CRT. Moreover, the defective product removal device 82 removes the defective printed circuit board 1.
1 is detected, the device transports the printed circuit board 11 to a tray for defective products. Further, the defect position marking device 83 is a device for directly marking a defective portion on the printed circuit board 11 or at a point on the sheet corresponding to the defective portion. These devices are installed as needed.

B. Reading optical system FIG. 3A shows the stage 10. shown in FIG. 2A. Substrate 11.
2 is a diagram showing an example of a reading optical system configured by IIs, a reading device 20, and the like. FIG.

In FIG. 3A, the light from the light source 22 is reflected by the /'t-fu mirror 23 and is reflected by the printed circuit board 1 of the stage drive system.
1. On the printed circuit board 11, a base B, a line L, a through hole H, and a land R around the base B are present.

The reflected light from the printed circuit board 11 passes through the nof mirror 23, and further enters the CCD 24 provided in the reading device 20 via the lens 25.

The CCD 24 is connected to the printed circuit board 11 that is sent in the transport direction Y.
Upper base B, line L, through hole H.

The reflected light from the land R etc. is read line by line.

FIG. 4 is a graph showing a signal waveform read along line AA' in FIG. 3A, and an example of a pattern obtained by combining the signal waveforms.

As shown in the signal waveform in Figure 4, there is relatively little reflected light at base B, and the threshold values THI, TH2 (THI<TH
A signal with a level between 2) is generated. Wiring pattern P
(Line L and land R) are formed of metal such as copper, so there is a lot of reflected light at this part, and the -value T
A signal of level H2 or higher is generated. In addition, in the through hole H, there is almost no reflected light, and the threshold value THI
Signals with the following levels are generated: Furthermore, an edge E usually exists between the through hole H and the land R, or between the line L and the base B. There are wobbles and inclinations in this part, and the reflected light level in this part does not take a particularly constant value, but is approximately between the threshold value TH1 and the threshold value TH2.

The signal from the reading device 20 is sent to the binarization circuit 21 in FIG. 2A.
g, 21b, for example, the threshold THI.

Each is binarized using TH2. Binarization circuit 21
a generates a hole image H1 indicating a through hole H, and the binarization circuit 21b generates a pattern image PI indicating a wiring pattern P (line L and runt R). These two images H1°PI are used as signals necessary for processing to be described later.

FIG. 3B is a diagram showing another example of the reading optical system. The light from the light source 22a is irradiated onto the CCD 24 in the reading device 20 as reflected light via the half mirror 23 and the lens 25, as in the example shown in FIG. 3A. In this example, a light source 22b is further provided on the back side of the stage 10, and the light passing through the through hole H is also irradiated onto the CCD 24. Therefore, in the through hole H, the signal level is the highest, in the wiring pattern P (line L and land R), the signal level is medium, and in the base B and edge E, the signal level is relatively low.

Furthermore, as another example, two or more rows of CCD24 are prepared,
The light source 22a detects the wiring pattern P (line L and land R), and the light source 22b detects the through hole H.
The configuration may be such that only the data is detected and the data is separately output to the subsequent binarization circuit.

C. Pattern Inspection Circuit FIG. 2B is a block diagram showing the internal configuration of the pattern inspection circuit 30 shown in FIG. 2A.

The hole image original signal H1s and pattern image original signal PISo generated by the binarization circuits 21a and 21b in FIG. 2A are provided to noise filters 32a and 32b, respectively, via an interface 31. The noise filters 32a and 32b perform smoothing processing and the like to remove noise and generate a hole image signal HIS and a pattern image signal PIs, respectively.

Hole image signal HIS and pattern image signal PI
Both of S are the comparison test circuit 33. DRC (Design
nRu1e Check) circuit 34. It is applied to all through-hole inspection circuits 35.

The comparison inspection circuit 33 is a circuit that compares and collates the hole image signal IIS and the pattern image signal PIS with an image signal obtained from a reference printed circuit board that has been pre-prepared, and identifies portions where they differ from each other as defects. be. As the reference printed circuit board, a printed circuit board that is of the same type as the printed circuit board 11 to be inspected and that has been determined to be a good product is used. This method (comparative method) is for example
It is disclosed in Japanese Patent No. 263807.

The through-hole inspection circuit 35 detects the relative positional relationship between the land R and the hole H on the printed circuit board 11, and tests the quality of the printed circuit board 11 by determining whether this deviates from the designed value. It is a circuit. This inspection method is disclosed, for example, in Japanese Patent Application No. 1-82117 filed by the present applicant.

D. DRC Circuit (D~1), Overview Before explaining the detailed structure and operation of each part of the DRC circuit 34, an overview thereof will be described below.

FIG. 1A is a block diagram showing an overview of the DRC circuit 34, and FIG. 1B is a flowchart showing the flow of the operation of the circuit 34.

The line and line width detection unit 36 is a circuit that measures the width W of the wiring pattern P on the sample substrate IIs from the input pattern image signal PIS and outputs a line signal LKO for determining whether this is the line L or not. and corresponds to step 5 IOI.

This width W and line signal LKO are calculated by the histogram generation section 37.
and becomes part of the histogram data. That is, if it is determined in step 5102 that it is line L, the memory data (frequency) WD whose address is line width W is increased by 1 as shown in step 8103. However, before starting the measurement, the memory 37c in the histogram main forming section 37, which will be described later, is cleared in step 5100.

When the line width W of the line L at a certain location is thus used as data, the next wiring pattern P is inspected in step 5104. When all wiring patterns P are inspected in step 5105, step 810
6, the contents of the memory 37c are read out and the local maximum value W
The address W, which takes D+, is adopted as the reference value.

The CPU 3g corresponds to step S106.

Line and line width detection section 36. Histogram generation unit 37. All of the CPOs 38 are connected to the MPU 50 by address buses AB and data buses DB, and the above-mentioned processing commands and data such as line width W are exchanged with each other through these buses AB and DB.

(D-2) Detection of line and line width FIG. 5 is a block diagram showing an outline of the line and line width detection section 36, and FIGS. 9 to 11 are flowcharts showing the flow of the operation of the intermediary section 36. It is.

The two-dimensional expansion unit 36a is a circuit that two-dimensionally expands the pattern signal PIS to generate a pattern image PI in correspondence with step 5200, and is formed of a group of shift registers as shown in FIG. In the same figure, pixel P
IX is a constituent unit forming the pattern signal PIS, but it does not necessarily have to be the minimum unit, and may be a set of multiple predetermined minimum units. ”.

Here, it is assumed that the signal indicating the existence of the wiring pattern P is "1 degree" and the signal indicating the base layer B is "0".

Pixel PI expanded two-dimensionally by shift register group
A cross operator OP is applied to X to determine whether it is a line or not, and to measure the width W of the pattern P. In FIG. 6, 0 is the center of the operator OP, and arms extend in the X direction and Y direction (including positive and negative directions, respectively).

FIG. 7 shows the case where the operator OP is applied to the line L running in the Y direction. What is actually affected are the line image LI and the base image Bl, but for ease of understanding, they are also expressed as line L1 and base image B.

Now, the center 0 of the operator OP is on the pixel PIX having a value of "1". If the pixel corresponding to center O is “
If it is "0", it means that it is the base B, it is no longer the pattern P, and there is no need to measure the width, so the line signal LKO is output as "0°" (steps 5201 and 5202 in FIG. 9). . On the hardware, AND in Figure 5
0- from the two-dimensional development section 36a to the gates 36f and 36g.
0 is output, and the line signal LKO, which is the output of the OR gate 36j, is set to "0" as 5X-5Y-0.

Returning to FIG. 7, if the pixel PIX corresponding to the center 0 is "12", that is, if it is O-1, the operator's arm L - L4
The respective lengths LD1 to LD4 are determined (steps 5201 and 3203 in FIG. 9). On the hardware, priority encoders 36b to 36e count the value of pixel PIX "1 degree" in the direction away from the center O. In the case of FIG. 7, LD -10, LD2-10. ... (1
)LD-3,LD4-5...(2
) (center O is not counted).

Next, using the value of LD - LD4, it is determined whether the center O is on the line L and the width of the pattern P where the center 0 is located. If the arm L1 is "1" in all bits in steps 5204 and 5205, the all-bit conductor signal is set as LO-1 (each of i-1 to i-4 is processed). In the case of FIG. 7, L and L2 are all bits “
1", and L■8 and L4 include "0°, so LO-1, LO□-1...(3) LO-0, LO4-san0...(4). Generation of this all-bit conductor signal is also performed by the priority encoders 36b to 36e.

The fact that equation (3) holds indicates that the wiring pattern P runs in the Y direction near the center O. In other words, by establishing equation (3), the wiring pattern P can be changed to the line L.
The line width W can be determined from the arm lengths LD and LD4 in equation (4). FIG. 10 shows this flow. In the case of FIG. 7, it is determined in step 5211 that the wiring pattern P has been lined, and step 5
In step 212, 5Y-1 is set as the line direction signal.

On the hardware, the AND gate 36f is ONL, and the line direction signal 5Y-1 is the OR gate 36j and the multiplexer 36.
sent to k.

The same applies when line L runs in the X direction, step 5
Flows from step 211 to step 8213, and step 521
4 makes the line direction signal 5X-1.

On the hardware, the A N D gate 36g is ONL, and the line direction signal 5X-1 is sent to the multiplexer 36k as the OR gate 36.

A line L whose center O runs in the X or Y direction
If it is determined that it is above (step 5212.
5214) The line signal LKO is set to "1'" (step S215). On the hardware, the "OR gate 36" corresponds to this.

Note that when the operator OP acts on a very wide wiring pattern P such as a power supply pattern, all bits in the arms L-L4 and the center O become "1", and LO-LO-LO3-LO, -1. ...(5) may hold true. In this case, AND game) 36f, 36
g is OFF, and the line direction signal is 5x-sy-o (6), so the OR gate 36j is 0FFL, and the line signal LKO is "0", so it is not determined that the line is L (step 5216). ).Arm length L -L as shown from now on
4 needs to be set longer than the expected line width.

Next, in FIG. 11, the line width W is determined.

As shown in steps 5211 and 5213 in Figure 10, the flow that flows to terminal J2 is either 5X-O, 5Y-1...(7), or 5X-1 and 5Y-0...(8). In this case, step 5 in Figure 11
The calculation of the line width W may be selected using only the value of SX as shown in 217.

If the above formula (7) applies, that is, if the line L is in the Y direction, then in step 5218, the line width W is determined by W-LD +LD4+1 taking into account the center O.
...Find as (9).

On the hardware, the adder 36i adds LD3+LD4+1.
is determined and sent to input D2 to multiplexer 36. This multiplexer 36 has 5Y-1 output Q.
is set to be equal to D2, and as a result (9
) can be used to obtain the output of Eq.

When the above formula (8) is satisfied, that is, when the line L runs in the X direction, W−LD +LD2+1 .
)■ Find it as.

On the hardware, the adder 36h adds LD, +LD2+
1 is determined and sent to input Dl to multiplexer 36. The second multiplexer 36 is provided with 5X-1 to make the output Q equal to Dl, and finally (1
0) We can obtain the output of Eq.

Further, FIG. 8 shows a case where the center O is not on the line L but on the land R. Among arms L-L4, only L4 has all bits "1#," so LO-LO-LO3-0...(11) LO4-1...
・(12) holds true. Therefore, in steps 5211 and 8213, it is determined that the center O does not exist on the line L, and the flow goes to step 8216, and the line signal LKO becomes "0".On the hardware, the AND gates 36f and 36g are set to 0FF.
L, (6) holds true.

In this way, when (6) holds in the line direction signal, the output Q (W) to the multiplexer 36 becomes unstable, but in the histogram generation section 37, which will be described later, when the line signal LKO is "0", the output Q (W) becomes unstable. Since the line width W is ignored, the effects of the present invention are not impaired.

(D-3) Generation of Histogram FIG. 12 is a block diagram showing the configuration of the histogram generation section 37, and the operation of the rotation section 37 is shown in steps 5100 and 5IO2 to 5106 in the flowchart of FIG. 1B.

First, before processing the pattern signal PIS, step 5100
The memory 37 stores histogram data in advance by
Set all 7 in the data of c to "0". This memory 3
The address 7c corresponds to the line width W, and the data WD stored at that address corresponds to the line L having that line width W.
is the frequency of

Therefore, setting all data contents to '0' corresponds to clearing the frequency WD of the line width W.

Specifically, the control section 37b gives the zero clear signal ZCL to the memory zero clear 37d to set all data WD on the data line to "0", and the control section 37b gives the memory write signal WRT to the memory 37c to perform the above-mentioned "0". 0° is written. At this time, the address W changes sequentially by outputting the count data of the self-running counter provided in the memory zero clear 37d to the address line, and eventually the data content is "02" at all addresses in the memory 37c.
becomes.

Next, in step 5102, histogram data is created only on line L. This is line signal L
This is performed by the data counting section 37e that receives the KO receiving the line width W only when the LKO is -1. The data counting section 37e further outputs the line width W to the address line, and increments the data WD in the memory 37c corresponding to this address by 1 and rewrites it.

In step 5104, the memory rewriting as described above is repeated every time the line signal LKO is received, and -
Once the window area has been scanned, the histogram generation is completed in step 5105.

FIG. 13 shows a conceptual diagram of the histogram obtained in this manner. The horizontal axis represents the line width W1, that is, the address of the memory 37c, and the vertical axis represents the frequency WD, that is, the data stored in the memory 37c using the line width W as an address. This figure shows a histogram when three types of line widths exist in one sample substrate IIs.

(D-4) When the histogram generation is completed in the reference value setting step 5105, a memory read signal RD is given from the control unit 37b to the memory read/write buffer (hereinafter referred to as "buffer") 37a to read the contents of the memory 37c. It is taken into the buffer 37a via the address line and data line. This content is sent to the CPU 38 via the data bus DB and the address bus AB, and is sent to the CPU 38 to determine characteristic values of the histogram, such as the local maximum value WD of the frequency WD, WD2 . Standard values W,, W2゜W corresponding to W■ D,..., respectively
a, . . . are determined (step s106 in Fig. 1B)
).

The CPU 38 not only sets this reference value, but also sends a control signal CTL to the control section 37b to indirectly control the operation of the control section 37b and, therefore, the operation of the histogram generation section 37.

(D-5) , Line width inspection Standard value of line width obtained as above W1゜W ,
Using Wa, the line width W of the printed circuit board 11 to be inspected is inspected.

The measurement of the line fW of the printed circuit board 11 can be obtained by performing the processes (D-1) and (D=2) in the same manner as in the case of the sample board IIs. The line width W of the printed circuit board 11 obtained in this way is the reference value W, W2
．． The quality of the product is determined using W3 as a comparison standard.

The sample board 11g used in the processes (D-1) to (D-4) may be one (or more than one) of the printed circuit boards 11 to be inspected, or may be of the same type as the printed circuit board 11. It may also be prepared separately.

E. Modifications The present invention is not limited to the above-mentioned embodiments, and for example, the following modifications are also possible.

(1) The configuration of the DRC circuit 34 is not limited to that shown in FIG. 1A, and may include a processing section that performs other DRC processing, such as a section that checks the quality of the line width and a section that inspects pattern chipping. You can leave it there. In particular, the present invention provides a DRC circuit 3 having a portion for checking the quality of line width.
In step 4, using it as a pre-treatment for the check portion produces a great effect.

(2) As a specific method of step 5101 in FIG. 1B, in (D-2), the width W and the line signal LKO are obtained using the crosshair operator oP, but it is not necessarily necessary to use the crosshair operator. For example, if the line L runs at 45° or 135° with respect to the X direction, the 14th
An operator equipped with eight arms L-L8 as shown in the figure may also be used.

Although the priority encoders 36b to 36e are used in FIG. 5 to determine the arm length of the operator OP, a ROM table whose addresses are arms L1 to L4 may also be used.

(3) In (D-3), the line width W was counted every time the line signal LKO was input, but a histogram is generated even if it is not necessarily counted corresponding to every line signal LKO, and its characteristics can be obtained. be able to. Therefore, for example, in FIG. 13, before inputting the line width W and line signal LKO to the data counting section 37e, the number of data may be reduced by once passing the line width W and line signal LKO through a sampling circuit. This has the effect of reducing the capacity of the memory 37C.

(4) In the CPU 38, the maximum value W of the histogram
In addition to finding D , WD , WD , . . . , a permissible value for the line width W may be determined. For example, the maximum value can be used as a reference value for the line width W, and ±30% of the maximum value can be used as an allowable value as a criterion for later line width inspection. Particularly, regarding the sample substrate itself used to determine the reference value of the line width, there is also an advantage that the histogram can be compared with the above-mentioned tolerance value to immediately determine the quality of the sample substrate itself without further inspection.

〔Effect of the invention〕

As explained above, in the printed circuit board line width inspection method of the present invention, the line width of the sample board is made into a histogram, and the reference value for the line width is determined by referring to the Hiss and Durham extreme values. When inspecting the line width of a printed circuit board to be inspected, the above reference value is used as a comparison standard for the line width detected for the printed circuit board. Therefore, it is possible to stably and automatically obtain a reference value necessary for determining whether the line width is acceptable or not, which has the effect that the line width inspection of a printed circuit board can be performed in a short time.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing the configuration of the DRC circuit 34, FIG. 1B is a flowchart showing the operation flow of the DRC circuit 34, and FIG. 2A is a diagram showing the overall configuration of a pattern inspection device to which an embodiment of the present invention is applied. 2B is a block diagram showing the configuration of the pattern inspection circuit 30, FIGS. 3A and 3B are conceptual diagrams showing reading by photoelectric scanning, and FIG. 4 is a signal waveform read by FIG. 3A and its 5 is a block diagram showing the configuration of the line and line width detection section 36, FIG. 6 is a conceptual diagram showing the two-dimensional expansion section 36a, and FIGS. 7 and 8 is a conceptual diagram of the crosshair operator OP, FIGS. 9 to 11 are flowcharts showing the operation flow of the line and line width detection section 36, FIG. 12 is a block diagram showing the configuration of the histogram generation section 37, and FIG. Conceptual diagram of a histogram. FIG. 14 is a diagram showing an operator in another embodiment of the present invention. 11.1. Printed circuit board, lls...sample board,
36...Line and line width detection unit, 37...Histogram generation unit, P...Wiring pattern, PI...Pattern image, L...Line, Ll...Line image, W...・Line width,

Claims (1)

[Claims] (1) A method for inspecting the line width of a printed circuit board, which inspects the width of a line in the wiring pattern based on image data read for each pixel by photoelectrically scanning a printed circuit board having a wiring pattern, the method comprising: a) Obtain the above image data for the sample board, and based on the image data,
(b) determining the line width of each line in the image of the wiring pattern obtained in step (a); (c) determining the line width. and (d) determining a reference value for the line width by referring to the extreme values of the histogram, when inspecting the line width of a printed circuit board to be inspected.
A method for inspecting line widths of printed circuit boards, characterized in that the above reference value is used as a comparison standard for line widths detected for the printed circuit boards.