JPH04192639A - Signal quality detection circuit - Google Patents

Abstract

PURPOSE:To detect signal quality in an excellent way without being affected by external noise or the like by detecting a jitter component or the like from a fixed pattern of an input data. CONSTITUTION:One output of a high frequency (RF) reception section 10 is connected to a demodulation section 14 via an intermediate frequency(IF) conversion section 12 and a demodulation signal output of the demodulation section 14 is given to an input of a jitter detection circuit 20 via a comparator (COM) 18 for signal binarization and a low-pass filter(LPF) 16. The other output of the high frequency reception section 10 is connected to the jitter detection circuit 20 via a signal detection circuit 22 and the signal detection circuit 22 outputs a signal representing a preamble period. Thus, even when a level of external noise is high, the propriety of the signal quality is discriminated in an excellent way.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a transmission device for packet data having a signal period with a fixed data pattern,
In particular, it relates to a signal quality detection circuit that determines whether the signal quality is good or bad.

[Background Art 1] An example of data transmission having a signal period with a fixed data pattern is packet data transmission. Packet data in this packet data transmission generally consists of a preamble, data, and postamble, as shown in FIG. That is, non-data parts called preamble and postamble are added before and after the data to be transmitted. Among these, the signal form of the preamble part is a pattern of consecutive logical values "H" as shown in Figure 17 (A), and a pattern of consecutive logical values "L" as shown in Figure 17 (B). There are patterns, such as a pattern in which rHJ and "L" appear alternately, as shown in FIG. By the way, in a wireless modem device or the like that spatially transmits such packet data, the quality of the signal is determined based on the reception strength of the signal. [Problems to be Solved by the Invention] However, the reception strength of a signal also increases when external noise is received in addition to the signal. Therefore, according to the conventional technique, even if the signal quality is poor, if there is large external noise, the signal quality is erroneously determined to be good. In addition, due to the influence of variations in the determination circuit and temperature characteristics, there is also the disadvantage that setting the threshold value for quality determination requires troublesome adjustment and temperature characteristic compensation. The present invention has been made in view of the above points, and an object of the present invention is to provide a signal quality detection circuit that can satisfactorily determine whether signal quality is good or bad even when external noise is large. .

[Means to solve the problem]

According to the present invention, jitter in a fixed pattern portion of transmission data is detected by the jitter detection means, or its noise component is detected by the noise component detection means. Jitter and noise components appearing in a data signal have a strong correlation with signal quality, and the less jitter or noise there is, the better the signal quality is. In the present invention, this relationship is utilized to determine whether signal quality is good or bad based on jitter or noise components. Further, according to the present invention, the quality of the non-fixed pattern portion is also determined by comparing the carrier levels of the fixed pattern portion and the non-fixed pattern portion of data. Therefore, the signal quality is determined without waiting for the end of data transmission, and data retransmission is promptly performed.

【Example】

Embodiments of the signal quality detection circuit according to the present invention will be described below with reference to the accompanying drawings. Note that the same reference numerals are used for common or corresponding components in each embodiment. <Example 1> First, Example 1 of the present invention will be described with reference to FIGS. 1 to 5. This example is effective when the preamble has a pattern in which "r) (J, rL" is repeated as shown in FIG. 17(C).
This is an example of application to a wireless modem using the FSX modulation method using radio waves in the 00 MHz band. FIG. 1 shows the basic configuration of the first embodiment. In the figure, a radio frequency (RF) receiving section 1 that receives signals
One output side of 0 is connected to the input side of a demodulator 14 via an intermediate frequency (IF) converter 12. Demodulator 1
The demodulated signal output side of No. 4 is a low-pass filter (LPF) 16 for noise removal. Comparator for signal binarization (CO
M) 18 are connected to the input side of the jitter detection circuit 20, respectively. The other output side of the above-mentioned high frequency receiving section 10 is connected to this jitter detection circuit 20 via a signal detection circuit 22. This signal detection circuit 22 is for outputting a signal indicating the preamble period. Next, referring to FIG. 2, the jitter detection circuit 2 described above will be described.
The configuration of 0 will be explained. This circuit calculates the jitter amount by the amount of deviation from the rising edge (UP) edge of data in the preamble to the falling edge (DOWN), or the time from the falling edge to the rising edge with respect to the 1-bit time length. Detection is now taking place. In the figure, the signal from the above-mentioned comparator 18 is transmitted on the one hand to a monostable multivibrator 24. The inverter 26 is connected to the input side of a two-manufactured NAND gate 28, respectively. In addition, monostable multivibrator 24
The output side of is a two-man powered NAND gate 30. They are each connected to the input side of the inverter 32. The output side of the inverter 26.degree. 32 is connected to the other input side of the NAND gates 30 and 28, respectively. The above-described components allow the amount of jitter at the falling edge of preamble data to be detected. The signal from the above-mentioned comparator 18 is then passed through an inverter 34 to a monostable multivibrator 36 . The inverter 38 is connected to the input side of a two-man powered NAND gate 40, respectively. The output side of the monostable multivibrator 36 is connected to a two-man NAND gate 42. They are each connected to the input side of the inverter 44. Then, the output side of the inverter 38.44 is NAND
42 and 40, respectively. The above components allow the amount of jitter at the rising edge of preamble data to be detected. Next, the output sides of the NAND gates 28, 30, 40, and 42 are respectively connected to the input sides of a four-power NAND gate 46, and the output side of this NAND gate 46 is connected to the monostable multivibrator 48 and the two Each is connected to the input side of a human-powered NAND gate 50. Further, the output side of the monostable multivibrator 48 is connected to the other input side of a NAND gate 50 via an inverter 52. This component determines whether the detected amount of jitter is less than or equal to a predetermined value. Next, the operation of detecting the amount of jitter at the falling edge of preamble data will be described with reference to the time chart of FIG. Note that at time TA-TB in the same figure, the falling edge of the preamble data is the original 1.
A case is shown in which the bit length edge is advanced, and a case in which the falling edge of the preamble data is delayed with respect to the original 1 bit length edge is shown at time TC-TD. First, the operation when the falling edge advances will be explained. When preamble data (see (A) in the figure) is input, it is input to the monostable multivibrator 24, and a 1-bit long pulse is output as shown in (B) in the figure. This pulse and the input pulse are shown in (A) in the same figure.
As shown in (B), the falling edge of the input pulse leads the falling edge of the 1-bit long pulse in phase. This pulse is input to NAND gate 30 on the one hand. Input data is inverted by an inverter 26 and input to the NAND gate 30 . Therefore, the output of the NAND gate 30 is a pulse whose width is proportional to the amount of advance of the falling edge, as shown in FIG. 3(C). On the other hand, the output of the monostable multivibrator 24 is inverted by the inverter 32 and input to the NAND gate 28, and the input data is input as is to the other input terminals. Therefore, the output of the NAND gate 28 becomes as shown in FIG. 3D, and no pulse is output. In this way, when the falling edge is advanced, a pulse proportional to the amount of advancement is output from the NAND gate 3o. Next, the operation in the case of falling edge delay will be explained. In this case, the input pulse and the output pulse of the monostable multivibrator 24 are such that the falling edge of the input pulse is a 1-bit long pulse, as shown at time TC-TD in FIGS. The relationship is such that the phase lags behind the falling edge. At this time, the outputs of the NAND gates 30 and 28 are as shown in FIGS. 3C and 3D, respectively. In other words, nothing is applied from the NAND gate 30,
The NAND gate 28 outputs a pulse whose width is proportional to the amount of delay of the falling edge. As described above, the lead and lag of the falling edge of the input pulse with respect to the reference pulse output from the monostable multivibrator 24 are determined by the NAND gates 30 and 2, respectively.
It is detected as a pulse output from 8, and the amount of jitter is indicated by the pulse width. Next, the operation of detecting the amount of jitter at the rising edge of preamble data will be described with reference to the time chart of FIG. Note that at time TE-TF in the figure, the rising edge of the preamble data is the original 1.
The case is shown in which the rising edge of the preamble data is delayed with respect to the original 1-bit length edge at time TG-TH. The circuit of FIG.
A circuit from to a NAND gate 46 is provided,
A similar operation is performed on the output of inverter 34. That is, the rising and falling edges of the input data are reversed, and the same operation as described above is performed (see (A) to (E) in the same figure). Therefore, the lead and lag of the rising edge of the input pulse with respect to the reference pulse output from the monostable multivibrator 36 are detected as pulses output from the NAND gates 42 and 40, respectively, and the amount of jitter is indicated by the pulse width. become. To summarize the above operations, the NAND gate 28°30.
40, 42. The pulses output from the input data represent the advance and lag of the falling edge of the input data, and the advance and lag of the rising edge of the input data, and all types of jitter can be detected by the width of these pulses. . Next, while referring to the time chart in FIG.
The operation of the circuit after gate 46 will be explained. The four NAND gates mentioned above 28, 30, 40.42
The respective outputs (see FIG. 4A) are input to a four-man powered NAND gate 46, summed, and supplied to a monostable multivibrator 48 and a NAND gate 5o, respectively. The monostable multivibrator 48 outputs a pulse that provides a threshold value for the amount of jitter, as shown in FIG. As mentioned above, the NAND gates 28, 30, 40.4
The width of each output pulse of 2 is proportional to the amount of jitter. Therefore,
The width of the output pulse of the NAND gate 46 corresponds to the amount of jitter in the input data as a whole. This pulse is compared with a pulse output from the monostable multivibrator 48 with a width corresponding to the threshold value. The output pulse of the monostable multivibrator 48 is inverted by an inverter 52 (see (C) in the figure) and input to a NAND gate 50. And this NAND gate 50
Then, the detected jitter amount of the input data is compared with the threshold value. First, as shown at times TI to TJ in the figure, if the pulse width indicating the amount of jitter in (A) is shorter than the pulse width of the threshold shown in (B) in the figure, the amount of jitter in the input data is It is determined that the signal quality is within the acceptable range, and the NAN
There is no output of D game) 50 (see (D) in the same figure). On the other hand, as shown at time TK-TL in the same figure, if the pulse width indicating the amount of jitter in the figure (A) is longer than the pulse width of the threshold shown in the figure (B), the jitter of the input data It is determined that the amount exceeds the allowable range in terms of signal quality, and N
A pulse having a width corresponding to the amount exceeded is output from the AND gate 50 (see (D) in the same figure). As described above, in the jitter detection circuit 20 (see FIG. 1),
The amount of jitter included in the input signal that is greater than the allowable range is detected, and a detection pulse signal is output. Although not shown, in the above jitter detection operation, the control signal supplied from the signal detection circuit 22 has a logic value of "H". That is, it is performed during the preamble period (see Figure 16.17). Next, the overall operation of the first embodiment configured as described above will be explained. The signal received by the high frequency receiving section 10 is supplied to the intermediate frequency converting section 12, where the frequency is converted from, for example, an 800 MHz band to an IF band of 455 KHz. The converted intermediate frequency signal is demodulated into a baseband signal in the demodulation section 14, and further passed through the low-pass filter 1.
6, unnecessary band noise is removed and the signal is supplied to a comparator 18 where it is binarized. This binarized signal is input from the comparator 18 to the jitter detection circuit 20. The jitter detection circuit 20 detects jitter components based on the input binary signal. On the other hand, the signal detection circuit 22 detects that the voltage is at the reception level based on the input signal from the high-frequency receiver 10, and further detects the jitter of the control signal that has the logical value rHJ for a period corresponding to the preamble. It is output to the circuit 20. In the jitter detection circuit 20,
A detection signal is output only while this control signal is rHJ. That is, if the amount of jitter in the received signal exceeds a specified value during the preamble period, it is determined that the signal quality is poor, and a detection signal is output from the jitter detection circuit 20. On the other hand, if the amount of jitter does not exceed the specified value during the preamble period, it is determined that the signal quality is good, and no detection signal is output. As described above, according to the first embodiment, the signal quality is determined by detecting the amount of jitter in the pulse signal included in the preamble period of the input data, so even if the signal quality is affected by external noise etc. It also becomes possible to accurately judge signal quality. In addition, since it is configured with a logic circuit, there is no need for troublesome adjustments or compensation for temperature characteristics.
Furthermore, it is possible to reduce the scale of the two circuits, which can be easily integrated into an LSI. There are also effects such as expected cost reduction. <Example 2> Next, Example 2 of the present invention will be described with reference to FIGS. 6 to 8. The basic configuration of this second embodiment is as follows:
This is the same as in Example 1 above. In the first embodiment, the signal quality is determined based on whether the jitter amount of each input data exceeds a specified value. However, with this judgment method,
Since the jitter varies in a probability distribution manner, it includes an uncertain element. To explain specifically, S/N 20dB
When set as the threshold value for signal quality,
It is impossible to definitively determine that the quality is good when the S/N is 21 dB and the quality is poor when the S/N is 20 dB. Then, as shown in graph LA in FIG. 6, S/N20d
B or more is 100% good quality, S/N 17 dB is 50% good quality, S/N 14 dB is 100% poor quality, and a certain spread occurs in quality judgment. Depending on the device, there is a requirement to minimize the spread of such determinations. Example 2 answers this need. FIG. 7 shows the configuration of the main parts of the second embodiment. In the figure, the signal detection circuit 22 of FIG. 1 is connected to the terminal T1.
The output side of Figure 2 is connected to the terminal T2.
The output side of the ND gate 46 is connected. These terminals Tl' and T2 are connected to an AND gate 52 operated by two people.
are connected to the input side of each. Further, the terminal T3 to which the clock signal is input is connected to the output side of the AND gate 52 as well as to the input side of a two-manual AND gate 54. The output side of this AND gate 54 is connected to the input side of a counter 56, and the output side of this counter 56 serves as an output terminal T4 for a flag signal indicating signal quality. Next, while referring to the time chart of FIG. 8, Example 2
The operation will be explained. First, the signal supplied from the signal detection circuit 22 is a window indicating the preamble period as described above (see (A) in the same figure). On the other hand, N.A.
The signal supplied from the ND gate 46 is a pulse signal corresponding to the amount of jitter (see (B) in the same figure). Therefore, A
The output of the ND gate 52 becomes a jitter detection pulse signal during the preamble period, as shown in FIG. On the other hand, the AND gate 54 performs a logical AND operation with the clock pulse (see (D) in the same figure), and
The signals shown in E) and (F) are now output to the counter 56. The counter 56 counts the input clock pulses, and when a preset count is reached, a flag indicating poor signal quality is output to the output terminal T4. That is, since the number of clock pulses corresponds to the width of the pulse signal indicating the amount of jitter, the degree of the amount of jitter is determined from the count number. In other words, since the quality of the signal is judged based on the integral amount obtained by integrating the pulse width of the pulse detected by the NAND gates 4 and 6 during the preamble period, the uncertainty of the judgment is reduced. become. Therefore, the distribution of determination probabilities in this embodiment is as shown in the graph LB in FIG. 6, and the spread of determination is favorably improved. <Example 3> Next, Example 3 of the present invention will be described with reference to FIGS. 9 to 11. FIG. 9 shows the overall configuration of the third embodiment. In the figure, a low-pass filter 16
The output side of is connected to one input side of the noise component detection circuit 58, and the output side of the signal detection circuit 22 is connected to the other input side. That is, compared to the embodiment described above, the configuration is such that a noise component detection circuit 58 is connected instead of the jitter detection circuit 20. The noise component detection circuit 58 has a configuration as shown in FIG. In the figure, the signal from the low-pass filter 16 is input to the terminal T5, and the signal from the signal detection circuit 22 is input to the terminal T6. The terminal T5 is connected to the input side of the 1-bit delay circuit 60.
The output side of the adder 62 is connected to the input side of the adder 62 together with the terminal T5. The output side of the adder 62 is a comparator 64
is connected to one input side of the , and the other input side is connected to the
A power supply 66 that provides a threshold voltage serving as a comparison reference is connected. The output side of this comparator 64 and the terminal T6 are respectively connected to the input side of a two-man power AND gate 68, and the output side thereof is connected to the output terminal T7. Next, the operation of the noise component detection circuit 58 will be explained with reference to the time chart of FIG. For example, the baseband signal of the low-pass filter 16 is
Assume that the situation is as shown in FIG. Then, since the baseband signal during the preamble period has a fixed pattern of rHJ and rLJ, the output of the 1-bit delay circuit 60 becomes inverted as shown in FIG. 3B. When these are added in the adder 62, the signal component is canceled and the noise component is extracted (see Fig.
See C). The output of this adder 62 is the output of the comparator 6
4, where it is compared with a threshold voltage of power supply 66. As a result, when the noise component exceeds the threshold voltage level S1, a detection pulse is output (see (D) in the same figure). These detection pulses are input to AND gate 68. A control signal indicating a preamble period is input to the low input terminal of the AND gate 68. Therefore, the AND gate 68 outputs a noise detection pulse included in the preamble period. When there is a lot of noise, the number of detected pulses also increases, and this is used to determine whether the signal quality is good or bad. Next, the overall operation of the third embodiment as described above will be explained. The signal received by the high frequency receiving section 10 is supplied to the intermediate frequency converting section 12, where the signal is frequency converted to an intermediate frequency band. The converted intermediate frequency signal is sent to the demodulator 14
The signal is demodulated into a baseband signal, and noise in unnecessary bands is removed by a low-pass filter 16. This signal is input from the low-pass filter 16 to the noise component detection circuit 58. In this noise component detection circuit 58,
Noise components are detected based on the input signal. On the other hand, the signal detection circuit 22 detects that the voltage is at the receiving level based on the input signal from the high frequency receiving section 10, and furthermore, a control signal whose logic value is "H" for a period corresponding to the preamplifier is generated. Jitter detection circuit 20
is output to. The noise component detection circuit 58 outputs a detection signal only when the control signal is rHJ. That is, if the noise component of the received signal exceeds a specified value during the preamble period, it is determined that the signal quality is poor, and a detection signal is output. Note that the above explanation is for the case where the preamble data of the received signal is a repetition of logical values rHJ and rLJ (see FIG. 17(C)). However, the preamble data is a series of rHJs with logical values. Alternatively, in the case of a series of "L"s (see (A) and (B) in the same figure), the fluctuation element of the received signal during the preamble period is only the noise component. Therefore, noise component detection is performed at terminal T
5 may be directly input to the comparator 64, and the circuit configuration is simplified compared to the case described above. As described above, according to the third embodiment, the signal quality is determined by detecting the noise component of the pulse signal included in the preamble period of the input data, so even if the signal quality is affected by external noise etc. It also becomes possible to accurately judge signal quality. <Example 4> Next, Example 4 of the present invention will be described with reference to FIGS. 12 and 13. The basic configuration of this fourth embodiment is the same as that of the third embodiment. In the third embodiment, signal quality is determined based on whether the noise component of input data exceeds a specified value. However, in this judgment method, since the noise varies in a probability distribution manner, it includes an uncertain element, and as in the first embodiment, a spread occurs in the quality judgment. This Example 4 is
This is to minimize the spread of such judgments. FIG. 12 shows the configuration of the main parts of the fourth embodiment. In the figure, the output side of the adder 62 of FIG. 10 is connected to the terminal T7, and the output side of the signal detection circuit 22 of FIG. 9 is connected to the terminal T8. Terminal T7 is connected to the input side of a full-wave rectifier circuit 70, and the output side of this full-wave rectifier circuit 70 is connected to the input side of a Miller integrator 72. Miller integrator 72 is connected to high gain amplifier 74 . amplifier 74
The charge-hold capacitor 78 is connected in parallel with a resistor 76° amplifier 74 connected to the inverting input side of the amplifier 74, and the non-inverting input side of the amplifier 74 is grounded. Further, a switch 80 whose opening/closing is controlled by an input signal at a terminal T8 is connected in parallel to the capacitor 78. That is, during the preamble the switch 80
is turned off, and integration by the mirror integrator 72 is performed. The output side of this Miller integrator 72 is connected to one input side of a comparator 82, and the other side is connected to a voltage 84 that provides a threshold voltage for comparison. The output side of this comparator 82 serves as a signal quality detection output. Next, the operation of this embodiment will be described with reference to the time chart of FIG. 13. The adder 62 outputs, for example, a noise component as shown in FIG. This noise component is rectified by a full-wave rectifier circuit 7°, and the rectified signal (see (B) in the same figure) is supplied to a mirror integrator 72. Here, the control signal input to the terminal T8 becomes a logical value rHJ during the preamble period (see (C) in the same figure), and the switch 80 is turned off. Therefore, the mirror integrator 72 starts the integration operation at the beginning of the preamble period rJIJ, and the noise component is integrated, so that the integrated output increases (see (D) in the same figure). This integral value is then compared with the threshold voltage S2 of the power supply 84 in the comparator 82, and when the integral value exceeds the threshold voltage, the output of the comparator 64 changes from the logical value "L" to rHJ, which indicates a signal quality defect. It will be output as a detection signal shown in the figure ((
(See E). Note that this detection signal returns to the logical value rLJ when the control signal at the terminal T8 becomes the logical value rLJ and the switch 80 becomes ○N, or in other words, at the end of the preamble period. As described above, according to this embodiment, the noise component is integrated and the signal quality is determined based on the integrated value, so that the uncertainty in the determination is reduced. Therefore, the distribution of determination probabilities in this example is the graph L in FIG.
As shown in B, the spread of judgment is improved. <Example 5> Next, Example 5 of the present invention will be described with reference to FIGS. 14 and 15. In the embodiment described above, the signal quality is detected based on the preamble data provided at the beginning of the packet data. However, the reception environment of a wireless modem or the like may change while the packet continues. In the above embodiment, even if the reception environment changes during the data period and the signal quality deteriorates, as long as the signal quality is determined to be good during the preamble period, the entire packet is determined to be of good quality. become. By the way, an error detection code is generally added to packet data, and this is used to detect errors before the end of the packet. When an error is detected after the end of the packet, a retransmission command is sent to the transmitting side, and the data is retransmitted. Therefore, even if the signal quality deteriorates in the middle of data, incorrect data will not be used. However, with this method, data errors cannot be detected until the end of the packet. Therefore, especially when the packet length is long, data transmission efficiency is extremely deteriorated. In order to increase transmission efficiency, the most effective method is to promptly detect deterioration in signal quality without waiting for the end of a packet and immediately issue a transmission command, as well as to stop transmission and retransmit the data. This embodiment responds to such a request. FIG. 14 shows the main parts of this embodiment. In the figure, terminal T9 is connected to the signal detection circuit 22 shown in FIG.
Control signals are input from
The reception level voltage outputted from the high frequency receiving section 10 shown in FIG. 1 is input to the terminal TIO. Terminal T10 is set to ○N by the signal input to terminal T9. It is connected to the input side of a low-pass filter 86 via a switch 84 that is controlled to be turned off. The low-pass filter 86 has resistors 88 . It consists of a capacitor 90, the output of which is connected to the input of a high input impedance, non-inverting amplifier 92. The output side of the amplifier 92 is connected to one end of a resistor 94, and the other end of this resistor 94 is connected to a resistor 96 whose one end is grounded.
and one input side of the comparator 98, respectively. That is, the output of the amplifier 92 is voltage-divided by resistors 94 and 96 and input to the non-inverting input side of the comparator 98. A terminal TIO is connected to the inverting input side of the comparator 98.
8 outputs a signal quality detection signal in the data section. Next, the operation of the fifth embodiment will be described with reference to the time chart of FIG. 15. Note that the determination of signal quality in the preamble period is performed according to the second embodiment described above, for example, the first embodiment. The reception level voltage (see (B) in the same figure) output from the high frequency receiving section 1o is applied to the switch 84 from the terminal TIO. The opening/closing and control of this switch 84 is performed by a control signal of the signal detection circuit 22 (see (A) in the same figure) applied to the terminal T9. Therefore, switch 8
4 is ON during the preamble period, and the reception level voltage is supplied to the low-pass filter 86. The signal whose fine fluctuations have been absorbed by the low-pass filter 86 is supplied to the amplifier 92. Next, when the preamble period ends, switch 84 is turned OFF.
Becomes FF. Therefore, the reception level voltage at the end of the preamble period is sampled and held in the capacitor 90, and this sampled voltage is amplified by the amplifier 92 and output (see (C) in the same figure). This voltage is divided by a voltage divider formed by resistors 94 and 96 and input to a comparator 98. The received level voltage is directly applied to this comparator 98. As a result, the comparator 98 compares the reception level voltage at the end of the preamble with the reception level voltage in the data section after time TM. In the illustrated example, the reception environment is changing at time TN of the data section. This reception level voltage is the resistance 94.9
When the value of 6 is Rly R2, R2 of the sample voltage
/(R1+R2) times or less, comparator 9
The output of 8 is inverted from the logical value "H" to "L" (see (D) in the same figure). As a result, the signal quality during the data period is determined to be poor, and signal quality detection is performed in response to changes in the reception environment. Note that the sample voltage is weighted by resistor voltage division and the comparator 9
The reason for performing the comparison using 8 is to prevent the comparator 98 from malfunctioning due to small fluctuations in the received level voltage. As described above, according to this embodiment, even if the reception environment of a wireless modem or the like changes while packets are continuing, signal quality deterioration is immediately detected by the non-fixed pattern part quality detection means shown in FIG. . Therefore, even before the end of a packet, a retransmission command can be issued when the signal quality deteriorates, and transmission can be stopped and retransmitted quickly, making it possible to significantly improve transmission efficiency. Other Examples> Note that the present invention is not limited to the above embodiments. For example, the circuit configuration can be modified in various ways to achieve the same effect, and these modifications are also included in the present invention. Furthermore, although the above embodiments are cases in which the present invention is applied to packet data transmission, it is applicable to various data transmissions as long as the present invention has a fixed data pattern.

【Effect of the invention】

As explained above, the signal quality detection circuit according to the present invention has the following effects. (1) Since the jitter component or noise component in the fixed pattern portion of the input data is detected, the signal quality can be detected satisfactorily without being affected by external noise. (2) Since the signal quality is detected without waiting for the end of input data transmission, data transmission can be stopped and retransmitted quickly to improve transmission efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a signal quality detection circuit according to the present invention, FIG. 2 is a block diagram showing main parts of the first embodiment, and FIG.
5 to 5 are time charts showing the effects of the first embodiment, and FIG.
7 is a block diagram showing the main parts of the second embodiment, FIG. 8 is a time chart showing the action of the second embodiment, FIG. 9 is a block diagram showing the third embodiment, and FIG.
is a block diagram showing the main parts of the third embodiment, FIG. 11 is a time chart showing the action of the third embodiment, FIG. 12 is a block diagram showing the main part of the fourth embodiment, and FIG. 13 is a time chart showing the action of the fourth embodiment. Chart, FIG. 14 is a configuration diagram showing the main parts of Example 5, FIG.
5 is a time chart showing the operation of the fifth embodiment, FIG. 16 is an explanatory diagram showing the structure of general packet data, and FIG. 17 is an explanatory diagram showing the form of preamble data. 10... High frequency receiving section, 12... Intermediate frequency converting section,
14... Demodulation section, 16... Low pass filter, 18
. . . Comparator, 20 . . . Jitter detection circuit (jitter detection means), 22 . . . Signal detection circuit, 58 . . . Noise component detection circuit (noise component detection means).

Claims (4)

[Claims] (1) A signal quality detection circuit for detecting the signal quality of data having a fixed pattern portion, comprising a jitter detection means for detecting jitter in the data of the fixed pattern portion and determining whether the signal quality is good or bad based on the degree of jitter. A signal quality detection circuit characterized by: (2) In a signal quality detection circuit that detects the signal quality of data having a fixed pattern portion, a jitter detection means is provided that detects jitter in the data of the fixed pattern portion and integrates the jitter to determine whether the signal quality is good or bad. A signal quality detection circuit comprising: (3) A signal quality detection circuit for detecting the signal quality of data having a fixed pattern portion, comprising noise component detection means for detecting a noise component in the data of the fixed pattern portion and determining whether the signal quality is good or bad based on the degree of the noise component. A signal quality detection circuit featuring: (4) In a signal quality detection circuit that detects the signal quality of data having a fixed pattern part, noise component detection detects a noise component in the data of the fixed pattern part and integrates the noise component to determine whether the signal quality is good or bad. A signal quality detection circuit comprising means for detecting signal quality. (5) In the signal quality detection circuit according to any one of claims 1 to 4, the quality of the signal is determined by comparing the carrier levels of the fixed pattern part and the non-fixed pattern part of the transmitted data. A signal quality detection circuit comprising non-fixed pattern portion quality detection means.