JPH04192022A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the processing efficiency due to the wait for the use of a data transfer bus by providing a signal line to the bus in order to instruct each high speed memory device to prefetch the contents of the data on a low speed shared memory device. CONSTITUTION:A data transfer bus 6 is provided with a data prefetch signal line 7. When the latest data is not present on a 1st high speed memory device 3, a 1st CPU 1 requests a low speed shared memory device 5 for the data. Thus the relevant data is read out of the device 5 and sent to the device 3 via the bus 6. At the same time, the CPU 1 activates the line 7 and requests the updation of the data stored in a 2nd high speed memory device 4. The device 4 reads the data on the same address line out of the device 5. Thus it is possible to omit a process where a 2nd CPU 2 has an access to the device 5. Then the number of times of the utilization of the bus 6 is reduced and the holding time is shortened. Thus, the data processing efficiency is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a multiprocessor system having a plurality of sets including a central processing unit and a high-speed memory device for temporarily storing data recently used by the central processing unit. The present invention relates to a data processing device.

(Prior Art) FIG. 3 is a schematic diagram showing a conventional data processing device, in which 1 is a first central processing unit (hereinafter referred to as the first CPU).
, 2 is a second central processing unit (hereinafter referred to as second CPU)
, 8 is a first high-speed memory device that temporarily stores data recently used by the first CPU, 4 is a second high-speed memory device that temporarily stores data recently used by the second CPU 2,
5 indicates a low-speed shared memory device. The low-speed shared memory device 5 and the high-speed memory devices 3 and 4 are connected by a data transfer bus 6.

Figure 4 is 1. It is a schematic diagram of the second high-speed memory device 8.4, in which a directory section 11 stores directory information of data, and a data memory section stores data itself! 2, and tag information 13, valid bits 14, and dirty bits 15 are stored in the directory section AE.

The tag information 13 is a block number indicating in which position in the low-speed shared memory device 5 each data in the data memory section 12 is stored. Further, the valid bit 14 indicates the validity of the tag information 13, and when it is "1", it is valid, and when it is "0", it is invalid.

Furthermore, dirty bit 15 indicates the latestness of tag information,
“1” indicates the latest, and “O” indicates not the latest.

This valid bit 14. The combination of dirty bits 15 causes the first . It is adapted to represent three states of data stored in the second high speed memory device 8.4.

(2) When the valid bit 14 is "0", the data in the data memory section 12 is invalid.

(2) When the valid bit 14 is "1" and the dirty bit is "0", the data in the data memory section 12 is valid and matches the data in the low-speed shared memory device 5.

(2) When the valid bit 14 is "1" and the dirty bit 15 is "1", the data in the data memory unit 12 is valid and newer than the data in the low-speed shared memory device 5.

The operation of such a data processing apparatus will be explained with reference to the flowchart shown in FIG.

FIG. 5 is a flowchart showing the read procedure of a conventional data processing device.

When the first CPUI inputs data address information to the first high-speed memory device 3 in order to read the latest data from the high-speed memory device 3, the first high-speed memory device 8 checks whether the corresponding data is stored or not. Perform a search, and as a result of the search, tag information 1 that matches the address information of the requested data
3 exists and the corresponding valid bit 14 of the first high-speed memory device 8 is “1”, the corresponding data in the data memory section 12 of the first high-speed memory device 8 is the first
is read out to CPUI 1.

On the other hand, as a result of the search, if the tag information 13 that matches the information input from the first CPUI does not exist in the first high-speed memory device 8, or if the corresponding valid bit 14 of the first high-speed memory device 3 is “ If the value is 0'', a reading error occurs (step 11).

If the latest data does not exist in the data memory section 12 of the first high-speed memory device 3, the data is requested from the low-speed shared memory device 5. If the latest data exists in the low-speed shared memory device 5, this latest data is read from the low-speed shared memory device 5 to the first high-speed memory device 3 via the data transfer bus 6 (step 512). As a result, the data stored in the data memory section 12 of the first high-speed memory 3 matches the data in the low-speed shared memory device 5, and the block number is written in the corresponding tag information 13 of the first high-speed memory device 3. Also, the corresponding valid
Bit 14 becomes "1#" and dirty bit 15 becomes "0".

When the latest data is stored in the data memory unit 12 of the first high-speed memory device 8, the first CPU should read the data again (transfer the corresponding address information to the first high-speed memory device 3).
Output to. When address information is input, the first high-speed memory device 3 performs a search to see if the corresponding data is stored, and tag information 1 that matches the requested address information.
3 exists, the corresponding data in the data memory section 12 is read out to the first CPUI and becomes a hit (step 513).

Subsequently, the CPU 2 of 9Js2 similarly requests the second high-speed memory device 4 to read data, and when the data address information is input to the second high-speed memory device 4, the second
The high-speed memory device 4 searches whether the corresponding data is stored. If the tag information 13 that matches the address information of the requested data exists and the second high-speed memory device 4
If the corresponding valid bit 14 of is 1", the corresponding data in the data memory section 12 of the second high-speed memory device 4 is read out, and as a result of the search, the first CPU
Tag information 13 that matches the address information input from I
does not exist in the second high-speed memory device 4, or
The corresponding valid bit 14 of the high-speed memory device 4 is “0”.
”, a read error occurs (step 514).

If the latest data does not exist in the data memory section 12 of the second high-speed memory device 4, the data is requested from the low-speed shared memory device 5. If the relevant data is stored in the low-speed shared memory device 5, the data is read from the low-speed shared memory device 5 to the second high-speed memory device 4 via the data transfer bus 6 (step 515). When the data is read into the second high-speed memory device 4, the block number is written in the tag information 13, the valid bit 14 becomes "1", the dirty bit 15 becomes "0",
The second CPU 2 issues a read request to the second high-speed memory device 4 again, and in the process described above, the latest data is read out and becomes a hit (step 816).

[Problem to be solved by the invention]

By the way, in the conventional device as mentioned above, multiple CP
When U sequentially reads data from the same address line of the low-speed shared memory device 5, the data transfer bus 6 is sequentially used multiple times (twice in the conventional device described above). When using the data transfer bus, the second CPU 2 will be on standby during that time, so
There is a problem in that when the data transfer bus 6 is used many times, a decrease in processing efficiency is unavoidable.

The present invention has been made in view of the above circumstances, and its purpose is to reduce the number of times each CPU uses the data transfer bus, and to prevent a decrease in processing efficiency due to waiting for the use of the data transfer bus. The purpose of the present invention is to provide a data processing device according to the present invention.

[Means to solve the problem]

The data processing device according to the present invention includes a data transfer bus with a signal line for causing each high-speed memory device to prefetch the data contents of the low-speed shared memory device.

[Effect]

According to the present invention, when a plurality of central control units sequentially read data from the same address line of the low-speed shared memory device, the data of the low-speed shared memory device is
When the data is read into one high-speed memory device, the activation of the signal line causes the same data to be read into other high-speed memory devices almost simultaneously prior to a read request from the central control unit.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a schematic diagram of a data processing device according to the present invention. In the figure, 1 is the first central control unit (hereinafter referred to as the first CP).
2 is the second central control unit (hereinafter referred to as the second CP).
), 3 is a first high-speed memory device for temporarily storing data recently used by the first CPU, and 4 is a second CPU
A second high-speed memory device temporarily stores data recently used by U2, and 5 indicates a low-speed shared memory device.

a first CPUI, a first high-speed memory device 3, and a second CPUI;
The CPU 2 and the second high-speed memory device 4 are capable of mutually transmitting and receiving data, while the first high-speed memory device 3. Data can be sent and received between the second high-speed memory device 4 and the low-speed shared memory device 5 via a data transfer bus 6.

In the device of the present invention, the data transfer bus 6 is provided with a data prefetch signal line 7. The signal line 7 is the first. is connected to the second CPUI, 2, and the first CPUI. It is connected to a second high speed memory device 8.4 and to a low speed shared memory device 5.

1st. The second high-speed memory devices 3.4 each include a data directory section 11 and a data memory section 12 as shown in FIG. 2, as in the conventional device shown in FIG. Tag information 13. Valid
Bit 14. Dirty bit 15 is stored. The tag information 13 is a block number indicating which position in the low-speed shared memory device 5 the data in the data memory section 12 of the high-speed memory devices 3 and 4 corresponds to, and the valid bit 14 is the tag information. Furthermore, the dirty bit 15 represents the validity of the tag information 13, and the currency of the tag information 13, respectively, in the same manner as in the conventional device.

Therefore, in such an apparatus of the present invention, the first CPU
reads the latest data from the first high-speed memory device 3,
Next, the operation of the second CPU 2 to read the same data from the second high-speed memory device 4 will be described with reference to the flowchart shown in FIG.

First, when the first CPUI inputs data address information to the first high-speed memory device 3 to read the latest data, the first high-speed memory device 3 searches to see if the corresponding data is stored. As a result of the search, if tag information 13 that matches the address information of the request data exists, in other words, the corresponding valid/
When the bit 14 is "1", the corresponding data in the data memory section 12 is read out.

On the other hand, as a result of the search, if the tag information 13 that matches the address information of the requested data does not exist, in other words, if the corresponding valid bit 14 of the first high-speed memory device 3 is "0", a reading error will occur ( Step SL).

In this way, the data memory section 1 of the first high speed memory device 3
If the latest data corresponding to 2 does not exist, the first CPU
I requests data from the low-speed shared memory device 5.

If the corresponding data is stored in the low-speed shared memory device 5, the data is read into the first high-speed memory device 3 via the data transfer bus 6 (step S2), and the tag in the first high-speed memory device 8 is read. The block number is written in the information 13, and the corresponding valid bit 14 is 1'',
Dirty bit 15 becomes "0".

At the same time, the first CPUI activates the data prefetch signal line 7 and requests updating of the data on the same address line of the second high-speed memory device 4.

As a result, the second high-speed memory device 4 reads data on the same address line from the low-speed shared memory device 5 (step S3), and as a result, the block number is written in the tag information 13 in the second high-speed memory device 4 as well. The corresponding valid bit 14 becomes "1" and the dirty bit 15 becomes "0".

When the data is read into the first high-speed memory device 3, the first CPUI reads and hits the latest data in the process described above (step S4).

Subsequently, the second CPU 2 requests the second high-speed memory device 4 to read the same data. When the second high-speed memory device 4 receives data address information, it searches to see if the corresponding data is stored.

As mentioned above, when the first CPUI makes a read error, the data prefetch signal line 7 is activated so that the data from the low-speed shared memory device 5 is transferred to the second high-speed memory device 8 almost simultaneously with the reading to the first high-speed memory device 8. Since it has already been read into the high-speed memory device 4, there is tag information 13 that matches the input address information, and the corresponding valid bit 14 of the second high-speed memory device 4 is “1”. Therefore, the corresponding data in the data memory section 12 of the second high-speed memory device 4 is read out, that is, it is hit (step S5).

Therefore, the second CPU 2 uses the low-speed shared memory device 71.
5 is omitted, the data transfer bus 6 is not used accordingly, and the number of times it is used is reduced accordingly.

Although the above-mentioned embodiment describes the case where two sets of CPUs and high-speed memory devices are provided, the case is not limited to this, and any number of CPUs may be used.
Of course, the present invention can also be applied to cases with PUs and high-speed memory devices.

〔Effect of the invention〕

As described above, in the device of the present invention, since the data transfer bus is provided with a signal line for causing each high-speed memory device to pre-fetch data from the low-speed shared memory device, the number of times the data transfer bus is used is significantly reduced, and The present invention has excellent effects, such as reducing burden, shortening standby time, and improving data processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the device of the present invention, FIG. 2 is a flowchart showing the processing procedure of the device of the present invention, FIG. 3 is a schematic diagram of a conventional device, FIG. 4 is a schematic diagram of a high-speed memory device, and FIG. 5 is a schematic diagram of a high-speed memory device. 2 is a flowchart showing a processing procedure of a conventional device. 1...First CPU 2...Second CPU S
. . . First high-speed memory device 4 . . Second high-speed memory device 5 . Indicates the same or equivalent part. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure Procedure Amendment (Voluntary) 1991, Month 4B 2, Name of Invention Data Processing Device 3, Person Making Amendment Case Related Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, agent address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (
Contact information: 03 (3213) 3421 Patent Department) 5, “Detailed Description of the Invention” column 6 of the specification subject to amendment, Contents of the amendment (11 “Department Directory Department 1” on page 2, line 14 of the specification)
1J should be corrected to read "Directory section 11." (2) In the first line of page 11 of the specification, the phrase "If tag information 13 exists, in other words, the first" has been replaced with "tag information 1."
3 exists and is the first." (3) From page 11, line 6 to line 7 of the specification, “
If the tag information 13 does not exist, in other words, it is the first," is corrected to read, "If the tag information 13 does not exist, or in other words, the first."that's all

Claims (1)

[Claims] (1) comprising a plurality of central processing units, a plurality of high-speed memory devices arranged corresponding to each central processing unit, and a low-speed shared memory device commonly used by the central processing units,
In the data processing device, data is transmitted and received between each of the high-speed memory devices and the low-speed shared memory device via a data transfer bus. A data processing device characterized in that a data transfer bus is provided with a signal line for data prefetching.