JPH041846A - Information processing system - Google Patents

Abstract

PURPOSE:To attain various complicated types of learning by providing an output part which outputs the computing result when the computing result of an arithmetic part exceeds the prescribed threshold value and then deciding the continuation of time of the output called the degree of significance based on the state values of both input and output parts. CONSTITUTION:A logic circuit element 1 is provided with an input part 3 where the weighing is applied to the input based on a weighing coefficient, an arithmetic part 5 where the input value given from the part 3 is computed and the state value of the part 3 is obtained, and an output part 7 where an output operation is carried out if the computing result of the part 5 exceeds the prescribed threshold value. The part 5 calculates the input value and sends it to the part 7. If the part 7 is ready to output the input value and the value received from the part 5 exceeds the threshold value, the part 7 performs an output operation and at the same time urges the part 3 carry out the learning. In this case, the degree of significance has the direct relation so that the internal energy value of the element 1 is outputted. Thus an actual element 1 is easily obtained. As a result, both parts 3 and 7 can be controlled and learned independently of each other. Then various types of learning are attained.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to an information processing method that performs information processing by propagating only significant information among logical operation results, and particularly relates to an information processing method that performs information processing by propagating only significant information among logical operation results. The present invention relates to a logic circuit that can realize a learning method in which the elements are also one element.

(Prior art) In conventional information processing systems, binary information such as "1", "0"
The main processing work was to encode information using binary values of ° and process the encoded information. In such information processing, both of the binary information of "11."0" have the same meaning (weight), and both "1" and "0" in the logical operation result are high-ranking. was being propagated to the process.

This was sufficient until information was imported from the outside into the logical system, but when processing the imported information internally,
Processing results are propagated to the final stage of processing. For this reason, as the processing content and amount of information increases, the processing becomes more complex, and the configuration becomes larger and more complicated, making it difficult to design the processing circuit.

Furthermore, in internal processing, in addition to correctly expressing information, it is necessary to process significant information, characteristic information, etc. obtained as a result of processing. This kind of processing is completely different from information representation, so it is difficult to use the logical product (AND) and logical sum (
It was unsuitable to be expressed using a pull operation expression such as OR).

In order to process information efficiently, it is necessary to suppress the propagation and processing of unnecessary information (unwanted information) as much as possible, and only propagate and process meaningful information. It becomes necessary.

Conventionally, when significant information is obtained as a result of information processing, processing is requested to the next stage processing circuit only when significant information is obtained. Conventionally, such a method has been carried out by a handshake method using human output of a request signal and an approval signal.

However, in such a system, it is extremely difficult to construct an information processing system that becomes more complex and larger in scale as the amount of processing information and processing contents increases.

Furthermore, in conventional threshold chain elements, the input section and the output section are not separated, making it difficult to implement a complex learning method. Conventional learning methods have selectively lowered the threshold value for the element that generated the output, or strengthened the input weighting coefficient.

(Problems to be Solved by the Invention) However, with this learning method, it has not been possible to actively strengthen elements that do not generate output but have potential. Therefore, it only passively accepts input patterns and performs learning according to the statistical distribution, so learning is just a name, but in reality it is simply storing statistical events on the circuit.

That is, conventional learning methods have selectively lowered the threshold value or strengthened the input weighting coefficient for the element that generated the output (He b b learning rule). However, with this learning method, it is not possible to actively strengthen elements that do not generate output but have potential, and learning ends up merely memorizing statistical events.

Another object of the present invention is to solve the above-mentioned problems.
The purpose of this is to separate the input section and output section and incorporate a control structure between them, which allows the learning of the input section and the learning of the output section to be separated, thereby creating a logic circuit that enables various complex types of learning. The goal is to provide the following.

Another object of the present invention is to provide a logic circuit that can implement a learning method in which the state value of the input section is also one element.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes an input section having a plurality of input terminals, an arithmetic section that performs a predetermined calculation using input values, and an output unit that outputs the calculation result when the calculation result in the calculation unit exceeds a predetermined threshold;
It is characterized in that the duration of the output, called significance, is determined based on the state value of the human power section and the state value of the output section.

Another feature of the present invention is that the degree of significance is determined by regarding the degree of significance as a projection value of a basis vector spanning a vector space, and performing calculations within the vector space.

(Function) The first feature of the present invention is that the element is separated into an input section and an output section, each having an independent state. Second, each operating characteristic can be changed through learning operations. These two components correspond to the fact that the event of receiving input and the event of producing output are two different things. Thirdly, by providing a function to suppress and control the output, it is possible to select an output event, and the learning of the output section can be controlled.

In the above configuration, the present invention makes it possible to configure a system with strong learning ability by configuring a learnable logic circuit using logic circuit elements as constituent elements. Since the suppression and learning of the output section and the suppression and learning of the input section can be performed separately and independently, versatile learning is possible.

That is, since the logic circuit element of the present invention can improve the sensitivity to human cover turns even for logic circuit elements that have not yet outputted, it is possible to actively incorporate input patterns. Due to this characteristic, it is possible to easily acquire the gazing mechanism inherent in living things.

(Example) First, before explaining the logic circuit according to the present invention, the information processing system which is the basis of the operation of the logic circuit according to the present invention will be explained with reference to FIGS. 1 to 6.

FIG. 1(a) is a schematic diagram showing the concept of the system in the information processing method.

In Fig. 1(a), this information processing method propagates only significant information in the information processing result to the next stage processing circuit, and propagates unnecessary information that becomes unnecessary during the calculation process to the next stage. First, processing at a later stage is not performed. That is, the processing outputs A, B, C of the first stage processing circuit
Among them, in the processing result of input information, for example, processing output A
When a significant result is obtained for C, the processing outputs A and C are treated as, for example, 1° level significant information, and only this significant information is output to the next stage processing circuit. Processing is performed on the significant information obtained, and if a significant result is obtained, the processing output is propagated to the next stage as significant information.In this way, only significant information can be submitted to the next stage of processing. Therefore, the processing circuit may focus only on significant information and process it.

Therefore, in order to construct a logic operation system that focuses only on meaningful matching results, we developed a logic circuit that performs a new pool operation process that expands information in the time direction, compared to the pool operation in the conventional logic operation system. will be introduced.

Since binary information is required to enable the pool operation, here, a significant result (significance information) is set to "1", and a meaningless result (significance information) is set to "0". Since "0" is meaningless information, it is assumed that "even if it is denied, it is meaningless information". Since negation is sometimes required in logical operations, we introduce a half-negation operation (NOT) that negates only the significant information "1", with negation limited only to the input terminal of the logic circuit. Therefore, the half-negation operation is Calculations are performed according to truth values as shown in FIG.

Also, since only the significant information "1" is propagated, the significant result lasts for a certain period of time and then becomes "0". Therefore, all new pool operation results are "1" after a certain period of time. In addition, the significant information “1” to be propagated is
” is input as is, or it is half negated at the input terminal to become “0” and input.

In a logic circuit that operates in this manner, the output value is "0°" except at the time when the calculation result becomes "1" and for a certain period of time after the calculation result becomes "1". Therefore, a storage circuit that holds this significant information and a transfer circuit that transfers the significant information to the storage circuit are required.

Therefore, by using such a logic circuit,
All arithmetic processing is processed in real time, and is performed between the input value and the half-negation of the input value, and is output to the next stage only when the output result is significant information of "1 degree," and "0" in the output result. ” is suppressed without being output to the next stage.

In addition, in such a logical processing system, all logical expressions include a negation operation and a logical product (AND) or a logical sum (OR).
) operations, so it is basically sufficient to have a logic circuit that performs such logical operations, but in practice other logic circuits may also be required. however,
The configuration can be expanded using essentially the same expansion methods.

Among the logic circuits described above, the AND circuit and the OR circuit operate according to the truth values shown in FIGS. 3 and 4. In FIGS. 3 and 4, A (t),
B (t) is the input value at time t, c (B is the output value for input values A and B at time t, and C (t-1) is the output value a certain time before time t. , C(t+D
t) is an output value after a certain period of time with respect to time t.

Let us now consider the case where these logic circuits are treated as threshold elements. That is, as shown in FIG. 1(b),
If 1 is set for five or more inputs out of n human power, 1 is output.

For example, if human power is A I and A 2, i-1 is 0
``If at least one of the elements A1 or A2 is true, it indicates that the logical expression A1 or A2 is true.Similarly, if i+=all, the function of and It can be analogized that when one input is 1, it is believed to be true and outputs 1.

3 and 4, the output value C(t) is
This is similar to the output value of an ND circuit or an OR circuit, but all output values become "0" before and after a certain time relative to time t, regardless of the input value.

In addition, "Oo" on the input side is obtained by negating "1" of the significant information propagated from the previous stage at the input end. °0" on the output side has no meaning and is used as the calculation result. Only the significant result "1" is propagated to the next stage.

In a logic system using such logic circuits, ■When and where is 1 propagated?

■Significant signal simultaneity.

■Intensity distribution of significance between significant signals.

or become important. Therefore, considering two-way information propagation instead of halving the significance of information, information transmission is realized as a result of the interaction of two-way information flows.

Therefore, information processing is executed by mutually controlling each other through this interaction. For example, as shown in FIG. 5, if the amount of information is represented by "-", the two information flows DI and D2 from A to B and from X to Y are controlled by each other, and DI and D2 are controlled by each other. After each piece of information in the flow is processed, significant information that has meaning is extracted as a feature, and the amount of information is reduced.

In such a logical processing system, all significance values are expressed as "1" and propagated, making it difficult to perform comparisons between a plurality of pieces of significant information or to diversify arithmetic processing.

Therefore, a measure of significance is needed. This measure is how much significance can be propagated to subsequent processing circuits. The quantity that realizes this property is the number of significant information "1" that information corresponding to a certain concept has, or the output duration of significant information "1" or the number of output lights, and such output frequency The degree of significance can be expressed by

By introducing such a degree of significance, input information can be ordered and input information can be controlled based on this ordering. In other words, information is in the process of being input and propagated to the next processing circuit, and the significance of that information, the significance of the relationships between pieces of information, and the new meaningful information that arises from the processing results of the information are important. Significant information is propagated to subsequent processing circuits.

In propagating such significant information, the selection of significant information is performed in each processing circuit based on the degree of significance. For example, with the number of significant information as the output frequency, information with a large number of significant information "1" is selected. In order to perform such a selection operation, an operator for calculating significance is required.

Assuming that this operator is C(z), Ctz), a wide variety of operators can be considered, but a simple example is the following expression. Assuming that the subscript of each human power is [C1z)-Σizi, zi is the degree of coincidence with respect to each human power 1i. For example, if the input information is "1011-", this input information is a reference pattern P stored in advance for calculating the significance level.
(for example, "1010"), and if the matched bit is set to "1°" and the mismatched bit is set to "0", 21 of the 1st bit (i-1) is "0", and the 2nd to 4th bits ( 22 to z4 in 1-2 to 4) are all “1”, and C
-3. In this way, the significance is calculated, and the one with higher significance is selected and propagated to the subsequent processing circuit. Note that in the significance calculation operation, the significance of information may be changed by learning.

In the operation of selecting significant information, since all the significant information becomes "O" after a certain period of time, the time point at which the significant information is outputted and the time point at which the manually inputted significant information is evaluated and selected must coincide. However, since it is difficult to propagate and process information at such timing, for example, as shown in FIG.
It has a recalculation instruction function that requests and instructs the preceding processing circuit to calculate significant information again. As a result, the previous stage processing circuit again selects significant information from the significant information held in the storage circuit according to instructions from the next stage, and outputs the selected significant information as a significant result to the next stage processing circuit again.

From the perspective of significance, the significance is developed in the time axis direction, so a bit string at a certain moment does not have an exact meaning. Significance has meaning in the integral value within a certain interval and the relative value between each component. The basic principle of a significant logic circuit is that the significance carried by each piece of information is aggregated to drive the next stage element.

Based on this, the basic construction method of decomposing the significance of information into each component and distributing it to each output light will be understood. The operation is basically considered to be a development of the projection operation that is familiar in mathematics. Therefore, unlike the pool algebra system, a system design method that ``directly converts a mapping on a vector space into a circuit'' can be realized by a significant logic circuit that introduces this significance as an expression quantity.

In a logic processing system including such a matching operation, the following may be considered as an example of a description in a specific design method of a logic circuit.

The literals are x, y, z, and the input part where X is input manually is l
x>, the output unit that outputs y is expressed as <y, and the matching operation between X and y is expressed as z-<xly>. Here, when X and y match, it means that z-1 holds true. Letting the operator be Op, a unary operation is expressed as Opl x>; a binary operation is expressed as 1x>0ply>, etc. Also, a circuit whose input is X, arithmetic processing is op, and output is y is <yl
opX〉 Here, the following relationship holds true for I>.

1-<0 0>-<1 1>0-<Ol1>-<1IO> Generally, information processing is a repetition of information determination and information processing. This determination is nothing but an information matching operation and evaluation of the results.

Here, the input cover turn is pl, the output cover turn is p2, and the mapping from input X to output y is f(x:piy:p2). The expansion of pl in the spatial direction is 10011011101>
It is expressed as a literal sequence like , and the expansion in the time axis direction is 1
100;111;101〉 and separated by “;”. This p
The operation of inputting l into X is written as <x l pl>.

If the operation sequence for f is fop, then f is <p21y><ylfoplx><xlpl>.

This description says, ``When the matching operation between X and pl is successful, f
When the operation of op is executed and the operation result becomes p2, p
2 is output.

for example, fop AND.

/*2 human power 1 output 1*/ pi -100; 01; 11; 10>;
/*4 clocks*/p 2 −〈0,
0; 0, 0; 1, 0: 0, 0/*8*1/
If you write a connection description as 2 clocks */, x>-1x><xlpl>;Y>-1y><y]ANDlx>;out>-1out><p21y>; Expand fop with a projection operator Then y><ylfoplx><xl=n+ al Pr
0J.

E+ a+ <p21Proj'lpl>:. The degree of significance can be decomposed as the projection value of each component, and the degree of significance can be easily extended to the feature space. If the significance of the input is E and the significance of the component is e, then E=(el,...
, en); @ Therefore, the operation of the significance quantity can be regarded as the rotation of a vector within the feature space.

Let the significance be El and E2. AN as a calculation of significance quantity
In addition to D and OR, the following operation f (El, E2) can be considered.

(1) Comparison: El-E2>TH→ Eout-El-E2; El-E2(TH→ no Eout; (2) Selection: El-E2>TH- Eout=E1; El-E2<TH→ Eout- E2; (3) Reinforcement: E1+E2>TH- Eout-E1+E2; (4) Gate: TH=OEl-"Through
gh; TH-HighE1→Inhibit - Complicated functional elements such as decoders and ALUs can be constructed by configuring the above basic operations. In order to put complex information on El and decipher it, it is necessary to be able to control TI (TI), but the same effect can be obtained by replacing E2.

Vectorize the input calculus and calculate X, Y, and its significance as E
shall be. A coupling matrix represents the connection relationship between input and output elements, and the matrix elements indicate the weights of the couplings.

[M] = l Y><X For the transformation relationship of significance, use matrix [M] and [E
(Y)] - [M] [E (X)] ; The initial matrix indicates the initial number of connections between elements, and it is assumed that the connection coefficient changes due to learning and becomes [M゛].

If diagonalized by this transformation, the significance level E (X
) is projected onto the base component, and E (Y) is obtained as an output. Therefore, the significance of input information can be constructed from the significance of each feature component.

Next, the flow of processing from In to Out will be considered using a neuron as a model.

Let lin, a> be an input circuit with human power in, a, let fI be an output circuit whose output is [, and let If><fl be the connection relation matrix of f. A circuit consisting of two stages in which the first stage outputs a single light is expressed by the following formula.% The meaning of this formula is that first, in and a are processed in the input stage,
is output. At the next stage, f is processed and OUT is output. Next, in order to control this flow, further substituting the processing circuits PL, P2, and the control signal U, ot>-at><ot Plu f><fpH
in, a>.

In this equation, if f is now significant due to P1, then P1 is executed, and if a more significant result is obtained, ot is output. This means that Pl.

This means that the program consisting of Pl has been executed.

Conversely, when f is insignificant, Pl is not executed and ot is not output. Pl and Pl are controlled by a control signal U in the opposite direction from in to out.

In this way, the two signals have a mutual relationship at PI and Pl, and influence each other.

Next, we will try to formulate a conditional branch. When multiple outputs are required due to Pl, a convention is used in which the sum is calculated for the same subscript i of ui and fi. This gives ot>-1ot><otl
P21ui, fi> Kuzono IpHin, a>.

Here, if ui-u and uj-not (u), then fi and fj have been selected depending on the value of U.

Similarly, if f i-f, f j-not (f), it is possible to control whether or not Pl acts on U.

These things can be achieved with conventional random logic circuits, and are not just a change in expression; they demonstrate the essence of data control. Here, if the error from the expected value is taken as U, it becomes a backward propagation method.

In this way, with this information processing method, information processing can be performed by focusing only on significant information, so even if the amount of information and processing content increases, the processing work can be significantly reduced and simplified. It becomes like this.

Next, the concept of logical processing according to the present invention that introduces the above-mentioned significance E (energy) will be described.

First, let's consider matching processing. The simplest comparison is to determine whether it is 1 or 0, which can be accomplished using the AND operator. The next more complex method involves ranking among multiple input signals. Furthermore, in a complex comparison calculation process, the number of 1's input at a certain time or the input frequency is convolved with the input frequency of the number of O's that are negated and input, and an output value is determined. Here, we define significance using a simple matching operation. Now, a bit-by-bit matching operation is performed on the storage data y and the input data X having the same bit width, and the number of equal bits is defined as the matching degree. The operation result for each bit is zi-<yilx
i>, the degree of coincidence is given as C(zl-Σizi.

Similar to threshold logic, when this C exceeds the threshold TH, an output value of 1 is obtained. Unlike the Boo 1 operation, the output of a significant logic circuit disappears after a certain period of time, so the significance level E can be defined as the duration of the 1 output within a certain time unit, or the output frequency of 1 within a certain time unit. I can do it. To simplify the problem, simply consider an element whose output is 1 for a period of significance E. Consider the following model in which significant logic elements are divided into input stage and output stage.

The degree of significance is related to the output energy EO of the output stage out of the internal energy of the element. Here, the difference between the internal energy and the potential around the element is defined as the output energy. Output begins when the output energy exceeds the threshold THOT, and stops when all the output energy is released. As a result of the calculation in the manual stage, input energy EIN is generated.

Various calculations can be considered at the input stage, or addition may be considered for simple weighting. When this energy value exceeds the threshold value THIN, the output starts, and the energy EO stored on the output side is released. After energy is released, calculations at the input end are prohibited until the output energy EO is stored (
refractory period). There is a damping mechanism at the input end, and if the human power energy EIN does not exceed the threshold THOT, the calculation result disappears after a certain period of time.

An example of programming this behavior is shown below.

<HP(IGT:(PROC>IGT4S(PT,CP
, CN, JO, J 1.10 , I 1. +2.13.
); <SIG>PT<0:3), CN, CP, Jj, Ij:
<INT>Pi-4, TH=3. EOT-1, EIN-
0,QO-8,Ql-8(SPART>IF EOT-)THTHEN EOT-EOT-(QO*5Tl(JO)+Ql*5T
I(Jl))/2IF EOT(<OTHEN E
OT-0:ENDIF;IF EOT)>THE
THENQO-QO+IF QO(<24 THE
N 5TI(JO)ELSE RO ENDIP・E
NDIP; ENDIF: IF EIN-<TI(T)IBIIIF EO
T>>THTl(EN EIN-(Pi*5Tl(If)-3TI(PT))/
4;ELSE EIN-OEOT-EOT+1:END
IF; IF EIN-<THTHEN N-EIN-1:ELSE EDT-EOT+EI
N:ENDIPIF TGT-IBOTHEN
IGT-IBO・ENDIFELSE IF EOT＞＞THE THEN IF IGT'-
IBI THEN IGT-IBI:IF If
THEN IF Pi<ku12 THEN P
i-Pi+1;ENDIFELSE IF Pi>>4
THEN PI-Pi-1:ENDIF:ENDIF
:ENDIP:EOT-ENT-2; ELSE EIN-0: EOT-0; ENDIF:E
NDIP.

This model can be easily implemented using MOS) run sisters and capacitors. The weight at the input end is set to MOS by EPROM.
This can be achieved by changing the drivability of the vehicle. Heb
As a result of a simulation given the learning rule b, the behavior was similar to that of a neural net using normal sigmoid elements. Operations such as competitive learning and error backpropagation models are also possible depending on how the elements are combined. The relationship between the digitization of coupling coefficients and element outputs and the convergence of learning is reported by Inomata et al. as follows.

(1) The coupling coefficient can be reduced to several bits, and the output can be reduced to one bit of 0 and 1. Also, a threshold function may be used instead of the sigmoid function.

(2) Modify the error propagation algorithm and use a minute constant instead of the first-order differential coefficient. In addition, the study results are summarized as conditions such as convergence to an optimal stable point.

General, Tendency, Proposal, “Study on reducing the number of bits in digital error backpropagation model”, IEICE Technical Report, NC89-4
1, pp. 51-56 (1989).

As reported in this model, since the output is digitized to 1.0, the convergence is poor and there is oscillation around the convergence point.

Furthermore, since the output changes from 1 to 0 after a certain period of time, the interpretation of the circuit operation will be slightly different. The output operation of each element is not synchronized, and the period of the element is related to the output energy, so it differs for each element, so the operation of the entire element group has to be quasi-periodic. Its operation is ergodic at first glance, and it is possible to construct a circuit that appears to follow all output patterns even if the same human power is continuously applied to the circuit. Able to configure circuits. In order to obtain a specific input/output relationship for the entire circuit, weighting at the input terminals of the elements alone is not sufficient; interaction between the elements is essential. When we examine the effect of adding a suppressive effect to the input, we find that if the suppressor is too strong, the system as a whole becomes less active, whereas if the suppressor is too weak, the system as a whole tends to be activated.

In fact, this tendency may be reflected in the fact that the proportion of inhibitory neurons among neurons in the brain remains within a certain range.

Methods for controlling this significance calculation include (1) varying the threshold value to change the activation level of the element; (2)
There are two possible ways to rewrite the stored data.

Dynamic control is performed using method (1), and method (2) is used for long-term changes corresponding to circuit changes.

In order to distinguish input signals related to the above control, those related to (1) are denoted by "()."

Items related to (2) are enclosed in “[]”.

<u, cl [mem], (thrl, thr2)i
l, i2. i3> When explicitly describing stored data to be compared with input data, surround the stored data with "#".

<u, cl#010:# [mem], (thrl.

thr2), il, i2. i3> Similarly, if the output data is written explicitly, <u, c#111#l#o10# [mem].

(thrl, thr2), il, t2. i3>.

A propagation pattern is generated with initial energy (initial significance), and a model is considered in which energy is exchanged with the information processing system while propagating within the system.

As a result of the system processing the pattern, the pattern is converted and a new pattern PJ is generated.

PJ-IP><Pj l int lpo>; The (significance level) energy of the pattern is expressed as E(PJ). Similarly, let the path of the pattern be W and the (significance) energy of the path be E (W). Similar to dynamical systems, a stable pattern on a stable path has constant energy (significance). Hereinafter, the (significance level) energy will be simply referred to as energy.

Next, a logic circuit according to the present invention will be explained with reference to FIGS. 7 to 10.

FIG. 7 is a configuration diagram of a logic circuit element embodying the present invention. The conventional element was comprised only of the input state value calculation section of the input section of the present invention and the learning rule.

As shown in FIG. 7, this logic circuit element 1 includes an input section 3 that weights human power using a coefficient, and an input section 3 that calculates input values from the human power section 3 to obtain a state value of the input section. . It has an arithmetic section 5 and an output section 7 which performs an output operation if the value from the arithmetic section 5 exceeds a threshold value.

The operation of this logic circuit is as follows.

(1) Find the value of the entire input from the input value and weighting coefficient and use it as the input state value.

(2) Find the next state from the current state of the human power unit 3 and the input state value and make a transition to the next state.

(3) If the state is in a learnable state, change the weighting coefficient of the input section 3.

(4) Next, send the input value to the calculation unit 5 and initialize the input state.

(5) The calculation unit 5 calculates the input value and sends it to the output unit 7.

(6) If the output unit 7 is in an output-enabled state and the value from the calculation unit exceeds the threshold value, perform the output operation. At the same time, the input unit 3 is prompted to learn.

(7) After output, return to the initial state and initialize the output state.

Since the significance level is directly related to the output of the internal energy value of the element, the actual element can be easily constructed. At the same time, the output value is limited to two values of 01, so U
LS I implementation is also possible.

FIG. 8 shows an example in which the logic circuit element 1 shown in FIG. 7 is implemented using a CMO3 circuit. The state values of the input section 3 and the output section 7 are obtained using parasitic capacitances jlci and Co of the drains of the MOS, respectively. The a state of the output section 7 is a flip-flop FF.
The channel width of the FF is changed so that the stored capacitance CO is discharged and returns to the initial state. The control circuit for controlling the state from the outside is omitted since it can be a circuit that simply charges and discharges the capacitance.

A logic circuit constructed by arranging the logic circuit elements 1 in multiple layers and wiring between each layer as shown in FIG. 9 also operates in a similar manner. The human signal is subjected to weighting processing and various calculations at each layer, and the significance of the signal is determined. The subsequent logic circuit element that receives an output with a certain degree of significance outputs a control signal to encourage the element at the tip of the comparison to learn. Alternatively, it is possible to scan the output state of the previous stage and instruct amplification of the output if necessary. Both of these types of control can be easily realized by simply controlling the state values of the input section or output section of the logic circuit element.

In order to realize a human-powered logic circuit, it is sufficient to increase the learning sensitivity of the human-powered part of the logic circuit element. That is, it is sufficient to control the state of the input unit so that it can easily transition to a learnable state, for example, by lowering the threshold value of the learnable state. Similarly, in order to realize an 8-power-oriented logic circuit, it is sufficient to increase the learning sensitivity of the 8-power portion of the logic circuit element. In an arithmetic-oriented logic circuit, considering that "arithmetic operation is an input/output relationship," it is sufficient that both the human power section and the output section have the same learning sensitivity. In this way, from the perspective of learning sensitivity,
It is possible to separate the functions of each layer and create three layers: a front section, a middle section, and a rear section. The learning sensitivity of the input section of the logic element is decreased from the front stage to the rear stage. On the contrary, the learning sensitivity of the output section improves from the front stage to the rear stage. By controlling the rate of change in sensitivity between the two, it is possible to easily control the ratio of each part.

Furthermore, as shown in Figure 10, by dividing the multi-layered logic circuit and changing the learning sensitivity and control method for each block, it is divided into an input section, a control section, and an output section, and more complex processing can be performed. It is also possible to construct a logic circuit for the basic unit of operation.

[Effects of the Invention] As described above, according to the present invention, since the status of the input section and the output section can be grasped separately, input values can be actively captured. Furthermore, since suppression and learning can be performed separately and independently for the input section and the output section, versatile learning is possible.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1(a) is a configuration block diagram showing the concept of an information processing method which is the basic concept of this invention, and FIG. 1(b) is a block diagram of the information processing method obtained by the information processing method shown in FIG. Figures 2 to 4 are diagrams showing the truth values of the logical operation circuit used in the processing circuit shown in Figure 1. Figure 5 is the flow of information processing in the processing method shown in Figure 1. 6 is a diagram showing one function of the processing circuit in the processing method shown in FIG. 1, FIG. 7 is a block diagram showing the configuration of an embodiment of the logic circuit element according to the present invention, and FIG. , a diagram showing a specific example of the logic circuit element shown in FIG. 7, FIG. 9 is a block diagram of a logic circuit configured by arranging the logic circuit elements shown in FIG. FIG. 2 is a block diagram of a circuit in which the multilayer logic circuit shown in the figure is structured and divided into a human power section, an arithmetic section, and an output section. 1... Logic circuit element 3... Human power section 5... Arithmetic section 7... Output section

Claims (2)

[Claims] (1) An input section with multiple input terminals, an arithmetic section that performs predetermined calculations using input values, and outputs the arithmetic result when the arithmetic result of this arithmetic section exceeds a predetermined threshold. An information processing method, characterized in that the duration of the output called significance is determined based on the state value of the input section and the state value of the output section. (2) The information processing method according to claim 1, wherein the degree of significance is determined by regarding the degree of significance as a projection value of a basis vector spanning a vector space and performing calculations within the vector space.