JPH04181808A - Phase comparator - Google Patents

Abstract

PURPOSE:To prevent leakage and radiation of noise to other circuit by synthesizing a noninverting output of a 1st logic circuit and an inverting output of a 2nd logic circuit and synthesizing the inverting output and the noninverting output of both the logic circuits and using the two synthesis signals as two input signals to a differential amplifier. CONSTITUTION:An in-phase spike component is generated to terminals U, D of ON/NOR gates 6, 7 and an opposite phase spike component is generated to terminals U', D' being opposite terminals of a balance output. Thus, the outputs at the terminals U, D' and the outputs at the terminals D, U' are synthesized to cancel the spike noise component. Since a signal not including the spike component is inputted to an amplifier 8, no noise component appears at an output terminal of a phase comparator 51. Thus, a signal with a level lower by the spike noise component, that is, only the required signal component appears at the output terminal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase comparator, and in particular to a digital P L
The present invention relates to a phase comparator used for L (Phase Locked Loop) and the like.

[Prior Art] A circuit diagram of a conventional phase comparator of this kind is shown in FIG. Fourth
As shown in the figure, the conventional phase comparator includes a first two-man powered NOR gate 1 whose input terminals are connected to a first input terminal R and a first output terminal U; The first S whose reset input terminal is connected to the output terminal of
A second two-power NOR whose input terminals are connected to the R flip-flop 2, the second input terminal V, and the second output terminal
a second SR flip-flop 4 whose reset input terminal is connected to the output terminal of the two-man powered NOR gate 3; and the output terminals of the first and second two-man powered NOR gates 1.3 and the first; The input terminal is connected to the output terminal of the second SR flipflop 2.4, and the output terminal is connected to the output terminal of the first and second SR flipflops.
A four-man power NOR gate 5 connected to the set input terminal of the SR flip-flop 2.4, an output terminal of the four-man power NOR gate 5, an output terminal of the first two-man power NOR gate 1, and the first SR flip-flop. a first three-man power NOR gate 9 whose input terminal is connected to the second output terminal and whose output terminal is connected to the first output terminal U;
The input terminal is connected to the output terminal of the R gate 5, the output terminal of the second two-power NOR gate 3, and the output terminal of the second SR flip-flop 4, and the output terminal is connected to the second output terminal. It consisted of 2 and 10 three-man powered NOR gates.

Next, the operation of the conventional circuit shown in FIG. 4 will be explained. The reference frequency signal (R input signal) is input from the first input terminal R, and the comparison frequency signal (■ input signal) is input from the second input terminal ■. A step-by-step analysis of the operation of each part in the case where the start-up is delayed is as follows.

(1) As an initial state, consider a state in which both the R input signal and the (1) input signal are at a low level (hereinafter referred to as L), and the output terminal U1D is both in the L state and waiting for the rise of the input signal. In this case, the state of each node is as follows: First and second input terminals R, V:L.

1st and 2nd output terminals U, D: L1 1st and 2nd two-man powered NOR gate 1.3 output High
h level (hereinafter referred to as H), the output L1 of the first and second RS flip-flops 2.4 becomes the output L1 of the 4NOR gate.

(2-1) The R input signal changes to L-H.

(2-2) The output of the first two-man powered NOR gate 1 is H-L
Changes to

(2-3) The level of the first output terminal U changes from L to H. At this point, a steady state is reached, and the first input terminal R: H.

Output L1 of the first two-man powered NOR gate 1 Output L1 of the first RS flip-flop 2 First output terminal U:
Hl Second input terminal V:L.

Output H1 of second two-man powered NOR gate 3 Output L1 of second RS flip-flop 4 Second output terminal D:
Ll will be the output crab L1 of the 4-man NOR gate 5.

(3-1) The V input signal changes from L to H.

(3-2) The output of the second two-man powered NOR gate 3 changes from H to L
Changes to

(3-3) The level of the second output terminal changes from L to H, and the output of the four-man power NOR gate 5 changes from L to H.

(3-4) As the output of the four-man power NOR gate 5 changes from L to H, the first and second output terminals U1D change from H to
The first and second RS flip-flops 2.4
The output changes from L to H.

(3-5) First and second RS flip-flops2.
By changing the output of 4 from L to H, 4-man power NOR
The output of the gate changes to HL.

At this point, a steady state is reached, First and second input terminals R, V:H.

First and second two-man NOR gate 1.3 output crab L1 Output H1 of the first and second RS flip-flops 2.4 First and second output terminals U1D:L.

4-man power NOR gate 5 output crab L1 becomes.

(4-1) The R input signal changes to HL.

(4-2) The output of the first two-man powered NOR gate 1 changes from L to H
Changes to

(4-3) The output of the first RS flip-flop 2 is H→
Changes to L. At this point, a steady state is reached, and the first input terminal R:L.

Output H1 of the first two-man powered NOR gate 1 Output L1 of the first RS flip-flop 2 First output terminal U:L.

Second input terminal V: Hl Output L1 of second two-man power NOR gate Output H1 of second RS flip-flop 4 Second output terminal D: L
.

4-man power NOR gate 5 output crab L1 becomes.

(5-1) The V input signal changes from H to L.

(5-2) The output of the second two-man power NOR gate 3 is L4H
Changes to

(5-3) The output of the second RS flip-flop 4 is H→
It changes to L, becomes a steady state here, and returns to the initial state of (1).

As a result of the above operation, the first output terminal U remains at H level from the rising edge of the R input signal to the rising edge of the (2) input signal. In other words, the pulse width H is proportional to the amount of phase delay of the comparison frequency signal (V side) with respect to the reference frequency signal (R side).
A level signal is obtained. On the other hand, the second output terminal is normally fixed at L level, but when the V input signal that enters with a delayed phase rises, the four-man power NOR gate 5 L+H+L spikes occur for the delay time that occurs.

The above is a case where the rise of ■the input signal is delayed with respect to the R input signal, but conversely, when the phase of the V input signal advances with respect to the R input signal, and ■the input signal rises first, this circuit Since the respective input terminals and output terminals are symmetrical circuits, the first input terminal R and the second input terminal ■, and the first output terminal U and the second output terminal Ri are exchanged. By doing so, the same operations as in (1) to (5-3) above can be obtained. Therefore, when the phase of the (1) input signal is advanced, the output from the second output terminal becomes H level from the rising edge of the (2) input signal to the rising edge of the R input signal. That is, an H level signal having a pulse width proportional to the amount of phase advance of the comparison signal (V side) with respect to the reference signal (R side) is obtained. On the other hand, at the output of the first output terminal U, an L-H-L spike is generated corresponding to the delay time generated in the four-man power NOR gate 5 when the R input signal rises.

The state in which the phase comparator shown in Fig. 4 is incorporated into the PLL is shown in Fig. 5.
As shown in the figure. In the figure, 51 is the phase comparator shown in FIG. 4, 52 is a loop amplifier that amplifies the output signal of the phase comparator, 53 is a loop filter that removes high frequency components, and 54
55 is a frequency dividing circuit, and 56 is a reference frequency signal source. Usually, each of these components 51
55 are each configured in separate ICs.

When a PLL is configured in this way, the phase and frequency of the V input signal are controlled so that the phase difference between the rising edges of the R input signal and the V input signal becomes 0. Therefore, if the phase of the input signal is delayed, The output of the first output terminal U, and when the phase of the V input signal is leading, the output of the second output terminal is
It becomes a thin spike shape. Further, at that time, a spike corresponding to the delay time of the four-man power NOR gate is generated at the output terminal on the opposite side, as described above.

■When the phase of the input signal changes from lagging to leading with respect to the R input signal (the phase of the V input signal advances by 4.5' per cycle with respect to that of the R input signal), the output terminal The output waveform is shown in FIG. As you can see from the figure,
In-phase pulses are always output to the output terminal D1U. For example, at the D terminal, the peak value of the output pulse is constant in the portion where the phase is delayed, but when the phase of the input signal advances, the pulse width increases and the peak value increases according to the advance angle. do. Therefore, as a pulse waveform, the NOR gate 5
A superposition of in-phase pulses with a delay of 2 appears.

[Problems to be Solved by the Invention] In the conventional phase comparator circuit, the first, which is the output pin of the IC,
The signal appearing at the second output terminal U1D is a pulse based on the phase difference signal on which spike-like noise is superimposed. Therefore, a pulse with an unnecessarily high peak value appears at the output terminal of the IC. This pulse is a combination of a reference frequency f component and its harmonic components. When a PLL is configured using this phase comparator as shown in FIG. 5, large spike-like noise will leak from the phase comparator to an external circuit (for example, a VCO). As the noise leaked to vCO increases, V
Modulation occurs in the oscillation frequency of the CO, causing the vCO to generate noise. Oscillators for communication equipment require an oscillation source with particularly low noise, so when using a conventional phase comparator circuit, the vC of the spike containing the reference frequency component is
It was necessary to devise ways to prevent leakage to O.

For example, in the PLL shown in FIG. 5, it is necessary to improve the performance of the loop filter 53 and increase the amount of attenuation for the reference frequency component. Furthermore, if this increases the phase rotation of the filter and reduces the phase margin of the feedback loop, a phase compensation circuit may be required. Furthermore, there are cases where it is necessary to block only the component of the reference frequency fR or to add an injection filter.

In addition, since the first and second output terminals U1D generate spikes of in-phase components, load current flows from the two output terminals to the power supply and ground simultaneously, which causes 1km noise and ground noise. . This noise VCO
In some cases, it was necessary to separate the power supply and ground into separate systems to prevent leakage to other systems.

Furthermore, if the reference frequency f2 is a high frequency, radiation noise will be emitted from the output terminal U1D, and in order to prevent this from leaking to vCO, an isolation shield is installed in the phase comparator circuit or VCO. Sometimes it was necessary.

[Means for Solving the Problems] The phase comparator of the present invention receives a first input signal and a second input signal, and the phase of the first input signal leads the phase of the second input signal. At the same time, positive and negative pulses with pulse widths proportional to the phase difference between the first and second input signals are applied to the first and second input signals, respectively.
Output from the second output terminal, when the phase of the second input signal leads the phase of the first input signal, a positive or negative pulse width proportional to the phase difference between the first and second input signals is output. a phase discriminator that outputs pulses from third and fourth output terminals, respectively, and a composite signal of the signal of the first output terminal and the signal of the fourth output terminal of the phase discriminator is supplied to the first input terminal. entered,
The present invention includes a differential amplifier whose second input terminal receives a composite signal of the signal at the second output terminal and the signal at the third output terminal of the phase discriminator.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the same figure, since 1 to 5 are equivalent to 1 to 5 in FIG. 4, a new explanation will be omitted. In Figure 1,
Reference numerals 6 and 7 are first and second three-way OR/NOR gates, respectively, and 8 is a differential amplifier. The U terminal (NOR output terminal) of the OR/NOR gate 6 and the ■ terminal (OR output terminal) of the OR/NOR gate 7 are connected via resistors R1 and R2, and the U terminal of the OR/NOR gate 6 is connected to the (OR output terminal) and the D terminal (N.

R output terminal) through resistors R3 and R4, the connection point between resistors R and R2 is the positive input terminal of the differential amplifier 8, and the connection point between resistors R3 and R4 is connected to the positive input terminal of the differential amplifier 8. It is connected to the negative input terminal of the differential amplifier 8.

In this example circuit, from input terminals R and V to U terminal and D
The logical operation up to the terminal is similar to that of the conventional example shown in FIG. However, in this example, the three-person NOR game
) is replaced with a three-man OR/NOR gate, so that signals with the opposite phase of the signals at the U and D terminals can be obtained from the U and ■ terminals, respectively. Then, a composite signal is inputted to the positive input terminal of the differential amplifier 8 by the resistances R, R2 of the signal of the U terminal and the signal of the ■ terminal, and the signal of the signal of the ■ terminal and the signal of the D terminal Since the composite signal is input to the negative input terminal of the differential amplifier 8, the signals (U-D) and (D-U
) is obtained.

The first (second) three-man OR/NOR gate 6 (7) is
It is configured by a differential circuit so that the signals from the two output terminals U and 11r (D, rf) are balanced outputs.

Similar to the conventional circuit, in-phase spike components are generated at the U and D terminals, but opposite-phase spike components are generated at the V and ■ terminals, which are terminals on the opposite side of the balanced output. Therefore, the spike noise component can be canceled by combining the U terminal output, the D terminal output, and the ■ terminal output. Since a signal that does not include this spike noise component is input to the amplifier 8, no noise component will appear at the output terminal of the phase comparator of this embodiment. Therefore, a signal that is lower by the amount of spike noise, that is, only the necessary signal components appear at the output terminal of this embodiment.

FIG. 2 shows signal waveforms at various parts when a signal similar to that shown in FIG. 6 is input. As is clear from the figure, when the phase difference is O, the output of the output terminal is also O, and when the phase difference is 18°, the peak value at the output terminal is one of that of the conventional example.
/3 or less.

In this way, since the level of the signal appearing at the output terminal becomes lower, the circuit of this embodiment suppresses leakage of noise to other circuits and emission of radiated noise.

In addition, since the three-man powered OR/NOR gate is of a differential type and always passes a constant current, the circuit of this embodiment can
No more noise will be generated on the ground.

Incidentally, in the circuit of this embodiment as well, a signal of the same level as in the conventional example appears at the U terminal, for example. However, this terminal is not directly connected to the output pin of the IC, and the signal at this terminal is canceled out by the signal at the ■ terminal, so even if high-level signals appear at these terminals, they will not be transmitted to the external circuit. The impact is small.

The circuit of this embodiment can be incorporated into the PLL shown in FIG. In this case, the positive output terminal and negative output terminal of the differential amplifier 8 in FIG. 1 are connected to the loop amplifier 52 in FIG.
What is necessary is to connect it to the positive input terminal and negative input terminal of.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. This example uses the NOR gate 1 in the previous example,
3, 5 as NAND gate 1a 1
3as5a and also OR/NOR gate 6.7.
/NAND gate 6a17a, and an inverter 9 is inserted in front of each input terminal to the SR flip-flop 2.4. The operation is the same as in the previous embodiment except that the phase advance and delay are detected at the falling edge of the two input signals, and the same effects as in the previous embodiment can be obtained.

[Effects of the Invention] As explained above, the phase comparator of the present invention generates a complementary pulse width proportional to the phase difference when the phase of the first input signal leads the phase of the second input signal. a first logic circuit that generates an output signal; and a second logic circuit that generates a complementary output signal with a pulse width proportional to the phase difference when the phase of the first input signal lags the phase of the second input signal. and a differential amplifier, which combines the positive output of the first logic circuit and the negative output of the second logic circuit, and combines the negative output of the first logic circuit and the second logic circuit. Since the positive output of the circuit and the positive output of the circuit are combined and these two combined signals are used as the two input signals of the differential amplifier, according to the present invention, the spike-like output from the first and second logic circuits Noise can be canceled at the input of the differential amplifier, and noise components are no longer superimposed on the signal at the output terminal of the phase comparator of the present invention, thereby preventing the signal level at the output terminal from becoming unnecessarily high. Therefore, according to the present invention, noise is not leaked or radiated to other circuits, and for example,
If the circuit of the present invention is used to configure a PLL, the oscillation frequency of the voltage controlled oscillator can be stabilized without taking special noise countermeasures.

Furthermore, since the differential amplifier and the first and second logic circuits are of a differential type, current consumption is always kept constant, so power supply noise and ground noise are not generated. Therefore, there is no need to separate the power supply, etc. for circuits outside the IC, and this has the effect of stabilizing the operation of the inside of the IC, as well as accommodating other noise-sensitive circuits within the same chip. becomes possible.

[Brief explanation of drawings]

1 and 3 are circuit diagrams each showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part in the embodiment of FIG.
FIG. 4 is a circuit diagram of the conventional example, FIG. 5 is a block diagram of the PLL, and FIG. 6 is a waveform diagram of each part of the conventional example. 1.3...First and second two-man powered NOR gate, 2.4
...first and second SR flip-flops, 5...4
Manually powered NOR gate, 6.7... First and second three manually powered OR/NOR gates, 8... Differential amplifier,
9.10...First and second three-man powered NOR gate,
51... Phase comparator, 52... Loop amplifier,
53... Loop filter, 54... Voltage controlled oscillator (VCO), 55... Frequency divider circuit, 56
...Reference frequency signal source.

Claims (1)

[Claims] A first input signal and a second input signal are input;
When the phase of the input signal leads the phase of the second input signal, positive and negative pulses with pulse widths proportional to the phase difference between the first and second input signals are output to the first and second output terminals, respectively. and when the phase of the second input signal leads the phase of the first input signal, positive and negative pulses with pulse widths proportional to the phase difference between the first and second input signals are outputted to the third input signal, respectively. , a phase discriminator that outputs from a fourth output terminal, and a composite signal of the signal of the first output terminal and the signal of the fourth output terminal of the phase discriminator is input to the first input terminal, and the phase A phase comparator comprising: a differential amplifier whose second input terminal receives a composite signal of a signal at a second output terminal and a signal at a third output terminal of the discriminator.