JPH04180359A - Encoding method for facsimile equipment - Google Patents

Abstract

PURPOSE:To detect the completion of transmission of code data by shifting the contents of first and second shift registers, and comparing the contents of least significant bits of both shift registers. CONSTITUTION:A main controller 1 shifts the contents of the first and second shift registers 7, 8 bit by bit to a low-order digit side at a prescribed timing, and stores information sent out from the least significant bit 7a of the first shift register 7 in a buffet for transmission, and also, compares the content of the least significant bit 7a of the first shift register 7 with that of the least significant bit 8a of the second shift register 8. The content of the least significant bit 7a of the first shift register 7 and that of the least significant bit 8a of the second shift register 8 coincide with each other when they show (0). Thereby, the main controller 1 judges that the transmission of the significant part of one piece of code data is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoding method for a facsimile machine.

2. Description of the Related Art Systems for transmitting variable code length code data obtained by coding image signals of conventional small limb facsimile devices have been known. In this system, in order to notify the image signal processing unit that the transmission of one piece of code data has been completed,
Binary code length data and code data are stored in an encoding table, the code length data is stored in a code length counter consisting of a down counter, and the code data is stored in a code register consisting of a shift register. Each time one bit of code data is transmitted from the register, the code length data of the code length counter is counted down, and when the content of the code length counter becomes zero, the end of transmission is notified to the image signal processing section.

However, in conventional variable code length transmission systems, a code length counter consisting of a down counter is required in addition to a code register consisting of a shift register, and the down counter is smaller than the shift register. Since the circuit configuration is complicated, the manufacturing cost and chip area increase.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an encoding method for a facsimile machine that does not require a down counter when implemented.

The present invention provides an encoding method for a facsimile machine that encodes an image signal using a redundancy suppression method and transmits the encoded image signal. 2 with the same number of bits and the content of each bit corresponding to the significant part of the coded data is the opposite of the coded data.
The reference data, which is value information and the content of each other bit is the same binary information as the code data, is read out from the code data table using the table address signal and stored separately in the first and second shift registers each having a predetermined number of bits. store,
Shift the contents of these shift registers one bit at a time and compare the contents of the least significant bit of both shift registers,
If the two match, it is determined that the content of the last bit of the significant part of the code data has been sent out from the first shift register.

In the present invention, by shifting the contents of the first and second shift registers, the code data and the reference data are shifted one bit each from the least significant bit of the first and second shift registers. Sent out. The reference data is
It has the same number of bits as the code data, the content of each bit corresponding to the significant part of the code data is binary information opposite to the code data, and the content of each other bit is the same binary information as the code data. Therefore, the contents of the lowest focus of both shift registers do not match until the significant part of the code data is sent out from the first shift register. , the contents of the least significant bits of both shift registers match. Therefore, by comparing the contents of the least significant bits of both shift registers, it is possible to detect the end of transmission of code data.

Back-1-■ Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 is a block diagram of the main parts of a facsimile machine used to implement the encoding method in an embodiment of the present invention. A reading section 2 for storing data, a ROM 3 for storing programs, etc., and a RAM for storing data, etc.
4th grade is connected. A part of the ROM 3 includes code data of a predetermined number of bits having a significant part of an arbitrary number of focuses;
Reference data that has the same number of bits as this code data, the content of each bit corresponding to the significant part of the code data is binary information opposite to the code data, and the content of each other bit is the same binary information as the code data. A code data table 5 is configured in which a necessary number of the following are stored alternately. The reading section 2 is equipped with an image signal processing means 6 and the like that performs predetermined processing necessary for encoding the image signal and outputs a table address signal according to the processing result. The main controller 1 temporarily stores the code data and reference data read out from the code data table 5 based on the table address signal from the image signal processing means 6, and shifts the stored contents by 1 bit at a predetermined timing. It has first and second shift registers 7.8 and the like having a predetermined number of bits.

In the code data table 5, for example, a required number of 12-bit code data and reference data are alternately stored as shown in FIG. 2(A). The reference data is 1, which is the same as the code data.
The content of each bit (B/ ) corresponding to the significant part of the code data is binary information opposite to the code data, and the content of each other bit is the same binary information as the code data.

In this example, the significant part of the code data is rl 10111J
Since the reference data is 6 bits, the first 6 bits are ro OOO00J and the latter 6 bits are [00100
0". When these data are read out, the first shift register 7 has roooo as shown in FIG. 2(B).
oollollJ is stored, and the second shift register 8 stores rooooooo.

1000J is stored.

Next, the operation will be explained. The image signal from the reading section 2 is subjected to predetermined processing such as black and white run length calculation by the image signal processing means 6, and a table address signal is output from the image signal processing means 6 according to the content. As a result, the code data as shown in FIG. 2(A), for example, is read out from the code data table 5, and the first code data as shown in FIG. 2(B) is read out.
The reference data stored in the address next to the code data is read out and stored in the second shift register 8. The main controller 1 is
The first and second shift registers 7 at predetermined timing.
．． Shift the contents of 8 bit by bit to the lower digit side, and
The information sent from the least significant bit 7a of the first shift register 7 is stored in a transmission buffer (not shown), and the contents of the least significant bit 7a of the first shift register 7 and the second
The contents of the least significant bit 8a of the shift register 8 are compared. That is, by shifting six times, the last bit "1" of the significant part of the code data is sent from the least significant bit 7a of the first shift register 7, and the contents of the least significant bit 7a of the first shift register 7 and the The contents of the least significant bit 8a of the second shift register 8 are both "0" and match. As a result, the main controller 1 determines that the transmission of the significant part of one piece of code data has been completed, and controls the image signal processing means 6 to read out the next code data and reference data from the code data table 5. and stored separately in the first and second shift registers 7.8.

Thereafter, the significant portions of the encoded data are sequentially transmitted using the same procedure.

An outline of the operation of the main control device 1 for realizing the above operation will be explained with reference to the flowchart of FIG. 3. First, in step 1, run length data corresponding to the image signal from the reading section 2, ie, a table address signal, is outputted from the image signal processing means 6 and stored in an A register (not shown). Next, proceeding to step 2, the contents of the code data table 5 whose address is the contents of the A register are read out and stored in the first shift register 7. Next, proceeding to step 3, the contents of the code data table 5 whose address is the value obtained by adding 1 to the contents of the A register are read out and stored in the second shift register 8.

Next, the process proceeds to step 4, where the contents of each bit of the first shift register 7 and the contents of each bit of the second shift register 8 are logically summed, and the result is stored in a Z register (not shown). Note that the Z register only needs to have one bit or more.

Next, the process proceeds to step 5, where it is determined whether or not the content of the least significant bit of the Z register is "0". If not, the process proceeds to step 6, where the content of the least significant bit of the first shift register 7 is determined. Write the contents of node 7a to the buffer 0th step knob 7
Then, the contents of the first and second shift registers 7.8 are shifted by 1 bit to the lower digits, and the process returns to step 4. In step 5, if the content of the least significant bit of register 2 is "0", the process returns to step 1.

In this way, since we used reference data in which the content of each bit corresponding to the significant part of the code data is binary information opposite to the code data, and the content of each other bit is the same binary information as the code data, First and second shift registers 7.8
Simply shift the contents of 1 bit at a time to the lower digits,
Parallel-to-serial conversion can be performed on the significant part of the coded data, and at the same time, the end of the significant part of the coded data can be determined. Therefore, there is no need for a down counter whose structure is more complicated than that of a shift register, and it is possible to reduce manufacturing costs and miniaturize the chip.

As described above, according to the present invention, code data of a predetermined number of bits having a significant part of an arbitrary number of bits, and each code data having the same number of bits as this code data and corresponding to the significant part of the code data The reference data whose bit contents are binary information opposite to the code data and the contents of other bits are the same binary information as the code data is read out from the code data table using a table address signal, and a predetermined number of bits are read out. The contents of these shift registers are shifted one bit at a time, and the contents of the least significant bits of both shift registers are compared. If they match, the sign data is significant. Since it is determined that the contents of the last bit of the part have been sent out from the first shift register, the contents of the first and second shift registers are simply shifted one bit at a time to the lower digit side. Parallel-to-serial conversion can be performed, and at the same time, it is possible to determine the end of the significant portion of code data. Therefore, there is no need for a down counter whose structure is more complicated than that of a shift register, and excellent effects are achieved in that manufacturing costs can be reduced and chips can be made smaller.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a facsimile machine used to implement the encoding method in an embodiment of the present invention, FIG. 2 is an explanatory diagram of the code data table and data stored in the shift register, and FIG. 3 is a flowchart illustrating an outline of the operation of the main control device. 5-code data table; 7-first shift register;
8...Second shift register. Patent applicant: Murata Machinery Co., Ltd. Figure 1 Figure 2 (A)

Claims (1)

[Claims] (1) In the encoding method of a facsimile machine that encodes and transmits an image signal using a redundancy suppression method, code data of a predetermined number of bits having a significant part of an arbitrary number of bits and a code having the same number of bits as this code data The content of each bit corresponding to the significant part of the data is binary information opposite to the coded data, and the content of each other bit is the same as the coded data.
Reference data, which is value information, is read from the code data table using a table address signal and stored separately in first and second shift registers each having a predetermined number of bits, and the contents of these shift registers are shifted one bit at a time.
A code for a facsimile machine, characterized in that the contents of the least significant bits of both shift registers are compared, and if they match, it is determined that the contents of the last bit of the significant part of the code data has been sent out from the first shift register. method.