JPH04178755A - Data integrator - Google Patents

Abstract

PURPOSE:To suppress the degradation in performance of processing by integrating data, which is distributed to respective pipelines by a distributing means, based on the comparison result of a comparing pipeline means and outputting this data to a communication path. CONSTITUTION:A distributing part 132 alternately distributes transactions from an input part 131 to A and B pipelines of a pipeline part (transaction comparing pipeline part) 133. For the purpose of integrating preceding and succeeding transactions in a transaction string from the distributing part 132, the pipeline part 133 compares the type of a transaction with types of preceding and succeeding transactions on the communication path stored in pipelines and is operated to prevent the delay of processing. Transactions are integrated on the communication path in this manner to reduce the quantity of transactions, and the transaction communication is relaxed. Thus, the degradation in performance of processing is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a data integration device for reducing the amount of transactions on a communication path in, for example, a transaction processing system.

(Prior Art) Conventionally, a transaction processing system is configured as shown in FIG. As shown in FIG. 37, a terminal group 9, which is a group of terminals for inputting and outputting transactions (data related to business processing, etc.), is connected to a lower-level computer 10, respectively. Furthermore, lower-level computer 11
The connection from the host computer 11 to the host computer 11 is through the exchange 12 or directly. The lower-level computer 10 processes requests from the terminal group 9 and transmits transactions to the higher-level computer 1l. The exchange 12 connects a plurality of lower level computers 12 and higher level computers 13. The higher-level computer 11 analyzes transactions from the lower-level computer 10 or from the exchange 12.

In such conventional transaction processing systems, when the amount of transactions between the lower-level computer 10 and the higher-level computer 11 becomes enormous, the communication capacity on the communication path becomes saturated and becomes a communication bottleneck. There is.

Furthermore, when the lower-level computer 10 integrates transactions in order to reduce the amount of transactions on the communication path, the load on the lower-level computer 10 increases, which may reduce performance.

(Problems to be Solved by the Invention) As described above, in conventional transaction processing systems, when the number of transactions becomes enormous, the communication capacity on the communication path may become saturated. In addition, in order to reduce the amount of transactions on the communication path,
1, there was a problem that the performance of the lower-order computer 11 was degraded.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a data integration device capable of suppressing deterioration in processing performance.

[Configuration of the Invention (Means for Solving the Problems) The present invention comprises a comparison pipeline means having at least two opposing pipelines each having a plurality of stages and comparing data in each pipeline. , distribution means for distributing input data to each pipeline of the comparison pipeline means, and integration means for integrating the data distributed to each pipeline by the distribution means based on a comparison result in the comparison pipeline means. and is configured to output the data integrated by the integration means to a communication path.

(Function) According to such a configuration, a plurality of pipelines face each other in the comparison pipeline means, and data is compared at each stage to determine whether or not unification is possible.

Therefore, input data can be integrated over a wide range. Further, by integrating the data, for example, the substantial amount of data in the communication path is reduced, making it possible to perform efficient processing.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a transaction processing system using a data integration device (hereinafter referred to as a communication mitigation device) for integrating transactions related to the same embodiment and easing communication by reducing the amount of data. It is a diagram.

The transaction processing system shown in FIG. 2 has a conventional configuration in which a communication mitigation device 13 according to the present invention is provided on a communication path, and the same parts are denoted by the same reference numerals and the explanation thereof will be omitted. The communication mitigation device 13 is the lower-level computer 10
and the exchange 12, and between the exchange 12 or the lower-level computer IO and the higher-level computer 11. The communication mitigation device 13 integrates the same functions and processing when transmitting transactions from the lower-level computer 10 to the higher-level computer 11.

FIG. 1 is a block diagram showing the detailed configuration of the communication mitigation device 13. As shown in FIG. In FIG. 1, 131 is an input section;
Transactions from the lower-level computer 10 or the exchange 12 are input. The input unit 131 can input transactions from a plurality of communication paths, thereby making it possible to connect computers and peripheral devices and computers in a hierarchical manner.

Reference numeral 132 denotes a transaction distribution unit (hereinafter referred to as distribution unit), which distributes transactions input through the input unit 131 to a transaction comparison pipeline unit 133, which will be described later.

133 is a transaction comparison pipeline section (hereinafter referred to as
(referred to as the pipeline section), and is provided with two pipelines (A pipeline and B pipeline). The pipeline unit 133 causes the transactions inputted to the two pipelines from the distribution unit 132 to flow in opposite directions, and processes the transactions between each stage (first to nth). The process here is to compare transactions in the same stage where the integration flag P (described later) is not set (“0°), and if integration (bearing) is possible, this stage number 133a (described later) is , the transaction vibe register 133b
, 133c P-ADDR" (described later). Also, the integration flag P is set to "1" indicating that bearing is possible.

134 is a B-pipeline output bus (B-BUS), and the transaction output from the B-pipeline of the pipeline unit 133 is transferred to the transaction buffer unit 135.
It is transmitted to the functional units 136-1 to 136-n and 13B-b via b-1 to 135b-n and 135b-b.

Reference numeral 137 denotes an A-pipeline output bus (A-BUS), which transfers transactions output from the A pipeline of the pipeline unit 133 to the transaction buffer unit L35.
It is transmitted to the functional units 136-1 to 136-n and 13B-a via a-1 to 135a-n and 135a-a.

Transaction buffer section 135a-1 to L35a-
n.

135b-1 to 135b-n are attached to the A pipeline output bus 137 and the B pipeline output bus 134, respectively, and a transaction whose address (“P-ADDR”) is a pipeline stage flowing on the buses 134 and 137 is Function unit section 136-1 to which is connected to the next stage
13B-n, it has a function to import the transaction. Furthermore, when supplying transactions to the functional unit units 13B-1 to 13B-n, the transactions are stored in the order in which they were taken in (FIFO) until the transactions on the A and B sides are complete.
It has a function.

Transaction buffer sections 135a-a, 135b-
b respectively A pipeline output buses 137 . It is attached to the B/< Eve line output bus 134, and the transaction buffer sections 135a-1 to 135a-n, L35b
-L to L35b-n has a function of capturing transactions that were not captured, that is, transactions that were not carried.

The functional unit sections 13B-1 to 13B-n have transaction buffer sections 135a-1 to 135a-n and 135b-i corresponding to the number of stages of the node line section 133.
~135b-n, the A pipeline output bus 13
7, 9z<connected to the eve line output bus 134. In the functional two-nit units 13B-1 to 13B-n, transaction buffer units 135a-1 to 135a-n
, 135b-1 to 135b-n and bearing transactions are integrated (bearing). The consolidated transaction is sent to functional unit output bus 138, which will be discussed below.

The functional unit section 138a-a connects to the A pipeline output bus 1 via the transaction buffer section 135a-a.
It is connected to 37. Functional unit section 136 b-b
are connected to the B pipeline output bus 134 via transaction buffer sections 135b-b. Functional unit portions 138a-a and 138b-b are responsible for sending transactions that cannot be bearing to a functional unit output bus 138, which will be described below.

138 is a functional unit output bus (Z-BUS);
Transactions integrated in functional unit units 136-1 to 13B-n and functional unit units 136a-
a, the transaction of 138b-b is output to the unit 139
It is for outputting via .

The output unit 139 takes in the transactions flowing to the functional unit output bus 138 and outputs them from the communication relaxation device 13 .

FIG. 3 is a block diagram showing the detailed internal configuration of the pipeline section 133.

133-1 to 133-n are the first to n-th vibe stages (stage 1 to stage n).

The vibe stage 133-1 has a stage number 133a indicating a stage-specific number assigned to each stage.
-1, an A pipe register 133b-1, a B vibe register 133cm1, and a comparator 133d-1.

Similarly, for the vibe stages 133-2 to 133-n, the stage numbers 133a-2 to 133a-nSA are
Vibe registers 133b-2 to 133b-n, B vibe registers 133cm2 to 133cmn, and comparator 1
33d-2 to 133d-n are provided.

Stage numbers L33a-1 to 133. a-n is an address when selecting the functional unit section 13B.

The A vibe registers 133b-1 to 133b-n contain “
P""P-ADDR"TYPE""DATA-
information is set. Each piece of information is used as follows.

P: Integration flag, B at the same stage as described later
If the result of comparison with “TYPE” in the vibe register is the same, “1” indicates the bearing of the transaction.
“ is set.

P-ADDR: The bearing stage number is set.

TYPE:) Information such as the type of ranzaktion is set.

DATA: Information in which ``TYPE'' indicates the attribute is set.

The pipeline flows in the direction of increasing stage numbers.

B vibe register 133cm1-133cmn has A
Similarly to the vibe register 133b-1=133b-n, information of "P"P-ADDR"TYPE" and "DATA" is set. “P” has A at the same stage.
"1" indicating the bearing of the transaction if the result of comparison with TYPE' in the vibe register is the same.
is set. The pipeline flows in the direction of decreasing stage numbers.

The comparators 133d-1 to 133d-n compare the information "TYPE" in each pipe register (A, B) and set the flag P.
It is determined whether or not to set "1" to "°".

FIG. 4 shows the transaction buffer section 135a.

135b is a block diagram showing a detailed configuration of the functional unit section 13B. FIG.

136a is a bus monitoring unit, and A pipeline output bus 137. The transaction buffer unit 135 monitors the B pipeline output bus 134 and captures transactions specifying its own functional unit unit 136.
a, 135b.

Reference numeral 136b denotes an A transaction buffer, which sequentially takes in transactions from the transaction buffer section 135a and inputs them to a functional calculator 136e, which will be described later.

Reference numeral 136c denotes a B transaction buffer, which sequentially takes in transactions from the transaction buffer section 135b and inputs them to a functional calculator 136e, which will be described later.

13[1d is an output transaction buffer, which holds the results obtained after performing calculations on transactions from the A and B sides in a functional calculator 136e, which will be described later. The output transaction buffer 13[id is connected to the functional unit output bus 138, and the contents held in the buffer 136dl:i are outputted to the outside of the communication mitigation device 13 via the output section 139.

136e is a functional arithmetic unit, which performs transaction “T”.
Transactions from the A and B sides indicated by "YPE" are integrated into one transaction.

Next, the operation of this embodiment will be explained.

As described above, the communication mitigation device 13 in this embodiment has two pipelines and the number of pipeline stages is n. Further, the communication mitigation device 13 is mainly composed of five parts.

That is, the input unit 131, the distribution unit 132, the pipeline unit 133, the calculation unit (transaction buffer unit 135)
a, 135b, a functional unit section 136), and an output section 139.

First, an overview of the overall operation will be explained.

First, when a transaction is input from the lower-level computer 10 or the exchange 12 to the communication mitigation device 13, the input section 13
1 is input. The input section 131 is provided with a plurality of input terminals so that at least two communication paths can be connected. Internally, multiple transactions are arbitrated in an order based on a predetermined algorithm such as time-sharing or random. The arbitrated transaction is distributed to the distribution unit 132
passed to.

The distribution unit 132 sends the transaction from the input unit 131 to the A pipeline of the pipeline unit 133.

Alternately distribute to B pipeline. Note that in the A pipeline, the flow is from stage 1 to stage n, and in the B pipeline, the flow is from stage n to stage 1.

The pipeline unit 133 compares the TYPE of the transaction with the TYPE of transactions stored in the pipeline and preceding and following on the communication path in order to integrate the transactions that come before and after in the transaction sequence from the distribution unit 132. A pipeline sends transactions at each stage to the next stage every cycle.

This ensures that there is no processing delay.

A transaction that has moved 0 stages is transferred to A pipeline a cover 1 corresponding to each pipeline (A, B).
37 and is output to the B pipeline output bus 134.

In the arithmetic unit, functional unit units 13B-1 to 13B-n are provided for the number of pipeline stages (n), and are connected in parallel to the A pipeline output bus 137 and the B pipeline output bus 134. .

Each functional unit section 188-1 to IH-n monitors the current transaction on each output bus (A-BUS, B-BUS) 137, 134, and identifies the stage number and functional unit added on the pipeline. If the numbers are the same, the transaction is imported into its own functional unit. The functional units 13B-1 to 136-n have an A pipeline output bus 137 and a B pipeline output bus 134.
When the transactions from
The arithmetic operation is performed in e and is output to the functional unit output bus 138 via the output processing buffer 136d.

The output section 139 takes the transaction from the arithmetic section output to the functional unit 8 cover 13B and outputs it from the communication relaxation device 13.

Next, the operation in the pipeline section 133 will be explained. First, the transaction from the distributor 132 is
In the A pipeline, it is set in the A vibe register 133b-1, and in the B pipeline, it is set in the B vibe register 133b-1.
Set to cmn. At this time, the vibe register 133
b, 188c's integration flag P is initialized to 0'.

In each stage 1 to n, the comparator 133d compares the "TYPE" of the vibe register 183b of the A pipeline with the "TYPE" of the vibe register IHc of the B pipeline.As a result, the vibe register 133b and the vibe register 133c are compared. The "TYPE" of the registers 133b are determined to be the same type, and the respective registers 133b.

When both of the integrated flags P of the registers 138c are "0", the integrated flags P of the vibe registers 133b and 133c are set to "1", and the contents of the stage number 133a are set to "P-ADDR"'. If the condition is not met, the contents of the register remain unchanged. The next cycle transfers the contents of each stage to the respective next stage in the pipeline flow.

Next, the calculation unit (transaction buffer unit 135a,
135b and functional unit section 136) will be explained later regarding a certain functional unit.

The bus monitoring section 138a of the functional unit section 138 monitors each pipeline output bus 134.137, and
When a transaction with the same stage number as the own functional unit number set in DR" arrives, the transaction is taken into the transaction buffer section 135b from the A pipeline output bus L37 or the B pipeline output bus 134.A bare transaction may still exist in the pipeline unit 133, so subsequent transactions are stored until all transactions are completed.The order in which the transactions are calculated may change depending on the pairing of transactions, but the transaction buffer unit 135a , 135b performs an operation like a FIFO function, so that the functional unit 13
The order of operations within B is guaranteed.

When transactions are completed in the transaction buffer units L35a and 135b, each A transaction buffer 138bSB) Transaction buffer 13
6c, and the transaction is guided to the functional calculator 136e.

In the functional calculator 136e, the transaction “TYP
Transactions are integrated based on "E".

A simple example of the operation is the transaction “TYP
Let "E" be the bank account number and "DATA" be the amount to be transferred.The functional unit section 136 is provided with a data addition function.As a result, if transactions occur simultaneously in the same account, transfers can be made on the communication path. Amounts can be added.

This way your account will be updated instantly. Information such as other transfer sources is not particularly urgent, so please transfer it later.

The calculation result by the functional calculator 138e is set in the output suction buffer 136d. The calculation result of the output transaction buffer 136d is sent to the functional unit output bus 1 along with information such as transaction type.
38, and is transferred to the exchange 12 or the host computer 11 via the output unit 139.

Next, the flow of operations will be specifically explained with reference to FIGS. 5 to 36.

Each of FIG. 5 to FIG. 36 shows a schematic configuration of the communication mitigation device 13 as shown in FIG. Here, it is assumed that the number of stages in the pipeline is five, and transaction types "0" to "4" occur. First, transactions input via the input unit 131 are held in the distribution unit 132. The distributor 132 sequentially distributes to the B pipeline (from the fifth stage) and the A pipeline (from the first stage) of the pipeline section 133. For example, as shown in FIGS. 5 to 11,
The transaction is r4J r3J r3J r
It is assumed that inputs are made in the order of lJr4J r4J rlJ.

Each transaction is sequentially distributed to the A and B pipelines and processed in a predetermined direction. In the processing process, as shown in FIG. 12, the transactions are completed at the same stage of the A pipeline and the B pipeline, and the comparator 133d determines that "TYPE" is the same type, and each node register 133b-3 , 133cm1 is set to "1", and "P-A" is set to "1".
The stage number "3m" is set in "DDR". In the figure, stage numbers set with subscripts are shown. In Figure 13, in the same way, in the second stage, transactions of type "4" are recognized as bearing possible and the integration flag P
"1" is set to "1", and the stage number "2" is 'P-A'.
Set to DDR'. In this way, processing is performed sequentially (Figures 14 and 15), and when a transaction exits the pipeline, if the integration flag P is set to "1", as shown in Figure 16, “P-AD
DR" is held in the transaction buffer section 135b. That is, the transaction whose integration flag P is set to "1" in the second stage is held in the transaction buffer section 135b-2.

Similarly, the type "3" transaction issued from the A pipeline is held in the transaction buffer section 135a-3, as shown in FIG.

As shown in FIG. 18, the transaction buffer 13 connected to the same functional unit section 13B-3
5a-3, 115b-3, when the transaction is held, the functional calculator 136 of the functional unit section 13B-3
e and sent to the functional unit output bus 138 (FIG. 19).

Hereinafter, as shown in FIGS. 20 to 36, transactions that can be integrated are integrated in the functional unit section 136 and output. Note that transactions that cannot be integrated are transferred from the A pipeline output bus 137 to the 27th
As shown in the figure, transaction buffer section 135a
-as is output via the functional unit section 13B-a, and B
As shown in FIG. 28, signals are output from the pipeline output bus 134 via the transaction buffer section 135b-b and the functional unit section 13B-b.

In this way, the amount of transactions can be reduced by consolidating transactions on a communication path, so transaction communication can be relaxed. As a result, it becomes possible to improve the communication ability without reducing the performance of the lower-level computer 11.

Although the above embodiments have been described using transactions as an example, the present invention is not limited to this and can be applied to database updates, network-type vector computers, and the like.

[Effects of the Invention] As described above, according to the present invention, the amount of transactions can be reduced by integrating transactions of the same type on a communication path connecting computers or peripheral terminals and computers. Therefore, even if the transaction processing system has a huge amount of transactions, processing performance will not deteriorate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data integration device (communication mitigation device) according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a transaction processing system using the data integration device shown in FIG. 1. Figure 3 shows the transaction comparison pipeline section (pipeline section) in Figure 1.
Figure 4 is a block diagram showing the detailed configuration of the arithmetic unit (transaction buffer unit, functional unit unit) in Figure 1.
5 to 36 are diagrams specifically explaining the flow of operation of the same embodiment, and FIG. 37 is a block diagram showing the configuration of a conventional transaction processing system. be. 9... Terminal group, 10... Lower level computer, 11... Upper level computer, 12... Exchange, 13... Data integration device (communication mitigation device), 131... Input unit, 132...
...Transaction distribution unit (distribution unit), 133...
・Transaction comparison pipeline section (pipeline section), 134...B pipeline field cover (B -
BUS), 135a. 135b...transaction buffer s, 136...
. . . Functional unit section, 137 . . . A pipeline output bus (A-BU'S), 138 . . . Functional unit output bus (Z-BUS), 139 . . . Output section. Applicant's agent Patent attorney Takehiko Suzue Figure 9 Figure 10! 1 Figure 11 Figure 13 Figure 15 Figure 12 Figure 14 Figure 16 Figure 19 Figure 21 Figure 18 Figure 20 Figure 22 Figure n Figure 24 Figure 28 Figure 29 @ Figure 31 Diagram: Sword Diagram: Diagram 32: Embryo Diagram

Claims (2)

[Claims] (1) Comparison pipeline means having at least two opposing pipelines each having a plurality of stages, and comparing data in each pipeline, and transmitting input data to each pipeline of the comparison pipeline means. a distributing means for distributing, and an integrating means for integrating the data distributed to each pipeline by the distributing means based on a comparison result in the comparing pipeline means, and integrating the data integrated by the integrating means. A data integration device characterized by outputting to a communication path. (2) The data integration device according to claim 1, further comprising input means for inputting data from a plurality of routes, and wherein the distribution means distributes the data input from the input means.