JPH04178172A - Voltage multiplying rectifier circuit - Google Patents
Voltage multiplying rectifier circuitInfo
- Publication number
- JPH04178172A JPH04178172A JP30205790A JP30205790A JPH04178172A JP H04178172 A JPH04178172 A JP H04178172A JP 30205790 A JP30205790 A JP 30205790A JP 30205790 A JP30205790 A JP 30205790A JP H04178172 A JPH04178172 A JP H04178172A
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- Prior art keywords
- capacitor
- rectifier circuit
- power supply
- column
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000003990 capacitor Substances 0.000 claims abstract description 66
- 238000003491 array Methods 0.000 claims abstract description 6
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は倍電圧整流回路、特に両波形で、多段。[Detailed description of the invention] [Industrial application field] The present invention is a voltage doubler rectifier circuit, especially a multi-stage voltage doubler rectifier circuit with both waveforms.
多出力に適した倍電圧整流回路に関する。This article relates to a voltage doubler rectifier circuit suitable for multiple outputs.
多段の倍電圧整流回路としては、第５図に示す。 A multi-stage voltage doubler rectifier circuit is shown in FIG.
コツククロフト・ウオルトン回路か従来よく知られてい
る。この回路は入力交流電源ｌを順次ダイオードＤ１．
Ｄ２．．．Ｄ２ｎの電気弁で押し上げコラムと呼ばれる
コンデンサ列Ｃ１，Ｃ２，、、、Ｃｎを介して電圧を半
サイクル毎に汲み上げて１平滑コラムと呼ばれるコンデ
ンサ列Ｋ１． Ｋ２． 、 、 、 Ｋｎの各コンデン
サにそれぞれ２Ｅづつの電圧を充電して、ｎ段では２ｎ
Ｅの直流出力を与える回路である。この回路は各構成要
素のコンデンサ、ダイオードの耐圧はそれぞれ入力交流
電源ｌの電圧の波高値の２倍で充分てあり、任意の倍数
の直流出力電圧か得られる長所かある。しかしながら出
力コンデンサには交流の半波しか充電されないので、電
圧変動率とりプルか大きくなる問題かある。The Kotscroft-Walton circuit is well known. This circuit sequentially connects the input AC power source l to the diode D1.
D2. ．． ．． The electric valve D2n pumps the voltage every half cycle through the capacitor arrays C1, C2, . K2. , , , Kn capacitors are each charged with a voltage of 2E, and in the n stage, 2n
This is a circuit that provides a DC output of E. This circuit has the advantage that the withstand voltage of the capacitors and diodes of each component is twice the peak value of the voltage of the input AC power supply l, and that an arbitrary multiple of the DC output voltage can be obtained. However, since the output capacitor is charged only by a half wave of alternating current, there is a problem that the voltage fluctuation rate and pull increase.
また、第６図に示す回路は特公昭４８−２５１４３号公
報に示されていた。いわゆるバランス形コツククロフト
・ウオルトン回路である。この回路は、二つの入力交流
電源を用いて、！圧変動率を改善した直流出力を得る回
路である。しかし、この回路は入力交流電源を２つ必要
とする点て、不利である。Further, the circuit shown in FIG. 6 was disclosed in Japanese Patent Publication No. 48-25143. This is a so-called balanced Kotscroft-Walton circuit. This circuit uses two input AC power supplies! This is a circuit that obtains DC output with improved pressure fluctuation rate. However, this circuit has the disadvantage of requiring two input AC power supplies.
本発明はひとつの入力交流電源により構成される。全波
形の倍電圧整流回路を得ることを課題とする。The present invention is configured with one input AC power source. The objective is to obtain a voltage doubler rectifier circuit for all waveforms.
この課題を解決するため、一対の互いに等しい直列数の
コンデンサ列と、これらコンデンサ列の直列接続点に鎖
交接続する一対の互いに等しい直列数のダイオード列と
からなる。４端子押し上げコラムを設け、この４端子押
し上げコラムをブリッジ接続整流回路で挟み込み接続す
ることを提案するものである。In order to solve this problem, it consists of a pair of capacitor strings with an equal number of series connections and a pair of diode strings with an equal number of series connections that are interlinked to the series connection points of these capacitor strings. It is proposed that a 4-terminal push-up column be provided and that this 4-terminal push-up column be sandwiched and connected by a bridge-connected rectifier circuit.
本発明は以上のように構成されているので、単一の入力
交流電源は、一対の４端子押し上げコラムを介して、入
力交流の正方向と負方向の両波について電圧を昇圧駆動
し、この両波についてブリッジ整流回路を駆動するので
、出力には両波の直流を送出することができる。Since the present invention is configured as described above, a single input AC power source boosts and drives the voltage for both positive and negative waves of input AC via a pair of four-terminal push-up columns. Since the bridge rectifier circuit is driven for both waves, it is possible to send both waves of direct current to the output.
第１図は本発明の一実□施例である。同図において、先
ずコンデンサＣＩ、Ｃ２か直列接続されて、コンデンサ
列を形成している。 またコンデンサＫｌ。FIG. 1 shows an embodiment of the present invention. In the figure, first, capacitors CI and C2 are connected in series to form a capacitor array. Also, capacitor Kl.
Ｋ２も直列接続されて、コンデンサ列を形成している。K2 is also connected in series to form a capacitor string.
これら一対のコンデンサ列の直列接続点にはダイオード
列旧、 Ｃ２とダイオード列Ｖ１． Ｖ２とが鎖交接続
される。このようにして４端子の押し上げコラムか形成
される。この４端子の押し上げコラムを挟み込むように
、ダイオード２１．２２．２３．２４からなるブリッジ
接続整流回路か接続される。これらの各ダイオード２１
．２２．２３．２４の極性は、押し上げコラム３の電圧
を順方向とするような極性である。そしてブリッジ接続
整流回路の出力となる。ダイオード２１．２２のカソー
ドと、ダイオード２３、２４のアノードとかこれらの倍
電圧整流回路の出力端子となる。入力交流ｌは図示の如
く、押し上げコラムの基部に接続される。At the series connection point of these pair of capacitor strings, there is a diode string V1.C2 and a diode string V1. V2 is interlinked. In this way, a four-terminal push-up column is formed. A bridge-connected rectifier circuit consisting of diodes 21, 22, 23, and 24 is connected so as to sandwich this four-terminal push-up column. Each of these diodes 21
．． The polarities of 22, 23, and 24 are such that the voltage of the push-up column 3 is in the forward direction. This becomes the output of the bridge-connected rectifier circuit. The cathodes of the diodes 21 and 22 and the anodes of the diodes 23 and 24 serve as output terminals of these voltage doubler rectifier circuits. The input AC l is connected to the base of the lift column as shown.
次に動作を説明すると、先ず入力交流電源１か矢印が正
方向の極性のときは、交流電源ＨａダイオードＤＩＱコ
ンデンサＫｌφ交流電源ｌの経路で電流か流れ、コンデ
ンサＫｌを図示の極性で充電する。Next, the operation will be described. First, when the input AC power supply 1 or the arrow indicates the positive polarity, a current flows through the path of the AC power supply Ha diode DIQ capacitor KlφAC power supply l, charging the capacitor Kl with the polarity shown.
入力交流電源の電圧をＥｓ１ｎωｔとすると、コンデン
サＫｌの充電電圧はその波高値Ｅとなる。（ωは角周波
数、ｔは時間を表す。）つぎに入力交流電源１か矢印か
負方向の極性のときは、交流電源ｌφダイオードＶｌφ
コンデンサＣ１φ交流電源ｌの経路で電流か流れ、コン
デンサＣＩを図示の極性で充電する。コンデンサＣＩの
充電電圧も同様にεとなる。さらに入力交流電源１か矢
印か正方向の極性のときは、交流電源ｌの電圧とコンデ
ンサＣＩの電圧Ｅとの和２ＥかコンデンサＣ１φダイオ
ードＶ２＜コンデンサに２に）コンデンサＫｌに）交流
電源ｌの経路で電流か流れ、コンデンサＫｌ、 Ｋ２を
図示の極性でそれぞれＥに充電する。つぎに入力交流電
源１か矢印か負方向の極性のときは、交流電源１の電圧
とコンデンサに１の電圧Ｅとの和２ＥかコンデンサＫｌ
に）ダイオードＶ２＜コンデンサＣ２φコンデンサＣＩ
＝＝＝＞交流電源ｌの経路て電流か流れ、コンデンサＣ
Ｉ、 Ｃ２を図示の極性でそれぞれＥに充電する。この
ようにして押し上げられた電圧はさらに交流入力電源１
の電圧と和になり、交流入力電源ｌの電圧か矢印が正方
向のときは、交流入力電源１＜コンデンサＣ１に）コン
デンサＣ２φダイオード２３＝）コンデンサＣＯに）ダ
イオード２２呻交流電源１の経路で電流か流れ、コンデ
ンサＣＯは３Ｅに充電される。また交流入力電源１の電
圧が矢印が負方向のときは、交流入力電源ＩＱコンデン
サＫｌφコンデンサに２−）ダイオ−）”２４＝）コン
デンサＣ１φダイオード２１＝＝＝＞交流電源１の経路
で電流か流れ、コンデンサＣＯは３Ｅに充電される。こ
のように交流入力電源ｌの両波で出力を与える。When the voltage of the input AC power source is Es1nωt, the charging voltage of the capacitor Kl becomes its peak value E. (ω represents angular frequency, t represents time.) Next, when the input AC power supply is 1 or the polarity is in the negative direction, the AC power supply lφ diode Vlφ
A current flows through the path of the capacitor C1φ AC power supply l, charging the capacitor CI with the polarity shown. Similarly, the charging voltage of the capacitor CI becomes ε. Furthermore, when the input AC power supply is 1 or the polarity is in the positive direction, the sum of the voltage of the AC power supply L and the voltage E of the capacitor CI is 2E or the capacitor C1φ diode V2<to the capacitor Kl) to the capacitor Kl) Current flows through the path, charging capacitors Kl and K2 to E with the polarity shown. Next, if the input AC power supply 1 is the arrow or the polarity is in the negative direction, the sum of the voltage of AC power supply 1 and the voltage E of capacitor 1 is 2E or the capacitor Kl
) Diode V2 < Capacitor C2φ Capacitor CI
===> Current flows through the path of AC power supply l, capacitor C
Charge I and C2 to E with the polarities shown. The voltage boosted in this way is further increased by the AC input power supply 1.
When the voltage of AC input power supply l or the arrow is in the positive direction, AC input power supply 1 < To capacitor C1) Capacitor C2 φ diode 23 =) To capacitor CO) Diode 22 In the path of AC power supply 1 Current flows and the capacitor CO is charged to 3E. Also, when the voltage of the AC input power supply 1 is in the negative direction of the arrow, the current is connected to the AC input power supply IQ capacitor Klφ capacitor 2-) diode-)"24=) capacitor C1φ diode 21 As a result, the capacitor CO is charged to 3E.In this way, both waves of the AC input power supply l provide an output.
押し上げコラムの段数は図示の２段に限らず１段から任
意の大きい段数にまで、自由に選定できるのは言うまで
もない。また、交流入力電源１の接続位置は図示の位置
に限らず押し上げコラムの相対位置、 （Ａ２．８２）
あるいは（Ａ３．８３）間に、接続することかできる。It goes without saying that the number of stages of the push-up column is not limited to the two stages shown in the figure, but can be freely selected from one stage to any larger number of stages. In addition, the connection position of the AC input power source 1 is not limited to the position shown in the figure, but the relative position of the push-up column, (A2.82)
Alternatively, it is possible to connect between (A3.83).
また同期をとる等の関係を持たせて、複数の交流入力を
印加することもてきる。It is also possible to apply a plurality of alternating current inputs in a synchronized manner.
第２図は３倍電圧整流回路に単純ブリッジ整流回路を併
設した実施例である。この実施例は第１図に示す３倍電
圧整流回路において、ブリッジ接続整流回路の一部の構
成要素を共用して単純ブリッジ整流回路を併設したもの
である。FIG. 2 shows an embodiment in which a simple bridge rectifier circuit is added to a triple voltage rectifier circuit. In this embodiment, in the triple voltage rectifier circuit shown in FIG. 1, a simple bridge rectifier circuit is added by sharing some of the components of the bridge-connected rectifier circuit.
′尚、ダイオード２５．２６の接続点を押し上げコラム
の途中（Ａ２．８２）あるいは（Ａ３．８３）間に接続
すれば、押し上げコラムの段数に応じた第２の出力か得
られる。その場合は、交流電源ｌはブリッジ接続整流回
路２の構成ダイオード２１．２２と２３．２４との間に
配置することか必要となる。'If the connecting points of the diodes 25 and 26 are connected between (A2.82) or (A3.83) of the push-up columns, a second output corresponding to the number of stages of the push-up columns can be obtained. In that case, the alternating current power supply l must be placed between the constituent diodes 21.22 and 23.24 of the bridge-connected rectifier circuit 2.
第３図は本発明の技術思想をさらに拡張して。Figure 3 shows a further expansion of the technical idea of the present invention.
ｎ倍の整流回路とｎ倍の整流回路とを合成した実施例で
ある。ｎ−１段の押し上げコラムを含む第１のｎ倍電圧
整流回路１００を構成し、この回路のブリッジ接続整流
回路のダイオード２１．２２の部分を共通にして第２の
倍電圧整流回路２００を構成する。This is an example in which an n-times rectifier circuit and an n-times rectifier circuit are combined. A first n-fold voltage rectifier circuit 100 including n-1 stages of push-up columns is configured, and a second voltage doubler rectifier circuit 200 is configured by using the diodes 21 and 22 of the bridge-connected rectifier circuit in common in this circuit. do.
ダイオード２１．２２には第１の倍電圧整流回路１００
と第２の倍電圧整流回路２００の双方の電流か流れるの
で、その電流に応じて部品選定か必要となる。A first voltage doubler rectifier circuit 100 is connected to the diodes 21 and 22.
Since current flows through both the voltage doubler rectifier circuit 200 and the second voltage doubler rectifier circuit 200, it is necessary to select components depending on the current.
更に拡張して、一つの交流電源により任意の数の任意の
倍率の倍電圧整流回路を構成できる。Further, it is possible to configure any number of voltage doubler rectifier circuits with any magnification using one AC power source.
第４図は本発明の別の実施例であって、押し上げコラム
のコンデンサの構成を直列形から並列形に変更したもの
である。構成を説明すると、まずコンデンサＣＩ、 Ｃ
２，Ｃｎ−１の各一端を共通接続しておく。また、コン
デンサＫ１． Ｋ２． Ｋｎ−１の各一端を共通接続し
ておく。そしてこれら一対のコンデンサ列の共通接続端
子をそれぞれブリッジ接続整流回路２の端子Ａ１． Ｂ
ｌに接続する。つぎにダイオード旧。FIG. 4 shows another embodiment of the present invention, in which the configuration of the capacitor in the push-up column is changed from a series type to a parallel type. To explain the configuration, first, capacitors CI, C
2. Connect each end of Cn-1 in common. In addition, capacitor K1. K2. Each end of Kn-1 is connected in common. The common connection terminals of these pair of capacitor arrays are connected to the terminals A1. B
Connect to l. Next is the old diode.
Ｄ２．・・・Ｄｎ−１とＶｌ、 Ｖ２．・・・Ｖｎ−１
を直列接続して図示のようにコンデンサ列の各一端をそ
れぞれに鎖交接続する。このようにして押し上げコラム
か構成される。この押し上げコラムをダイオード２１．
２２゜２３、２４からなるブリッジ整流回路により挟み
込み接続される。動作については、第１図の実施例と同
様であるか、押し上げコラムの各コンデンサの充電電圧
か電圧の押し上げに伴って、 Ｅ、２Ｅ、・・・（ｎ−
１）Ｅと一段づつ上昇する。尚、この実施例においては
入力交流電源ｌは押し上げコラムの基部ＡＩ。D2. ...Dn-1 and Vl, V2. ...Vn-1
are connected in series, and one end of each capacitor array is linked to each other as shown. In this way a push-up column is constructed. This push-up column is connected to diode 21.
A bridge rectifier circuit consisting of 22, 23, and 24 is sandwiched and connected. The operation is the same as that of the embodiment shown in Fig. 1, or as the charging voltage of each capacitor in the push-up column is pushed up, E, 2E, ... (n-
1) Go up one step at a time with E. In this embodiment, the input AC power source l is the base AI of the push-up column.
Ｂ１間に接続することか必要条件となる。本実施例は、
第３図に示す実施例の如く、複数回路に拡張することも
可能である。A necessary condition is to connect between B1. In this example,
It is also possible to expand to multiple circuits as in the embodiment shown in FIG.
尚、各出力端子に接続されるコンデンサＣＯは平滑用で
あり１回路構成上、必須の構成要素ではない。出力リプ
ルが許容される用途、またはりプルかある程度含有され
ていた方か好ましい用途においてほこのコンデンサは省
かれる。Note that the capacitor CO connected to each output terminal is for smoothing purposes and is not an essential component in one circuit configuration. This capacitor is omitted in applications where output ripple is acceptable, or where some amount of ripple is preferred.
また、各実施例において、交流電源ｌはインバータによ
り、数十キロヘルツまたはそれ以上の高周波を用いるこ
ともてきる。また、各ダイオードの極性はそれぞれ反対
方向にすることも当然できる。Further, in each embodiment, the AC power supply l can use a high frequency of several tens of kilohertz or more by using an inverter. Furthermore, the polarities of the diodes can of course be set in opposite directions.
本発明は以上述へたような特徴を存し、一つの交流源か
ら複数の直流電圧源を得ることかでき。The present invention has the above-mentioned features and can obtain a plurality of DC voltage sources from one AC source.
しかも９両波形であるので、電圧変動率やりプルを低く
抑えることかできる。また、各ダイオードの耐圧は、す
べて等しく入力交流電圧の波高値の２倍あればよく製作
上、経済的である。Moreover, since it is a 9-way waveform, the voltage fluctuation rate and pull can be kept low. In addition, it is sufficient for the diode to have the same breakdown voltage twice the peak value of the input AC voltage, which is economical in manufacturing.
第１図は本発明に係る３倍電圧整流回路の一実施例を示
す。第２図は３倍電圧整流回路に単純ブリッジ整流回路
を併設した実施例である。第３図は本発明をさらに拡張
して、ｎ倍の整流回路とｍ倍の整流回路とを合成した実
施例である。第４図は押し上げコラムのコンデンサ列を
並列形で構成した実施例である。第５図および第６図は
従来の倍電圧整流回路の例を示す。
１・・・交流電源、２・・・ブリッジ接続整流回路３・
・・押し上げコラム
Ｃ１，Ｃ２，、、、Ｃｎ、 Ｋｌ、に２．、、、Ｋｎ−
・・コンデンサＤ１．Ｄ２．．．．Ｄｎ、 Ｖｌ、Ｖ２
．、、、Ｖｎ・・・ダイオード４１、４２・・・出力端
子
特許出願人 オリジン電気株式会社
第３図
第５図FIG. 1 shows an embodiment of a triple voltage rectifier circuit according to the present invention. FIG. 2 shows an embodiment in which a simple bridge rectifier circuit is added to a triple voltage rectifier circuit. FIG. 3 shows an embodiment in which the present invention is further expanded to combine an n-times rectifier circuit and an m-times rectifier circuit. FIG. 4 shows an embodiment in which the capacitor rows of the push-up column are arranged in parallel. 5 and 6 show examples of conventional voltage doubler rectifier circuits. 1... AC power supply, 2... Bridge connection rectifier circuit 3.
・・Push-up columns C1, C2,..., Cn, Kl, 2. ,,,Kn-
...Capacitor D1. D2. ．． ．． ．． Dn, Vl, V2
．． ,,,Vn...Diode 41, 42...Output terminal Patent applicant Origin Electric Co., Ltd. Figure 3 Figure 5
Claims (6)
のコンデンサ列と、該コンデンサ列の直列接続点に鎖交
接続する互いに等しい数のダイオードを直列接続した一
対のダイオード列とからなる、４端子押し上げコラムと
、該４端子押し上げコラムを挟み込み接続されるブリッ
ジ接続整流回路とからなる倍電圧整流回路。(1) A four-terminal push-up device consisting of a pair of capacitor strings in which equal numbers of capacitors are connected in series, and a pair of diode strings in which equal numbers of diodes are connected in series and linked to the series connection points of the capacitor strings. A voltage doubler rectifier circuit consisting of a column and a bridge-connected rectifier circuit connected to sandwich the four-terminal push-up column.
て構成される第２のブリッジ接続整流回路と、該第２の
ブリッジ接続整流回路の入力端子に接続される交流電源
とを含んで構成される第１項記載の倍電圧整流回路。(2) A second bridge-connected rectifier circuit configured by using a half circuit of the bridge-connected rectifier circuit in common, and an AC power source connected to an input terminal of the second bridge-connected rectifier circuit. 2. The voltage doubler rectifier circuit according to item 1.
のコンデンサ列と、該コンデンサ列の直列接続点に鎖交
接続する互いに等しい数のダイオードを直列接続した一
対のダイオード列とからなる、４端子押し上げコラムと
、該４端子押し上げコラムを挟み込み接続されるブリッ
ジ接続整流回路とからなる倍電圧整流回路と、 該倍電圧整流回路と同様構成で一部回路を共通にして構
成される他の倍電圧整流回路を含んで構成される倍電圧
整流回路。(3) A 4-terminal push-up device consisting of a pair of capacitor arrays each having an equal number of capacitors connected in series, and a pair of diode arrays each having an equal number of diodes connected in series and linked to the series connection point of the capacitor array. A voltage doubler rectifier circuit consisting of a column and a bridge-connected rectifier circuit that is connected by sandwiching the four-terminal push-up column, and another voltage doubler rectifier that has the same configuration as the voltage doubler rectifier circuit and shares some circuits. A voltage doubler rectifier circuit that includes a circuit.
流電源を含んで構成される第１項または第３項記載の倍
電圧整流回路。(4) The voltage doubler rectifier circuit according to item 1 or 3, which includes an AC power source connected to a relative corresponding point of the push-up column.
ンデンサ列と、該コンデンサ列の他の一端にそれぞれに
鎖交接続する互いに等しい数のダイオードを直列接続し
た一対のダイオード列とからなる、４端子押し上げコラ
ムと、該４端子押し上げコラムを挟み込み接続されるブ
リッジ接続整流回路と、前記押し上げコラムの基部に接
続される交流電源とからなる倍電圧整流回路。(5) Consisting of a pair of capacitor rows having an equal number of capacitors connected in common at one end of each capacitor row, and a pair of diode rows having an equal number of diodes connected in series and linked to each other end of the capacitor row; A voltage doubler rectifier circuit comprising a four-terminal push-up column, a bridge-connected rectifier circuit connected to sandwich the four-terminal push-up column, and an AC power source connected to the base of the push-up column.
れる第１項乃至第５項記載の倍電圧整流回路。(6) The voltage doubler rectifier circuit according to any one of items 1 to 5, which includes a capacitor connected to the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30205790A JPH04178172A (en) | 1990-11-07 | 1990-11-07 | Voltage multiplying rectifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30205790A JPH04178172A (en) | 1990-11-07 | 1990-11-07 | Voltage multiplying rectifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04178172A true JPH04178172A (en) | 1992-06-25 |
Family
ID=17904397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30205790A Pending JPH04178172A (en) | 1990-11-07 | 1990-11-07 | Voltage multiplying rectifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04178172A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07258601A (en) * | 1994-03-23 | 1995-10-09 | Fujikura Kasei Co Ltd | Polyurethane resin coating composition |
| WO2007017793A1 (en) * | 2005-08-08 | 2007-02-15 | Philips Intellectual Property & Standards Gmbh | Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier |
-
1990
- 1990-11-07 JP JP30205790A patent/JPH04178172A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07258601A (en) * | 1994-03-23 | 1995-10-09 | Fujikura Kasei Co Ltd | Polyurethane resin coating composition |
| WO2007017793A1 (en) * | 2005-08-08 | 2007-02-15 | Philips Intellectual Property & Standards Gmbh | Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier |
| JP2009505617A (en) * | 2005-08-08 | 2009-02-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Voltage multiplier circuit with improved power efficiency and equipment provided with such a voltage multiplier circuit |
| US7944719B2 (en) | 2005-08-08 | 2011-05-17 | Koninklijke Philips Electronics N.V. | Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier |
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