JPH04178168A - Over voltage protection system of parallel operation system - Google Patents

Abstract

PURPOSE:To realize over voltage protection while keeping redundancy of parallel operation by providing a comparing means which generates an over voltage decision signal when a voltage obtained by rectifying and smoothing an impulse, obtained in the secondary side of a transformer of each power supply unit, in addition to a DC output, has exceeded the reference voltage. CONSTITUTION:When a fault where a resistor R1a of a power supply unit 30a becomes open is generated, an output voltages Vo1, Vo2 rise and a partial voltage of output voltages Vo1, Vo2 exceed the reference voltages Vref 2a, Vref 2b. In this case, comparators 15a, 15b generates an over voltage detecting signal. Moreover, with rise of the output voltage Vo1, the voltage Vc1a rises and a partial voltage of the voltage Vc1a exceeds the reference voltage Vref 3a and a comparator 31a generates an over voltage decision signal. On the other hand, since the PWM circuit 12b executes the control operation to lower the output voltage Vo2, the voltage Vc1b is lowered and the comparator 31a does not generate the over current decision signal and the PWM circuit 12b continuous operations.

Description

[Detailed Description of the Invention] [Summary] Regarding an overvoltage protection method for a parallel operation system that protects loads from overvoltage in a parallel operation system, the present invention aims to provide overvoltage protection while maintaining the robustness of parallel operation. In an overvoltage protection method for a parallel operation system in which a plurality of power supply units that output DC by switching the DC supplied to the transformer and rectifying and smoothing the pulsating current obtained on the secondary side of the transformer are connected to the load in parallel, A first comparison means that generates an overvoltage detection signal when the output voltage of each power supply unit exceeds a first reference voltage, and a pulsating current obtained on the secondary side of the transformer of each power supply unit, separately from the DC output. a second comparing means for generating an overvoltage determination signal when the rectified and smoothed voltage exceeds a second reference voltage; and stopping the switching operation of each power supply unit supplied with the overvoltage detection signal and the overvoltage determination signal. and a stopping means;
The load is configured to be protected from overvoltage.

[Industrial application field]

The present invention relates to an overvoltage protection method for a parallel operation system, and more particularly, to an overvoltage protection method for a parallel operation system that protects a load from overvoltage in the parallel operation system.

BACKGROUND ART In electronic devices such as information processing devices, parallel operation of power supply units is increasing with the aim of increasing capacity, lowering prices, and increasing reliability due to increased processing.

A parallel operation system is, for example, 5
This is a method in which two 0A power supply units are connected in parallel to increase capacity, and the number of power supply units in parallel is increased by adding more loads. In this case, it is necessary to protect the load from being destroyed even if a failure occurs in the power supply unit.

[Conventional technology] FIG. 4 shows a circuit configuration diagram of an example of the conventional method.

In the figure, the differential amplifiers 11a and llb of the power supply unit 10a and lob each have an output voltage Vo1°Vo2 of resistors R1a and R2a, Rlb and R2b l: The divided voltage is set to a reference voltage Vref of, for example, 2.5V. 1 a, V
An error voltage is generated by comparing it with ref 1 b, and the PWM circuits 12a and 12b generate a switching pulse with a pulse width corresponding to the error voltage, thereby switching the switching transistors 13a and 13 provided on the primary sides of the transformers Ta and Tb.
b performs switching respectively, and output voltages Vol, Vo
Constrain the circle so that each of the two is constant.

Further, each of the comparators 15a and 15b has an output voltage Vo
For example, the voltage divided by the resistors R3a and R4a, R3b and R4b of Vo2 is set to the reference voltage Vref 2 of voltage 3V.
a, compared with Vref 2 b, the reference voltage Vref
2a and Vref 2b, generates an H-level overvoltage detection signal and activates the latch circuits 16a and 16b.
The PWM circuit 12a is latched respectively.

The operation of each of 12b is stopped, and the output voltage Vo 1°Vo
2 to prevent overvoltage.

The operation of the power supply unit lOa is shown in a flowchart.
As shown in FIG. 5, after the power is turned on in step 20, the divided voltage of the output voltage Vol is compared with the reference voltage Vref2a (step 21), and when the output voltage Vol is greater, an overvoltage detection signal is generated (step 22), and this signal In step 23), the power is latched and the power is turned off in step 24. The power supply unit 10b also performs the same operation.

[Invention or problem to be solved]

In the conventional system, for example, the resistor R1a of the power supply unit 10a
The differential amplifier 11a
generates an error voltage that increases the output voltage Vol. This causes an overvoltage condition and comparator 1
5a generates an overvoltage detection signal and the PWM circuit 12a stops operating.

However, due to the rise in the output voltage Vol, the comparator 15b of the power supply unit lOb also generates an overvoltage detection signal, causing the PWM circuit 12b to stop.

In other words, since parallel operation is being performed, the own power supply unit 10
All power supply units 10a, 10 even if there is no failure in b.
There was a problem that the system would stop and the robustness of the system would be lost.

The present invention has been made in view of the above points, and an object of the present invention is to provide an overvoltage protection method for a parallel operation system that performs overvoltage protection while maintaining redundancy in parallel operation.

[Means to solve the problem]

The overvoltage protection method of the parallel operation system of the present invention consists of a plurality of power supply units that switch the DC supplied to the primary side of a transformer, rectify and smooth the pulsating current obtained on the secondary side of the transformer, and output DC. In an overvoltage protection method for a parallel operation system connected to a load in parallel, a first comparing means generates an overvoltage detection signal when the output voltage of each power supply unit exceeds a first reference voltage; a second comparison means that generates an overvoltage determination signal when a voltage obtained by rectifying and smoothing the pulsating current obtained on the secondary side separately from the DC output exceeds a second reference voltage; and an overvoltage detection signal and an overvoltage determination signal. and a stop means that stops the switching operation of each power supply unit when supplied to protect the load from overvoltage.

[Effect]

In the present invention, when a failure occurs in any power supply unit operating in parallel, an overvoltage detection signal is generated by the first comparison means of all power supply units, but the overvoltage determination signal is generated by the faulty power supply unit. If only the switching operation of the faulty power supply unit is generated or stopped to prevent overvoltage on the load, the remaining power supply units continue to supply power to the load.

〔Example〕

FIG. 1 shows a circuit configuration diagram of an embodiment of the method of the present invention. In this figure, the same parts as in FIG. 4 are given the same reference numerals, and their explanations will be omitted.

In FIG. 1, diodes Dla and D2a and a coil Lla are connected to the secondary side of the transformer Ta of the power supply unit 30a.
A DC output voltage Vol is obtained by the capacitor C1a and the diode D3a.

D4a, capacitor C2a, and resistor R7a provide a DC voltage Vcl-a that is approximately equal to the output voltage Vol.

Similarly, a DC output voltage Vo2 is obtained by the diodes Dlb and D2b, the coil Llb, and the capacitor C1b connected to the secondary side of the transformer Tb of the power supply unit 30b, and the diode D3b.

D4b, capacitor C2b, and resistor R7b provide a DC voltage Vclb that is approximately equal to output voltage Vo2.

Note that a DC voltage VIN is applied to the transformers Ta and Tb and the switching transistors 13a and 13b.

The above voltages Vcla and Vclb are connected to resistors R5a and R6, respectively.
The voltage is divided by a, R5b and R6b, and the comparator 31
a, 31b, and the reference voltage Vref 2 a
, Vref 2 b, respectively, the reference voltage Vr is slightly lower than
It is compared with ef 3 a and Vref 3 b.

Comparators 31a and 31b have voltages Vcla and Vc, respectively.
The divided voltage of each lb is the reference voltage Vref3 a, Vr
When ef 3 b is exceeded, an H-level overvoltage determination signal is generated and supplied to each of the AND circuits 32a and 32b.

A comparator 15a is provided in each of the AND circuits 32a and 32b.
, 15b, respectively, and the comparators 15a, 15b each take out the overvoltage detection signal when being supplied with the H level overvoltage determination signal, and output the overvoltage detection signal to the latch circuit 16a.

16b.

Here, for example, if a failure occurs in the resistor R1a of the power supply unit 30a, the PWM circuit 12a performs a control operation so that the output voltage Vol increases due to the error voltage of the differential amplifier 1-1a, and thereby the output voltage V
ol and Vo2 rise as shown in FIG. 2 (A), and the comparators 15a and 15b respectively output
2 divided voltage or reference voltage Vref 2 a, Vref
2b, an overvoltage detection signal shown in FIG. 2(B) is generated.

Moreover, as the output voltage Vol rises, the voltage Vcla increases to the second level.
As shown in FIG.
When the voltage exceeds a, an overvoltage determination signal shown in FIG. 2(D) is generated. This overvoltage judgment signal is approximately the same as the overvoltage detection signal.
generated in time. Therefore, the latch circuit 16a
The PWM circuit 1 sends a stop instruction as shown in Fig. 2 (G).
2a, and the PWM circuit 12a stops operating.

However, as the output voltage Vol rises, the PWM circuit 12
b performs a control operation to lower the output voltage Vo2, so the voltage Vclb decreases as shown in FIG. 2(E),
The comparator 31a does not generate an overvoltage determination signal as shown in FIG. 2(F). As a result, the latch circuit 16b does not instruct the PWM circuit 12b to stop, as shown in FIG. 2(H), and the PWM circuit 12b continues its operation without stopping.

The operation of the power supply unit 30a is shown in a flowchart.
As shown in FIG. 3, after the power is turned on in step 4o, the divided voltage of the output voltage Vol is compared with the reference voltage Vref2a (step 41), and when the output voltage Vol is greater, the divided voltage of the voltage Vcla is further compared with the reference voltage Vref3a. When the voltage becomes large (step 42), an overvoltage detection signal is generated (step 43), and this signal is latched (step 44).
, the power is turned off in step 45. Power supply unit 3
0b also performs the same operation.

In this way, when a failure occurs in any power supply unit 30a that is operating in parallel, all power supply units 30a
An overvoltage detection signal is generated by the comparators 15a and 15b of the faulty power supply unit 30a, and an overvoltage judgment signal is generated by the comparator 31a of the faulty power supply unit 30a, and the switching operation of only the faulty power supply unit 30a is stopped and the load R5 is The filter prevents the filtering voltage, and the remaining power supply unit 1-30b operates normally and continues to supply power to the load RL, and the redundancy of parallel operation is maintained.

〔Effect of the invention〕

As described above, the overvoltage protection method for the parallel operation system of the present invention can provide overvoltage protection while maintaining the redundancy of parallel operation, and is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of an embodiment of the inventive method, Fig. 2 is a signal timing chart of each part of the circuit shown in Fig. 1, Fig. 3 is a flow chart of the circuit operation of Fig. 1, and Fig. 4 is a conventional method. FIG. 5 is a flowchart of the circuit operation of FIG. 4. In the figure, 11a and llb are differential amplifiers, 12a and 12b are PWM circuits, 13a and 13b are switching transistors, 15a,
15b, 31a, and 31b are comparators, and Ta and Tb are transformers. Patent applicant: Fujitsu Ltd. Patent attorney: Osamu Katayama ``7j''
, , . ', -2,'Gol \, -1/ Stop instruction↓

Claims (1)

[Scope of Claims] A plurality of power supply units in parallel that output DC by switching the DC supplied to the (Ta, Tb) primary side of a transformer, rectifying and smoothing the pulsating current obtained on the secondary side of the transformer. In an overvoltage protection method for a parallel operation system connected to a load, first comparison means (15a, 15b) generate an overvoltage detection signal when the output voltage of each power supply unit (30a, 30b) exceeds a first reference voltage. ) and each power supply unit (3
0a, 30b) which generates an overvoltage determination signal when the voltage obtained by rectifying and smoothing the pulsating current obtained on the secondary side of the transformer separately from the DC output exceeds the second reference voltage.
1a, 31b), and stopping means (16a, 32a, 16b, 32
b) An overvoltage protection method for a parallel operation system, comprising: protecting the load from overvoltage.