JPH0417511B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a video printer for an image printer that receives a video signal as input and records the screen of a raster scan type CRT or the like as a hard copy using data obtained by sampling and digitizing the video signal. This invention relates to signal processing circuits.

If the horizontal effective scanning period in a raster scan video signal is 53.5 μsec, and 600 sampling points are provided for one horizontal effective scanning period,
The interval between sampling points is approximately 0.09 μsec. in general,
Analog-to-digital (AD) converters used to convert analog signals into numbers that can perform high-speed conversion are difficult to achieve. If the number of sampling points is reduced in order to eliminate the restriction on the conversion period of the AD converter, the resolution will decrease and the image quality of the hard copy will become coarse.
Alternatively, if the sampling points in one horizontal effective scanning period are shifted on the time axis and assigned to a large number of frames, the sampling point interval becomes longer and the AD conversion time becomes longer. However, with this method, 1
The disadvantage is that it takes a long time to process the screen.

In order to solve the problems of the video signal processing circuit of an image printer, the present invention has been developed to solve the above-mentioned problem of the video signal processing circuit of an image printer.
An N-ary counter that satisfies the relationship of N and takes the sampling pulse as a count input, an M-ary counter that can be preset and uses the output of the N-ary counter as an input, and only during one count period based on the preset data of the M-ary counter. , a sampling timing circuit that generates N shift pulses, a level detection circuit that detects a plurality of levels of a video signal, and a data encoder that converts and outputs the output of the level detection circuit as a code consisting of desired n bits. from a memory device having a capacity of n×N bits or more and configured to transfer n bits of the output of the data encoder in parallel using N shift pulses generated by the sampling timing circuit. 1 is a video signal processing circuit for an image printer characterized by the following configuration.

Embodiments of the present invention will be described below based on the drawings. FIG. 1 is a block diagram of a video signal processing circuit of the present invention. In FIG. 1, a sampling signal oscillator 1 is a highly stable oscillator using a crystal resonator. In this embodiment, the video signal source 8 is:
Since a progressive scanning composite video signal is used, it is input to a synchronization signal separation circuit 10 and a video signal separation circuit 11, where it is separated into a video synchronization signal 9 and a video signal 15 consisting of a horizontal synchronization signal and a vertical synchronization signal. . The video synchronization signal 9 is used as a timing pulse for the M-ary counter 3 to preset the data latched by the preset data latch 4. It is also used to reset the N-ary counter 2. Preset data latch 4
is used to latch data in order to instruct the M-adic counter 3, which is used to divide one horizontal effective scanning period into M sampling intervals, to indicate the interval to be sampled. In this embodiment, the M-ary counter 3 is configured as a down counter that can be preset.

The main controller of the image printer having the video signal processing circuit of this embodiment uses the video synchronization signal 9
When a vertical synchronizing signal is detected in the preset data latch 4, data corresponding to the sampling interval to be sampled is latched. The M-ary counter 3 presets the latch data of the preset data latch 4 in synchronization with the video synchronization signal 9. The N-ary counter 2, which has been reset by the video synchronization signal 9, starts counting the output signal of the sampling signal generator 1 when the video synchronization signal 9 turns OFF. The output of the N-ary counter 2 becomes the count input of the M-ary counter 3. M-ary counter 3
continues to count down, and when it has counted a preset predetermined number of times, it generates a borrow output to the sampling timing circuit 5. The sampling timing circuit 5 extracts the output of the sampling signal oscillator 1 only when the borrow output is ON, and generates N shift pulses 7 to shift the shift register group 6.

Therefore, according to the video signal processing circuit of this embodiment, one horizontal effective scanning period is divided into M sampling sections, and each sampling section includes N sampling signals. Therefore, one horizontal effective scanning period includes a maximum of M×N sampling signals.
In reality, even if one horizontal effective scanning period is M x (one sampling interval), presetting is performed by the video synchronization signal 9, so the value of M is determined by the configuration of the counter length. It is not intended to limit. The video signal 15 extracted from the video signal source 8 by the video signal separation circuit 11 is divided into k voltage levels by the level detection section 12, and is converted into data as k binary signals. The data is input to the encoder 13 and converted into an n-bit binary code required by the image printer. The level detection unit 12 is composed of k level comparators made of bipolar melangisters whose set levels are variable. Data encoder 13
Each bit of the amplitude data of the video signal converted by is input to each of the n register groups 16, and read into the register group 6 in parallel by the N shift pulses 7.

In other words, digitization was performed in synchronization with the sampling signal. The readout circuit 14 combines the parallel outputs of the respective shift registers of the register group 6 in accordance with the bit configuration of the memory used to control the image printer, and transfers the combined outputs to the main controller. It is also possible to use an IC memory or the like instead of a shift register as long as it can respond to the sampling frequency. In this case, the memory element needs to have a capacity of n×N bits.

FIG. 2a shows one horizontal scanning period of a composite video signal, and FIG. 2b shows the division of sampling sections into one horizontal scanning period. FIG. 3 is a timing diagram when N=8 and the order of the preset sampling intervals of the M-ary counter 3 is set to 2. FIG. 3a shows the output of the sampling signal oscillator 1, and when the video synchronizing signal b turns OFF, the N-ary counter 2 starts counting.
In d and e, the M-ary counter generates a borrow output in the second sampling interval, and the sampling timing circuit
This indicates that eight shift pulses were generated.

As explained above, if the video signal processing circuit for image printers of the present invention is used, the only part that directly handles analog signals is the level comparator, and the rest can be processed in TTL, so it can be integrated into an integrated circuit. It is also easy to process the sampled signal, and it is also possible to increase the speed of the sampling signal as long as the response time of the level comparator and the part that temporarily stores the numerical data allows.

The present invention is effective when an image printer is configured to copy screens sequentially. That is, since the video signal processing is fast, the video signal processing can be performed during paper feeding time, etc., the printing speed is not reduced due to signal processing, and the circuit configuration is simple and low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing circuit according to the present invention, FIG. 2 is an explanatory diagram of horizontal scanning periods and sampling intervals, and FIG. 3 is an explanatory diagram of timing in an embodiment. 1... Sampling signal oscillator, 2... N-ary counter, 3... M-ary counter, 4... Preset data latch, 5... Sampling timing circuit, 6...
Shift register group, 7...Shift pulse, 8...
Video signal source, 9... Video synchronization signal, 10...
Synchronous signal separation circuit, 11... video signal separation circuit,
12... Level detection section, 13... Data encoder, 14... Readout circuit.

Claims (1)

[Claims] 1. An N-ary counter that counts and inputs sampled signals, satisfying the relationship PM×N, assuming P sampled signals for one horizontal scanning period of a video signal, and a presettable counter that receives the output of the N-ary counter as input. An M-ary counter, a sampling timing circuit that generates N shift pulses only during one count period based on preset data of the M-ary counter, a level detection circuit that detects a plurality of levels of a video signal, and the level detection circuit. a data encoder that converts the output of the signal detection circuit into desired n bits;
A video signal processing circuit for an image printer comprising a memory device having a capacity of more than one bit.