JPH04172963A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH04172963A JPH04172963A JP29740190A JP29740190A JPH04172963A JP H04172963 A JPH04172963 A JP H04172963A JP 29740190 A JP29740190 A JP 29740190A JP 29740190 A JP29740190 A JP 29740190A JP H04172963 A JPH04172963 A JP H04172963A
- Authority
- JP
- Japan
- Prior art keywords
- output
- voltage
- circuit
- turned
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 claims description 16
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 abstract description 6
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 9
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は出力回路に係り、特に出力にソースフォロアと
したＮチャネル電界効果トランジスタを使用し、出力ト
ランジスタのゲート電圧を正の電源電位より高電圧に昇
圧してドライブする出力回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output circuit, and in particular uses an N-channel field effect transistor as a source follower for the output, and sets the gate voltage of the output transistor higher than the positive power supply potential. This invention relates to an output circuit that boosts and drives a voltage.
従来のこの種の出力回路は、第３図に示す様に、電源Ｖ
ＤＤと接地電位ＧＮＤの間の電圧ＶＤＤ１（Ｖ）を基に
した昇圧回路で、ゲート電圧をＶＤＤより高圧に昇圧す
る構成となっていた。その動作を以下に説明する。A conventional output circuit of this type, as shown in FIG.
This booster circuit is based on the voltage VDD1 (V) between DD and the ground potential GND, and is configured to boost the gate voltage to a higher voltage than VDD. Its operation will be explained below.
発振器６の出力信号を電圧ＶＤＤＩを基にした信号とし
、インバータ８の出力１３が“Ｌ”、インバータ１０の
出力１４が“ＨＩＩの時、スイッチ１をＯＮ、スイッチ
２をＯＦＦ、スイッチ３をＯＮとし、接点１１の電圧ｖ
ｎｎｔまで上げ、次にインバータ８の出力１３が“Ｈ”
、インバータ１０の出力１４が“Ｌ”と反転したとき、
スイッチ１をＯＦＦ、スイッチ２をＯＮ、スイッチ３を
ＯＦＦとし、インバータ８の出力１３が電圧ＶＤＤＩに
なると、第５図に示すように、接点１１を〔２×ＶＤＤ
Ｉ（Ｖ）：］に昇圧し、コンデンサ５に充電する。再び
、インバータ８の出力１３とインバータ１０の出力１４
が反転するとき、スイッチ１をＯＮ、スイッチ２をＯＦ
Ｆ、 スイッチ３をＯＮとし、インバータ１０の出力１
４が電圧Ｖ。０．に上がると、接点１２は（：３ＸＶＤ
Ｄｌ （Ｖ）：）に昇圧し、昇圧した電圧を出力電界
効果トランジスタ７のゲートに供給する。こうすること
で、ソースフォロア出力のトランジスタ７のオン抵抗を
十分に下げ、パワーロスを小さくするようにしている。The output signal of the oscillator 6 is a signal based on the voltage VDDI, and when the output 13 of the inverter 8 is "L" and the output 14 of the inverter 10 is "HII", switch 1 is turned on, switch 2 is turned off, and switch 3 is turned on. and the voltage of contact 11 v
nnt, then the output 13 of inverter 8 goes “H”
, when the output 14 of the inverter 10 is inverted to "L",
When the switch 1 is turned off, the switch 2 is turned on, and the switch 3 is turned off, and the output 13 of the inverter 8 becomes the voltage VDDI, the contact 11 is set to [2×VDD] as shown in FIG.
I(V):] and charges the capacitor 5. Again, the output 13 of inverter 8 and the output 14 of inverter 10
When reverses, switch 1 is turned on, switch 2 is turned off
F. Turn on switch 3 and output 1 of inverter 10.
4 is the voltage V. 0. , contact 12 becomes (:3XVD
The voltage is boosted to Dl (V):) and the boosted voltage is supplied to the gate of the output field effect transistor 7. By doing so, the on-resistance of the source follower output transistor 7 is sufficiently lowered to reduce power loss.
前述した従来の出力回路は、ソースフォロアの出力電界
効果トランジスタ７のゲート電圧を昇圧する昇圧回路を
、ＶＤ、−ＧＮＤ間の電圧ＶＤＤ１で構成しているため
、電圧ＶＤＤＩが変動すると、昇圧された電圧もＶＤＤ
に対して変動する。従って、負荷出力電流を供給する前
記Ｎチャネル電界効果トランジスタ７のゲート電位が変
化するため、前記Ｎチャネル電界効果トランジスタ７の
オン抵抗が電圧ＶＤＤＩに依存して変化する。また電圧
ＶＤＤ、が高い電圧になったとき、昇圧回路の過昇圧に
よりゲート破壊を起こすという欠点があった。In the conventional output circuit described above, the booster circuit that boosts the gate voltage of the output field effect transistor 7 of the source follower is configured with the voltage VDD1 between VD and -GND, so when the voltage VDDI fluctuates, the boosted voltage increases. Voltage is also VDD
fluctuates relative to Therefore, since the gate potential of the N-channel field effect transistor 7 that supplies the load output current changes, the on-resistance of the N-channel field effect transistor 7 changes depending on the voltage VDDI. Another drawback is that when the voltage VDD becomes a high voltage, gate breakdown occurs due to excessive boosting of the booster circuit.
本発明の目的は、前記欠点を解決し、もとの電圧ＶＤＤ
Ｉが変動しても、出力トランジスタがゲート破壊を起こ
すことのないようにした半導体装置を提供することにあ
る。The purpose of the present invention is to solve the above-mentioned drawbacks and to restore the original voltage VDD
It is an object of the present invention to provide a semiconductor device in which gate breakdown of an output transistor does not occur even if I fluctuates.
本発明の出力回路の構成は、出力Ｎチャネル電界効果ト
ランジスタのゲートに供給するＶ。０以上の電圧を、Ｖ
ＤＤを基準にした定電圧回路を基に発生する昇圧回路を
備えていることを特徴とする。The configuration of the output circuit of the present invention is such that V is supplied to the gate of the output N-channel field effect transistor. A voltage of 0 or more, V
It is characterized by being equipped with a booster circuit that generates voltage based on a constant voltage circuit with DD as a reference.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
第１図において、本実施例の出力回路は、定電圧回路工
６と、発振器６と、相補型電界効果トランジスタからな
るインバータ８，９．１０と、コンデンサ４，５と、ス
イッチ１，２．３と、Ｎ型出力電界効果トランジスタ７
と、接点１１〜１４とを備え、負荷１５に出力している
。In FIG. 1, the output circuit of this embodiment includes a constant voltage circuit 6, an oscillator 6, inverters 8, 9, 10 consisting of complementary field effect transistors, capacitors 4, 5, switches 1, 2, . 3, and an N-type output field effect transistor 7
and contacts 11 to 14, and outputs to a load 15.
電源ＶＤＤと、これを基準とした定電圧回路１６の出力
電圧との間の電圧（以降■、と記す）を基にした昇圧回
路で、ゲート電圧を電圧ｖＤｎより高圧に昇圧する構成
となっている。その動作を以下に説明する。This is a booster circuit based on the voltage (hereinafter referred to as ■) between the power supply VDD and the output voltage of the constant voltage circuit 16 based on this, and is configured to boost the gate voltage to a higher voltage than the voltage vDn. There is. Its operation will be explained below.
インバータ８，９．１０は、正の電源電圧を基準とした
定電圧回路１６の出力電圧を電源とし、発振器６の出力
信号により動作する。初め、インバータ８の出力１３が
“Ｌ”、インバータ１０の出力１４が“Ｈ”の時、スイ
ッチ１ｔ−ＯＮ、 スイッチ２をＯＦＦ、スイッチ３を
ＯＮとし、接点１１の電位をＶＤＤまで上げ、次にイン
バータ８の出力１３が“Ｈ”、インバータ１０の出力１
４が“Ｌ”と反転したとき、スイッチ１をＯＦＦ、 ス
イッチ２をＯＮ、スイッチ３をＯＦＦとし、接点１３が
ｖＤＤとなると、接点１１は電圧（ＶＤＤＩ ＋Ｖ、）
に昇圧し、コンデンサ５に充電する。The inverters 8, 9, and 10 are powered by the output voltage of the constant voltage circuit 16 based on the positive power supply voltage, and are operated by the output signal of the oscillator 6. Initially, when the output 13 of the inverter 8 is "L" and the output 14 of the inverter 10 is "H", switch 1t is turned on, switch 2 is turned off, switch 3 is turned on, the potential of contact 11 is raised to VDD, and then , the output 13 of the inverter 8 is “H” and the output 1 of the inverter 10 is “H”.
4 is reversed to "L", switch 1 is turned OFF, switch 2 is turned ON, switch 3 is turned OFF, and when contact 13 becomes vDD, contact 11 becomes voltage (VDDI +V, )
and charges the capacitor 5.
再び、インバータ出力１３．１４が反転したとき、スイ
ッチ１，２．３をそれぞれＯＮ、ＯＦＦ、ＯＮとし、イ
ンバータ１０の出力１４がｖａｏｔに上がると、接点１
２は電圧［：ＶＤＤ１＋Ｖｔ＋Ｖ’ｔ（第４図参照）〕
まで昇圧し、出力電界効果トランジスタ７のゲートに電
圧を供給する。Again, when the inverter output 13.14 is inverted, switches 1 and 2.3 are turned ON, OFF, and ON, respectively, and when the output 14 of the inverter 10 rises to vaot, contact 1
2 is the voltage [:VDD1+Vt+V't (see Figure 4)]
and supplies the voltage to the gate of the output field effect transistor 7.
この際、電圧Ｖ、は電圧ＶＤＤＩを基にした定電圧なの
で、出力電界効果トランジスタ７のゲート電圧は、電圧
Ｖ ＤＤＩに対して一定となる。At this time, since the voltage V is a constant voltage based on the voltage VDDI, the gate voltage of the output field effect transistor 7 is constant with respect to the voltage VDDI.
次に本発明の第２の実施例の出力回路を説明する。第２
図は本発明の第２の実施例の基本のブロック図である。Next, an output circuit according to a second embodiment of the present invention will be explained. Second
The figure is a basic block diagram of a second embodiment of the present invention.
第２図において、本実施例では、前記第１の実施例のス
イッチ１，２．３を、ダイオード１ａ＋ ２ａ、３ａ
とした。昇圧機構としては、前記第１の実施例の同じで
ある。本第２の実施例では、ダイオードｌａ、２ａ、３
ａを使用することにより、スイッチドライブを省略でき
る。In FIG. 2, in this embodiment, the switches 1, 2.3 of the first embodiment are replaced with diodes 1a+2a, 3a.
And so. The boosting mechanism is the same as in the first embodiment. In this second embodiment, diodes la, 2a, 3
By using a, the switch drive can be omitted.
但し、昇圧値はダイオードの順方向電圧Ｖｐ分降下し、
電圧（ＶＤＤＩ ＋’ＶＩ ＋ＶＩ −３Ｖｐ ：］
（！：なる。However, the boost value drops by the forward voltage Vp of the diode,
Voltage (VDDI +'VI +VI -3Vp:]
(!:Become.
〔発明の効果〕
以上説明したように、本発明は、ソースフォロアとした
Ｎチャネル電界効果トランジスタを使用した出力回路に
おいて、出力電界効果トランジス夕のゲート電圧を電源
電圧を基準とした定電圧下で昇圧するため、出力電界効
果トランジスタのゲートソース間電圧は電源電圧に対し
て常に一定となり、そのため出力オン抵抗の電源電圧依
存性がなくなり、また電圧ＶＤＤＩが高い電圧のとき、
ゲート破壊も起こらないという効果を存する。[Effects of the Invention] As explained above, the present invention provides an output circuit using an N-channel field effect transistor as a source follower, in which the gate voltage of the output field effect transistor is controlled under a constant voltage with reference to the power supply voltage. Since the voltage is boosted, the gate-source voltage of the output field effect transistor is always constant with respect to the power supply voltage, so the dependence of the output on-resistance on the power supply voltage disappears, and when the voltage VDDI is high,
This has the effect that gate destruction does not occur.
第１図は本発明の第１の実施例の出力回路を示す回路図
、第２図は本発明の第２の実施例の回路図、第３図は従
来技術の出力回路の回路図、第４図は第１図の特性を示
す電位図、第５図は従来回路の電位図である。
１．２．３・・・スイッチ、１ ａｌ ２ ａｌ
３ ａ・・・ダイオード、４，５・・・コンデンサ、６
・・・発振器、７・・・出力電界効果トランジスタ、８
，９．１０・・・ＣＭＯＳインバータ、１１，１２．１
３．１４・・・接点、１５・・・負荷、１６・・・安定
回路。FIG. 1 is a circuit diagram showing an output circuit of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIG. 3 is a circuit diagram of a conventional output circuit, and FIG. FIG. 4 is a potential diagram showing the characteristics shown in FIG. 1, and FIG. 5 is a potential diagram of a conventional circuit. 1.2.3...Switch, 1 al 2 al
3 a...Diode, 4, 5... Capacitor, 6
...Oscillator, 7...Output field effect transistor, 8
, 9.10...CMOS inverter, 11, 12.1
3.14...Contact, 15...Load, 16...Stability circuit.
Claims (1)
スフォロアタイプの出力回路において、前記電界効果ト
ランジスタのゲート電圧を昇圧する昇圧回路が、正の電
源電位を基準とした定電圧回路で構成されていることを
特徴とする出力回路。In a source follower type output circuit using an N-channel field effect transistor for output, a booster circuit that boosts the gate voltage of the field effect transistor is configured as a constant voltage circuit with a positive power supply potential as a reference. Features an output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2297401A JP2718258B2 (en) | 1990-11-02 | 1990-11-02 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2297401A JP2718258B2 (en) | 1990-11-02 | 1990-11-02 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04172963A true JPH04172963A (en) | 1992-06-19 |
| JP2718258B2 JP2718258B2 (en) | 1998-02-25 |
Family
ID=17846022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2297401A Expired - Fee Related JP2718258B2 (en) | 1990-11-02 | 1990-11-02 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2718258B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1008142C2 (en) * | 1997-01-27 | 2000-01-19 | Honeywell Inc | Bidirectional DC converter. |
| JP2002153045A (en) * | 2000-11-10 | 2002-05-24 | Denso Corp | Charge-pump circuit and load-driving circuit using the same |
| WO2003034576A3 (en) * | 2001-10-19 | 2004-06-03 | Clare Micronix Integrated Syst | Method and system for charge pump active gate drive |
| JP2005304144A (en) * | 2004-04-08 | 2005-10-27 | Nissan Motor Co Ltd | Fet driving unit and method of controlling fet drive voltage |
| JP2005328625A (en) * | 2004-05-13 | 2005-11-24 | Fujitsu Ten Ltd | Power unit, voltage control method, and voltage control program |
| US7079131B2 (en) | 2001-05-09 | 2006-07-18 | Clare Micronix Integrated Systems, Inc. | Apparatus for periodic element voltage sensing to control precharge |
| US7079130B2 (en) | 2001-05-09 | 2006-07-18 | Clare Micronix Integrated Systems, Inc. | Method for periodic element voltage sensing to control precharge |
| US7764113B2 (en) | 2007-07-11 | 2010-07-27 | Panasonic Corporation | Output circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6416118A (en) * | 1987-07-10 | 1989-01-19 | Nec Corp | Gate driving circuit |
| JPS6414768U (en) * | 1987-07-17 | 1989-01-25 |
-
1990
- 1990-11-02 JP JP2297401A patent/JP2718258B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6416118A (en) * | 1987-07-10 | 1989-01-19 | Nec Corp | Gate driving circuit |
| JPS6414768U (en) * | 1987-07-17 | 1989-01-25 |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1014047C2 (en) * | 1997-01-27 | 2001-03-06 | Honeywell Inc | Device for simultaneously supplying different DC voltages. |
| NL1008142C2 (en) * | 1997-01-27 | 2000-01-19 | Honeywell Inc | Bidirectional DC converter. |
| JP2002153045A (en) * | 2000-11-10 | 2002-05-24 | Denso Corp | Charge-pump circuit and load-driving circuit using the same |
| US7079131B2 (en) | 2001-05-09 | 2006-07-18 | Clare Micronix Integrated Systems, Inc. | Apparatus for periodic element voltage sensing to control precharge |
| US7079130B2 (en) | 2001-05-09 | 2006-07-18 | Clare Micronix Integrated Systems, Inc. | Method for periodic element voltage sensing to control precharge |
| US6828850B2 (en) | 2001-10-19 | 2004-12-07 | Clare Micronix Integrated Systems, Inc. | Method and system for charge pump active gate drive |
| US6995737B2 (en) | 2001-10-19 | 2006-02-07 | Clare Micronix Integrated Systems, Inc. | Method and system for adjusting precharge for consistent exposure voltage |
| US7019719B2 (en) | 2001-10-19 | 2006-03-28 | Clare Micronix Integrated Systems, Inc. | Method and clamping apparatus for securing a minimum reference voltage in a video display boost regulator |
| US7019720B2 (en) | 2001-10-19 | 2006-03-28 | Clare Micronix Integrated Systems, Inc. | Adaptive control boost current method and apparatus |
| US7050024B2 (en) | 2001-10-19 | 2006-05-23 | Clare Micronix Integrated Systems, Inc. | Predictive control boost current method and apparatus |
| US6943500B2 (en) | 2001-10-19 | 2005-09-13 | Clare Micronix Integrated Systems, Inc. | Matrix element precharge voltage adjusting apparatus and method |
| WO2003034576A3 (en) * | 2001-10-19 | 2004-06-03 | Clare Micronix Integrated Syst | Method and system for charge pump active gate drive |
| US7126568B2 (en) | 2001-10-19 | 2006-10-24 | Clare Micronix Integrated Systems, Inc. | Method and system for precharging OLED/PLED displays with a precharge latency |
| JP2005304144A (en) * | 2004-04-08 | 2005-10-27 | Nissan Motor Co Ltd | Fet driving unit and method of controlling fet drive voltage |
| JP4501509B2 (en) * | 2004-04-08 | 2010-07-14 | 日産自動車株式会社 | FET driving device and method for controlling FET driving voltage |
| JP2005328625A (en) * | 2004-05-13 | 2005-11-24 | Fujitsu Ten Ltd | Power unit, voltage control method, and voltage control program |
| US7764113B2 (en) | 2007-07-11 | 2010-07-27 | Panasonic Corporation | Output circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2718258B2 (en) | 1998-02-25 |
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