JPH04170207A - High voltage amplifier circuit - Google Patents

Abstract

PURPOSE:To use a high power supply voltage by stacking longitudinally transistors(TRs) in multi-stage so as to improve the dielectric strength of the amplifier circuit and providing a circuit adjusting a base bias of the TRs stacked longitudinally in interlocking with an output signal of the amplifier circuit. CONSTITUTION:With a level of an input signal set to L, a TR Q1 of an amplifier circuit section 2 is turned off and TRs Q2-Q6 are turned off, then a level of an output signal to an output terminal 1 goes to H. Most of a collector current of the TRs flows to a resistor R1 as a collector current of the TR Q6 at the end of longitudinal stack of the amplifier circuit section 2, then the level at the output terminal 1 is decreased to a potential till the TR Q6 is saturated. When the current amplification TR Q1 of the amplifier circuit section 2 is turned on, a TR Q7 of a bias variable circuit section 4 is simultaneously turned on and most of the collector current flows to a resistor R2 as a collector current of a TR Q11 at the end of longitudinal stack of the bias variable circuit section 4. Thus, a full range output is attained.

Description

[Detailed Description of the Invention] [Field of Application in Industry] The present invention relates to an amplifier circuit, and in 4.11, an amplifier circuit using a bipolar transistor (hereinafter referred to as a transistor) with a low breakdown voltage between emitter and collector is provided. Concerning the configuration of circuits for use at high voltages.

[Conventional technology]

In general, among the characteristics of transistors,
There is a trade-off between operating speed and withstand voltage (1), and if the epitaxial layer and base recessed layer are made shallower in order to increase the operating speed, the withstand voltage of the transistor, especially the emitter-collector withstand voltage, will decrease. I end up.

Therefore, when a common emitter amplifier circuit as shown in FIG. 3 is constructed using transistors, the power supply voltage V
. 0 is limited by the emitter-collector breakdown voltage of the transistor Q.

[Problem to be solved by the invention]

When integrating bipolar transistors, whose power supply voltage is limited by the emitter-collector breakdown voltage as described above, into an integrated circuit, the transistors used for signal processing inside the integrated circuit can be integrated without any particular problems. On the other hand, transistors used for output to external circuits may not be integrated.

That is, if a high power supply voltage is required at the output of the integrated circuit in relation to external circuitry, the circuitry used here (including transistors and circuit elements) cannot be integrated into the integrated circuit.

In such a case, this circuit must be installed externally, and for this reason, the number of components increases, resulting in an increase in mounting space, an increase in man-hours, or an increase in the set number. Problems such as decreased reliability arise.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems in amplifiers using transistors, as described in 1., and to provide an amplifier circuit that can operate at high speed and use a high power supply voltage.

[Means to solve the problem]

The high voltage amplification circuit of the present invention has a first power supply voltage terminal connected in series with a first load circuit and an I. A common emitter/collector load amplification circuit section is provided between the terminal and the second power supply terminal, and the second load circuit is connected in series with the transistor J1, which has a vertically stacked configuration by sequentially connecting the collector and emitter of separate transistors. A bias variable circuit section with a common emitter/collector load connected to the first power supply voltage terminal and the second power supply voltage terminal, and separate dividing circuits connected in series in a vertically stacked configuration. a bias dividing circuit section in which a circuit group is provided between the second load circuit and the second power supply voltage terminal, and a base of a first transistor connected to the output terminal of the amplifier circuit section, The output potential of the variable bias circuit section is inputted to a second terminal connected to a second power supply voltage terminal of the amplifier circuit section.
An external signal is input to the base of the transistor of the first Rt bias variable circuit section and the base of the third transistor connected to the second power supply voltage terminal of the front Rt bias variable circuit section. The bases of the transistors other than the second and third transistors are connected so as to be supplied with the potential at the dividing point of the bias dividing circuit section.

〔Example〕

-〇- Below, optimal embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the circuit +ill configuration of the first embodiment of the present invention.

The configuration of this embodiment includes an amplifier circuit section 2 connected to an output terminal 1, a bias dividing circuit section 3 that applies a bias to the amplifier circuit section 2, and an amplifier circuit that applies a bias according to an output signal of jl≦2. It consists of a bias variable circuit section 4 that adjusts the value.

The amplifier circuit section 2 consists of six NPN transistors connected sequentially to the collectors and emitters of adjacent transistors in a vertically stacked configuration.
Ransistors Q1 to Q3. and a resistance R1 as a load.

The resistor R4 has one end connected to the power supply voltage terminal 5 and the other end connected to the output terminal 1.

For vertically stacked transistors, transistor Q6 is
The collector of the transistor Q1 is connected to the output terminal 1 and the resistor b't: R+, the emitter of the transistor Q1 is connected to the ground terminal 6, and the input signal is input to the base of the transistor Q1.

The variable bias circuit section 4 is composed of five NPN transistors Q7 to Q11 arranged vertically by sequentially connecting the collectors and emitters of adjacent transistors, and a resistor R2 as a load.

One end of the resistor R2 is connected to the power supply voltage terminal 5, and the other end is connected to the base of the transistor Q6 of the amplifier circuit section 2.

In a vertically stacked transistor, the transistor, riQ +
1, the collector is connected to the base of the transistor Q6, the emitter of the transistor Q7 is connected to the ground terminal 6, and the input signal is input to the base.

The bias division circuit section 3 has a configuration in which five resistors R3 to R7 and a diode 1]1 are connected in series.

The resistor R3 has one end connected to the resistor b'CR of the bias variable circuit section 4.
2 and the collector of transistor Q + 1 and the base of transistor Q 6 of amplifier circuit section 2 .

Further, the cathode of the diode D1 is connected to the ground terminal 6.

Then, the four transistors Q2 to Q5 of the amplifier circuit section 2
and four transistors Q8~ of the bias variable circuit section 4
The base of Q11 is connected to four dividing points N, to N4 of the bias dividing circuit section 3.

The operation of this embodiment will be described below.

First, when the level of the input signal is "L I+", the transistor Q of the amplifier circuit section 2 is turned off, and the transistors Q2 to Q6 are also turned off, so the level of the output signal to the output terminal 1 is "H". becomes.

At this time, a power supply voltage V is applied between the emitters and collectors of transistors Q and Ql. A voltage obtained by equally dividing 0 by the resistor 1j'CR2-R7 and the diode D1 is applied.

The value of this applied voltage is set within a range that does not cause breakdown between the emitter and collector of each transistor.

Next, the operation when a high level signal is input to the base of transistor Q will be described.

At this time, transistor Q1 is in the on state, and most of the collector current of this transistor is transferred to the amplifier circuit section 2.
As the collector current of the vertically stacked end transistor Q6 flows through the resistor R1, the potential at the output terminal 1 drops to the point where the transistor Q6 becomes saturated.

In this case, it is undesirable for the amplifier to have its gain and output signal potential limited, so in this example,
A bias variable circuit section 4 is provided so that a full range output signal can be output.

Now, when the current amplification transistor Q1 of the amplifier circuit section 2 is turned on, the transistor Q7 of the bias variable circuit section 4 is also turned on at the same time, and most of the collector current is transferred to the end transistor of the vertically stacked bias variable circuit section 4. Qz
flows through the resistor R2 as a collector current.

Therefore, the power supply voltage V was equally divided by the resistors R2 to R7 and the diode I]1. 0, only the voltage drop across the resistor R2 becomes large, and a full range output signal can be obtained at the output terminal 1.

-10=Here, the diode l]1 connected in series between the resistor R7 and the IX ground terminal 6 increases the voltage drop across the resistor R2 of the bias variable circuit section 4, and outputs the output signal. It was established to further expand the range of

The operation will be explained below. - As mentioned above, when the input signal level is "H11", the output signal level is "LIT", but in this case,
The larger the voltage drop across the resistor R2 is, that is, the lower the base potential of the transistor Q6, the lower the low level of the output signal and the wider the range.

Now, considering the current flowing through each resistor of the bias dividing circuit section 3, the current Il flowing through the resistor R6 is the sum of the base current □ of the transistors Q2 and Q8 and the current I7 flowing through the resistor R7.

That is, IEI"I7+2・Eng.8.

in the same way I, = Ie + 2・IB = I7 + 411 ■.

I, + = IT, +2 ” I n = I? +
6iφI 11■. =I4 +2・I a ” I
7 + 8・IB.

However, (1)3 to I7 are currents flowing through the resistors R3 to R7, respectively.

Therefore, for the sake of simplicity, assuming that the resistance values of all the resistors are equal to R, the voltage drop in each of the resistors R3 to R6 is as follows. e”R・■7+2ΦR fist I I3 =, V R7+ 2・R−I.

vl? 5=v77+4・RIIIn ■R4=vR7+6・R1ll8 ■R3=VR7+8・R・IB.

However, ■33~vI? o is the voltage drop across each resistor.

Therefore, the base potential of the transistor Q6 in FIG. 1, that is, the potential VN5 at the dividing point N5, is as follows, where the potential at the dividing point N is VN, V N5 = V Nl + V RG + V l? 5+V
R4+ V R3=VNI+4・V R7+200R
” I u ■.

Here, considering the difference in voltage drop across resistor R7 with and without diode D, dividing point VN
In □, the potential is the same in both cases, so the voltage drop without diode D1 is greater than that with diode l.
] 1.1 drop in the case of 1, the diode D1
must be larger by the voltage drop at

That is, VR70=VR7D 1'Vp ■
becomes.

However, VR70: Voltage drop across resistor R7 without diode D; VR7D: Voltage drop across resistor R7 when diode D1 is present; Diode 1].

Therefore, as can be seen from equations (■) and (0), regarding the l-transistor Q6, by providing the diode 1), the base potential is lowered by 4·VF compared to the case without the diode D□. Since it is possible to
The low level potential of the output signal is lowered and the range is improved.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing the circuit configuration of a second embodiment of the present invention.

The difference between this embodiment and the first embodiment shown in FIG. 1 is that the vertically stacked transistors constituting the amplifier circuit section 2 and bias variable circuit section 4 in FIG. 1 are each constructed with Darlington-connected transistors. That's what I did.

By doing this, in addition to the effects of the first embodiment, this embodiment can suppress fluctuations in the low-level output voltage due to variations in the current amplification factor h, etc., and enables a full range of output fluctuations. It also has the effect of being able to.

〔Effect of the invention〕

As explained above, the present invention improves the withstand voltage of an amplifier circuit by vertically stacking transistors in multiple stages, and furthermore, the above-mentioned vertically stacked 1-transistor is connected to the output signal of the amplifier circuit. Since a circuit for adjusting the base bias is provided, it is possible to provide an amplifier that can use a high power supply voltage even in a low breakdown voltage process and can output a full range of output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the circuit configuration of the first embodiment of the present invention +1111, FIG. 2 is a circuit diagram showing the circuit configuration of the second embodiment of the present invention, and FIG. 3 is the circuit diagram of the conventional circuit configuration. FIG. 7 is a circuit diagram of the common emitter amplifier circuit without showing the circuit h+, 7 configuration. DESCRIPTION OF SYMBOLS 1... Output terminal, 2... Amplification circuit section, 3... Bias division circuit section, 4... Bias variable circuit section, 5.
...Power supply voltage terminal, 6...Ground terminal.

Claims (1)

[Claims] 1. A first load circuit is connected in series with a first load circuit and a transistor group in which the collectors and emitters of separate bipolar transistors are sequentially connected to form a vertically stacked structure. A second load circuit is connected in series with an emitter-grounded, collector-load amplification circuit section provided between the power supply voltage terminals of the transistor, and a group of transistors configured in a vertically stacked configuration by sequentially connecting the collectors and emitters of separate bipolar transistors. and the first power supply voltage terminal and the second
a bias variable circuit section with a common emitter/collector load provided between the power supply voltage terminals of the second load circuit and the second load circuit; a bias dividing circuit section provided between power supply voltage terminals of the amplifier circuit section, the output potential of the bias variable circuit section being input to the base of a first bipolar transistor connected to the output terminal of the amplifier circuit section; a second power supply voltage terminal connected to the second power supply voltage terminal of the amplifier circuit section;
An external signal is input to the base of the bipolar transistor and the base of the third bipolar transistor connected to the second power supply voltage terminal of the variable bias circuit section, and A high voltage amplifier circuit, characterized in that the bases of bipolar transistors other than the bipolar transistors are connected so as to be supplied with a potential at a dividing point of the bias dividing circuit section. 2. The high voltage amplifier circuit according to claim 1, wherein at least one low impedance voltage generating circuit is connected in series between the divided circuit group and the second power supply voltage terminal. High voltage amplifier circuit. 3. The high voltage amplifier circuit according to claim 2, wherein the voltage generating circuit is a PN junction diode. 4. The high voltage amplifier circuit according to claim 1, claim 2, and claim 3, wherein the first and second load circuits and the dividing circuit are constituted by resistors. .