JPH0416810B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a multiplier between digital numbers, and particularly to a parallel array multiplier, and is suitable for three-dimensionally integrating various internal circuit parts constituting the multiplier. This invention relates to an improvement for defining the arrangement relationship.

<Prior Art> Multipliers for multiplying digital numerical values are almost an essential element for digital computers and signal processing devices.

Therefore, great efforts have been made to increase the speed of this multiplier.

First, such conventional multiplication methods and multipliers will be explained.

To simplify the discussion, the numbers are expressed as positive decimal numbers in 32-bit binary numbers, with multiplicand A, multiplier B,
The product P is expressed as follows.

A≡0.a1a2a3…ai…a32 B≡0.b1b2b3…bj…b32 P≡0.p1p2p3…p64 …(1) Then, for simplicity, without considering the weight of each digit, use the following equation (2). The represented Ui,j is called an operand.

Ui, j=ai・bj...(2) To illustrate the relationship between equations (1) and (2) above, in Figure 2, the diagonal line indicates ai, the horizontal line indicates bj, and those with black circles Each intersection becomes an operand Ui,j. Therefore, the product P obtained by the sum of these operands is
becomes.

There are many multiplication methods to find the total sum, but
Among them, the method using combinational circuits (CLC) is currently available.
It is the fastest. Array multipliers (AMs) are a typical example, and are widely used due to their good compatibility with integrated circuits.

As an example of such an array multiplier AM, FIG. 3 shows a 4-bit multiplicand A where the most significant bit value is al and the least significant bit value is a4, and a 4 bit multiplicand A where the most significant bit value is b1 and the least significant bit value is b4. An example of a 4 bit x 4 bit configuration is shown in which the product P with a certain 4 bit multiplier B is obtained.

The black circles shown in this figure indicate the respective operands Ui and j, similar to the black circles in Figure 2.
In order to simplify the diagram, the diagonal lines for ai and the horizontal lines for bj in FIG. 2 are omitted.

The rectangle designated by the symbol "HA" represents a half adder cell, and the rectangle designated by "FA" represents a full adder cell. As is well known, the half adder cell HA is
For example, the specific circuit configuration shown in FIG. 4 is used to add two inputs x and y, and the full adder cell FA is similarly configured to add three inputs x and y using the specific circuit configuration shown in FIG. Performs addition of inputs x, y, and z. As a result, both have two outputs: a sum output s and a carry output c.

The logical formula of the half adder HA is the following formula (3).

c=xy;s=x+y...(3) Similarly, the logical formula for the full adder FA is the following formula (4).

c = xy + yz + zx; s = x + y + z + xyz ...(4) As the number of digits increases, the capacity of the array multiplier AM described above can naturally be expanded by increasing the number of half adders HA and full adders FA used. However, in such a case, if the basic configuration shown in Figure 3 were simply followed as the number of digits increased, the calculation speed would become considerably slower, and conversely, if the calculation speed was increased beyond a certain value, If you try to secure it for a long time, there will be a limit to the capacity.

Therefore, the inventor of the present invention has attempted to further speed up the multiplication process by parallelizing the multiplication process, even if the concept of the array multiplier AM as described above is basically used. It was done by one of the people.

This is called a parallel array multiplier (PAM), and its principle is as shown in FIGS. 6-8.

Now, as an example, if the number of parallel multiplications is "4", all the operands shown in FIG. 2 are divided into four subgroup areas #1 to #4 as shown in FIG. Divide into.

In that case, generally speaking, if the total number of operands is n (in the case of Figure 2, n = 32 Ensure that there are four operands each.

After doing so, each operand subgroup area #1~
Each partial product is obtained by applying the array multiplier configuration shown in the third figure to #4.

In particular, FIG. 7 shows the configuration of the array multiplier AM1 for the #1 operand subgroup area, but the configuration of the array multiplier AM1 for the other #2 to #4 operand subgroup areas (not shown) is also shown. The same structure will be adopted when the new position is established. In the figure, the rectangular cells marked with "HA" are the half adders described above, and the others are full adders FA.

The output of this array multiplier AM1 is a first output group C1 consisting of a multi-bit carry value group c2,...
Similarly, there are two groups of second output groups S1 consisting of multiple bit sum value groups s2, . A group is obtained.

Therefore, to obtain the final product P,
It is necessary to calculate the sum of these eight types of logical signal group values.

First, as shown in Figure 8, we need to use the well-known carry-save adder, which is constructed by collecting the necessary number of full adders FA in order to convert three inputs into two outputs: sum and carry. Multiple CSAs, in this case,
Six numbers (CSA1 to CSA6) are used to convert the above eight types of logic signal group values into two numerical value strings.

After doing so, the two numerical strings are added using a carry look-ahead adder CLA, which is also well known, to obtain the product P.
get.

In FIG. 8, each output group each consisting of a plurality of bit lines is schematically shown as a single signal line.

<Problems to be Solved by the Invention> The conventional parallel array multiplier described above is excellent in its principle. However, from a practical standpoint, what must be taken into consideration is the layout relationship between each functional circuit part, and even the wiring relationship, when this is realized on a suitable integrated circuit board using actual circuit elements. and various problems associated with them.

Conventionally, various integrated circuits are still largely fabricated in a two-dimensional plane. The parallel array multiplier PAM, which is the subject of this book, is no exception.

Therefore, when realizing this parallel array multiplier on a two-dimensional circuit board, each array multiplier AM1 to AM4 is used to calculate each partial operand group, and a carry save adder CSA1 is used to process their outputs.
~If an optimal layout relationship is not adopted between the CSA6, the carry look-ahead adder CLA for obtaining the final output, etc., the signal propagation path will become unnecessarily long, and the advantages of the above-mentioned principle may be lost. .

However, it is also true that within the two-dimensional plane, no matter how optimal the layout is devised, there is a limit to the simplification and shortening of the signal propagation path that cannot be overcome. be.

For example, let's take a look at the layout relationship that was considered appropriate in the past as shown in FIG. 9 (the connection relationship between AMx and CSAx is different from that in FIG. 8).

As mentioned above, each array multiplier AM1 to AM
From 4, sums S1 to S4 and carry C1 to
Two types of output groups of C4 are output.

Therefore, of course, they require a wiring area.

For example, among the two types of output groups related to #1 array multiplier AM1, one output group S1 requires a dedicated wiring area A11, and the other output group C1 also requires a dedicated wiring area A11. A wiring area A12 is required. Other array multiplier AM2~
The same is true for AM4, and given that a wiring area is required, it is also the same for each output line group of the carry save adder groups CSA1 to CSA6 (the wiring areas are shown in Figure 9). A81～
Only A82 is shown surrounded by imaginary lines).

On the other hand, as mentioned above, each output group from each array multiplier described above is sequentially converted into three groups by a carry-save adder group by taking an appropriate combination among them. Since it has to be converted into two groups, the existence of interconnect areas that overlap each other becomes inevitable.

Specifically, as schematically shown with the symbol "BG" in FIG. 9, a bridge portion that crosses over one another occurs between a certain wiring group and another wiring group.

When you think about it this way, it becomes obvious that even though the parallel array multiplier PAM is excellent in principle, when you try to realize it using concrete circuit elements on a two-dimensional plane board, It can be seen that each wiring portion occupies a considerable area and, as seen in the bridge portion BG, has the disadvantage of requiring a complicated manufacturing process.

This impairs the speed-up of signal processing and becomes a major factor in reducing the degree of integration.

The present invention was made with the main purpose of overcoming these conventional drawbacks; specifically, it is to three-dimensionally integrate parallel array multipliers, and to derive a rational wiring relationship for this purpose. It places emphasis on two points: stipulating the minimum arrangement relationship that can be obtained.

In particular, the reason mentioned above is that when it comes to circuit devices that are simply made three-dimensional without any consideration given to the layout, the shortening rate of the signal propagation path, etc., is not as great as in the two-dimensional era. This is because it is very possible that there will be no change.

<Means for Solving the Problems> In order to achieve the above object, the present invention divides a multiplier into a plurality of parts, calculates in parallel the partial product of each divided partial multiplier and the multiplicand, and then
A plurality of array multipliers, a plurality of carry-save adders that process each output of the plurality of array multipliers, and outputs of the plurality of carry-save adders to obtain a product by summing the partial products. and a carry look-ahead adder that obtains a final product output from the plurality of array multipliers; wherein at least some of the plurality of array multipliers are arranged in a three-dimensional integrated circuit with respect to each other in a height direction. arranged in different functional levels so that the height direction represents the degree of parallelism of operations; and one direction within the two-dimensional plane of the three-dimensional integrated circuit is an input given to each of the array multipliers. Provided is a parallel array multiplier characterized in that the digits of the number are configured so that the other direction orthogonal to the one direction represents the direction of progress of arithmetic processing.

<Function> In general, a three-dimensional integrated circuit is a circuit in which one two-dimensional circuit board has one functional level and is stacked in a plurality of levels in the height direction.

For example, if four circuit configuration planes, each corresponding to a two-dimensional board, are stacked in four layers in the height direction, the first layer, second layer, third layer, and fourth layer are stacked in order from bottom to top. They are called layers, or first functional level, second functional level, third functional level, fourth functional level, etc. An insulating layer may be placed between each functional level as necessary, or a through-hole structure may be used to electrically communicate between the upper and lower functional levels. However, an insulating layer located above or below a functional level may be considered to be included in that functional level.

Accordingly, in the present invention, as is clear from the above-mentioned summary structure, as a minimum limitation, when converting a parallel array multiplier into a three-dimensional one, it is necessary to , are arranged in functional levels that are different from each other in at least some height directions, and the height directions represent the degree of parallelism of operations, and one direction within the two-dimensional plane of this three-dimensional integrated circuit. is configured to represent the digit of the input number to be calculated, and another direction perpendicular to the one direction represents the direction of progress of the calculation process.

The effects of such a configuration are as follows.

In the two-dimensional integrated circuit structure in the conventional example,
It has been stated that more or less bridge portions BG inevitably occur between the output lines from each of the array multipliers AM1 to AM4. This is an unavoidable problem no matter how much consideration is given to the arrangement.

On the other hand, by applying the idea of the present invention, such bridge portions can be easily eliminated if the design is optimally adopted.

Therefore, it is also possible to directly connect the output lines of each array multiplier to the subsequent processing circuit (i.e., the carry-save adder group in the above example) without creating a bridge section. means that the subsequent circuits may be placed closely adjacent to the array multipliers and also to each other.

Therefore, as a result of applying the present invention, the critical path, which is the longest among all the signal propagation paths from input to output, will naturally also be
Get it short enough. In particular, in the parallel array multiplier as a three-dimensional integrated circuit constructed according to the present invention, each of the three-dimensional directions represents the degree of parallelism, the number of digits of the operation number, and the direction of the operation processing. This is also an incidental effect of the fact that the correspondence between the physical structure and circuit configuration of three-dimensional integrated circuits has become extremely clear.

<Embodiment> FIG. 1 shows a configuration example of a parallel array multiplier PAM as an embodiment to which the idea of the present invention is applied.

In the present invention, one of the important structural requirements is to make the parallel array multiplier PAM three-dimensional.
Array Multiplier), that is, a three-dimensional parallel array multiplier.

In this embodiment, each array multiplier AM1, AM2, AM3,
AM4 has four functional levels #1 to #4 that overlap each other in the height direction.
They are all arranged separately in each layer of LV1 to LV4, and in this case, they are arranged in directly adjacent layers above and below.

In this Figure 1, each array multiplier AMx
For the sake of simplicity, the connection paths shown between CSAx and each corresponding carry save adder CSAx and carry look ahead adder CLA are simply shown to show the connection relationship between them, and are not shown in detail. Although it does not indicate a typical connection pattern, the degree of parallelism is shown in the height direction of the three-dimensional structure, the number of digits of the number to be calculated is shown in one direction within the two-dimensional plane, and the number of digits in the two-dimensional structure is It is clearly shown that the other direction perpendicular to one direction represents the direction in which the arithmetic processing proceeds. in this way,
Not only is the correspondence relationship between the physical structure and the internal circuit configuration extremely simple, but since the correspondence relationship is as described above, each array multiplier
It is clearly shown that the lateral connection path in the two-dimensional plane from AMx via the carry-save adder CSAx to the carry-look-ahead adder CLA can be made sufficiently short.

In other words, since there is no room for bridges to occur between lines, for example, in the case shown in the diagram, #4 function level
#4 array multiplier AM4 located in LV4
and carry save adder CSA for #3 array multiplier AM3 located in #3 function level LV3.
1, the #3 array multiplier AM3 located in the #3 function level LV3 above, and the #2 function level LV.
The carry save adder CSA2 related to the #2 array multiplier AM2 arranged in the second array multiplier group can both be arranged very closely to the array multiplier group, and similarly, the carry save adder CSA2 related to the #2 array multiplier AM2 arranged in the save adder
CSA3 to CSA6 and carry look-ahead adder CLA are also
They can be placed in close contact with each other.

In this embodiment, considering the path that takes the maximum delay time from input to output, that is, the critical path described above, #4 array multiplier AM4, #1 carry save adder CSA1,
#4 carry save adder CSA4, #5 carry save adder CSA5, #6 carry save adder CSA6,
The path then passes through the carry look-ahead adder CLA in order.

However, as described above, according to the present invention, these functional circuit parts can be arranged extremely closely together, so naturally the signal lines between them can be made much shorter than in the past, and therefore critical paths can also be shortened. This can be shortened to a satisfactory degree.

If you want to make further modifications to this embodiment, for example, #4 array multiplier AM4 and #3 array multiplier
It is possible to keep it within the same functional level LV3 as AM3. As can be understood from the figure, even if these are accommodated within one two-dimensional plane, there is no need to have wiring portions that intersect with each other.

Therefore, in that sense, the effectiveness of the present invention is demonstrated even in such modified examples by omitting the unnecessary area occupied by the bridge, which was unavoidable in the past. However, if two or more array multipliers are arranged in one plane, the wiring length for one array multiplier may be longer due to the area of the subsequent carry-save adder. It will be done. Therefore,
If this is not desired, it is still better to place all array multipliers in different functional levels, as shown in the illustrated embodiment.

Although it is omitted in the figure, as mentioned earlier, an insulating layer is usually inserted between each functional level, so there is a A well-known through-hole structure or the like may be used for the wiring portion.

<Effects of the Invention> According to the present invention, a parallel array multiplier is made three-dimensional,
Moreover, regarding the combination of the plurality of array multipliers used, if they are arranged two-dimensionally, the array multipliers, which are in a relationship where bridge parts are unavoidable between the output line groups, are at least By arranging them in different functional levels in the horizontal direction, the bridge section can be completely eliminated, and the subsequent functional circuit parts such as the carry-save adder and the carry-look-ahead adder can be integrated into the array multiplier group. They can be placed very close to each other as well as to each other.

In other words, in the conventional configuration, no matter how optimal the design was, the occurrence of bridge sections was unavoidable, and signal delays in the signal propagation path always occurred. Therefore, it is possible to design a circuit configuration without any parts and with an extremely short wiring length without any difficulty.

Therefore, it is possible to obtain a parallel array multiplier with a very simple physical structure, with virtually no need to take wiring delays into consideration, and which will serve as an integrated circuit for the future. As an element, we can have great expectations.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a three-dimensional integrated circuit structure of a parallel array multiplier as an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of operands in multiplication, Figure 3 is an example of the circuit configuration of an array multiplier, Figure 4 is an example of the circuit configuration of a half adder, Figure 5 is an example of the circuit configuration of a full adder, and Figure 6 is an example of the circuit configuration of a full adder. The figure is a diagram explaining the principle of a parallel array multiplier, and FIG. 7 is an example diagram of a circuit configuration of one array multiplier section for obtaining a partial product in a parallel array multiplier.
FIG. 8 is an explanatory diagram of the overall construction method of a parallel array multiplier, and FIG. 9 is an explanatory diagram of a conventional example in which the parallel array multiplier is constructed within a two-dimensional plane. In the diagram, AM, AM1, AM2, AM3, AM4
is an array multiplier, HA is a half adder, FA is a full adder, PAM is a parallel array multiplier as a whole,
CSA1, CSA2, CSA3, CSA4, CSA5,
CSA6 is a carry-save adder, CLA is a carry-look-ahead adder, and LV1, LV2, LV3, and LV4 are respectively functional levels that differ from each other in the height direction in the three-dimensional integrated circuit structure.

Claims (1)

[Claims] 1. After dividing the multiplier into a plurality of parts and calculating the partial products of each divided multiplier and the multiplicand in parallel, the sum of the partial products is calculated to obtain the product. an array multiplier; a plurality of carry-save adders for processing each output of the plurality of array multipliers; and a carry-look-ahead adder for obtaining a final product output from the outputs of the plurality of carry-save adders. A parallel array multiplier having; at least some of the plurality of array multipliers are arranged in functional levels different from each other in the height direction in a three-dimensional integrated circuit, and the height direction is One direction in the two-dimensional plane of the three-dimensional integrated circuit represents the degree of parallelism of the number of inputs given to each array multiplier, and the other direction orthogonal to the one direction A parallel array multiplier characterized in that one direction of is configured to represent the direction of progress of arithmetic processing.