JPH04167613A - Delay adjusting circuit device - Google Patents

Abstract

PURPOSE:To set delay quantity while confirming delay characteristic by using a switching transistor which allows an electrical turn on/off to perform connection/disconnection between an internal signal node and a capacitor. CONSTITUTION:In a delay control circuit device which generates delay by delivering a prescribed signal when the internal signal node 1 to which the capacitor 2 is connected arrives at prescribed potential, the switching transistor 7 is provided between the internal signal node 1 and the capacitor 2. The switching transistor 7 performs an on/off operation by a signal level supplied to the gate of the transistor, and the connection/disconnection between the capacitor 2 connected to the internal signal node 1 and the internal signal node 1 via the switching transistor 7 can be easily performed. In such a way, it is possible to set the delay quantity as confirming the delay characteristic of the delay adjusting circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay adjustment circuit device used in an industrial large-scale integrated circuit (LSI).

[Prior art] Methods for setting delays in circuit devices constituting LSIs can be roughly divided into
There are two methods: changing the value of the R time constant and changing the number of connected inverters. Further, as an example of a circuit capable of adjusting the delay time, a delay adjustment circuit as shown in FIG. 2 has been proposed.

In this delay adjustment circuit, an internal signal node 1 is connected to the other ends of a plurality of capacitors 2, each of which has one end grounded, through a fuse 3 that can be blown with a laser, and a P-channel human-powered signal transistor 4, and the drains of the N-channel second transistor 5 are connected. A voltage detector 6 is connected to such an internal signal node 1, which detects that the internal signal node 1 has reached a predetermined second potential and sends out a signal.

Note that the source of the human input signal transistor 4 is connected to a power source, and the gate is supplied with an input signal.

Further, the source of the second transistor 5 is grounded.

The operation of the delay adjustment circuit configured in this manner will be described below.

When a low (L) level signal is supplied to the gate of the input signal transistor 4, the input signal transistor 4 is turned on and a first potential, which is the power supply voltage, is applied to the internal signal node l. Therefore, each capacitor 2 connected to the internal signal node l is charged via the fuse 3.

Next, when a high (H) level signal is supplied to the gate of the input signal transistor 4, the input signal transistor 4
is in an off state, and on the other hand, the second transistor 5 is in an on state, so that the internal signal node l is connected to the second transistor 5.
The potential of the internal signal node l decreases as the charge in the capacitor 2 is discharged. Then, when the potential of the internal signal node l reaches the second potential, the voltage detector 6 sends out a signal.

Therefore, the time for the potential of internal signal node l to reach the second potential is determined by how many capacitors 2 are connected to internal signal node l.

In this manner, the conventional delay adjustment circuit generates a desired delay by blowing out an appropriate number of fuses 3.

[Problems to be Solved by the Invention] However, as mentioned above, the fuse 3 is blown by a laser device, and there is a problem that a fusing process is necessary. Another problem is that the circuit board must be transported, and the circuit board may be damaged during this transportation process. or,
After blowing out the fuse 3, check the delay characteristics, and if the delay characteristics are incomplete, the above-mentioned process will be required again.

The present invention has been made to solve these problems, and an object of the present invention is to provide a delay adjustment circuit that can easily set the amount of delay while checking the delay characteristics.

[Means for Solving the Problems] The present invention provides a delay adjustment circuit device that generates a delay by transmitting a predetermined signal when an internal signal node connected to a capacitor reaches a predetermined potential. The device is characterized in that a switching transistor is provided between the signal node and the capacitor.

[Function] The switching transistor turns on and off depending on the signal level supplied to the gate, and easily connects and disconnects the capacitor connected to the internal signal node and the internal signal node via this switching transistor. This function allows the delay amount to be set while checking the delay characteristics of the delay adjustment circuit device.

[Embodiment] In FIG. 1 showing an embodiment of the delay adjustment circuit of the present invention, the same components as those shown in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted.

The other end of each capacitor 2 is connected to an internal signal node l via an electrically programmable, for example, F AMOS (floating gate avalanche injection MO9) 7.

Although only three FAMOSs 7 are shown in the drawing, it is of course possible to provide more than three FAMOSs.

The operation of the delay adjustment circuit configured in this manner will be described below.

In order to program one or more FAMOS 7, the input signal node l is connected to the source of an N-channel transistor 9, the drain of which is connected to a power supply 8 with a voltage of 12.5 volts; The source of the F'AMO 97 to be executed is connected to the drain of an N-channel transistor 10 whose source is grounded.

By turning on these transistors 9 and 1O, a desired RAM 097 is programmed. Incidentally, such a programming method is the same as a conventional method.

This FAMOS 7 is programmed by the above-described method when an H level signal is supplied to its gate, and if electrons are stored in the floating gate, it becomes an on state, and conversely, if no electrons are stored, it becomes an off state. Thereby, the internal signal node 1 and the capacitor 2 can be easily connected or disconnected. Therefore, the delay time can be easily adjusted. Note that how this circuit device performs the delay adjustment operation is the same as in the conventional example.

In this way, the internal signal node 1 and the capacitor 2 can be connected or disconnected by simply changing the signal level supplied to the gate of the necessary FAMOS 7, and the desired delay time can be easily obtained.

In addition, since programming of PAMOS7 can be done electrically, there is no need to move the circuit board between devices as in the past, so there is no risk of damage to the circuit board, and delay characteristics can be determined on a single testing system. Delay L while checking
SI can be created.

[Effects of the Invention] As described in detail above, according to the present invention, a switching transistor that can be turned on and off electrically is used to connect or disconnect an internal signal node and a capacitor. No special process is required to connect or disconnect the signal node and the capacitor, and the amount of delay can be set while checking the delay characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the configuration of a delay adjustment circuit device of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a conventional delay adjustment circuit device. l...Internal signal note, 2...Capacitor, 7...
・RAM050 Patent applicant: Ricoh Co., Ltd. Attorney: Blue Image, 1 other person

Claims (2)

[Claims] (1) In a delay adjustment circuit device that generates a delay by sending out a predetermined signal when an internal signal node connected to a capacitor reaches a predetermined potential, a switching transistor is connected between the internal signal node and the capacitor. A delay adjustment circuit device comprising: (2) The delay adjustment circuit device according to claim 1, wherein the switching transistor is a FAMOS.