JPH04167601A - Digital control variable attenuator using field-effect device - Google Patents

Abstract

PURPOSE: To quickly perform the digital control operation by providing a gate control line selectively connected to first plural gate electrodes which selectively apply a digital control signal for supply of a prescribed extent of attenuation between an input electrode and an output electrode. CONSTITUTION: A serial semiconductor area 20 which gives a serial signal path between an input electrode 12 and an output electrode 18 is provided, and a first set of gate electrodes is so arranged that it is operated in the series semiconductor area 20. These gate electrodes control a resistance value supplied between the input electrode 12 and the output electrode 18, and at least one parallel semiconductor areas 16 and 22 are connected between the input electrode 12 or the output electrode 18 and a reference potential conductor 14. For the purpose of controlling a resistance value supplied from the serial signal path to the reference potential conductor 14, a second set of gate electrodes is so arranged that it is operated in parallel semiconductor areas 16 and 22. Thus, high-speed control operation adapted to a monolithic microwave integrated circuit using GaAs semiconductor materials is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates generally to attenuator circuits, and specifically to:
This paper relates to a digitally controlled variable attenuator using a field effect device based on field effect technology.

In modern electronic applications, it is often necessary to utilize attenuator circuits or components responsive to control signals to vary the amount of resistance provided. Such attenuators are used in automatic gain control circuits, positioning systems (pos
It is useful for electronic locating systems, telephone systems, television systems, etc.

In the prior art, electronic variable solid state attenuators for radio frequency (RF) use typically include PI
N diodes were used. PIN diode attenuators can be arranged in various network configurations. A bias control circuit including a field effect transistor (FET) is utilized to bias the PIN diode in response to various analog control signal quantities, thereby causing the PIN diode network to respond to various resistance values. We are able to supply any one of these. Although PIN diode attenuators as discrete components can provide outstanding performance, they require an amount of power that is undesirable in some applications. Additionally, PIN diodes cannot be easily integrated into monolithic circuits.

Other prior art methods of providing electronic variable attenuators sometimes utilize FETs such as gallium arsenide (GaAs) metal semiconductor field effect transistors (MESFETs). These devices can also be arranged in various network formats, and each device can operate without bias. Therefore, almost no power is consumed except during switching operations.

Analog control signals are applied to the gates of these devices to adjust the attenuation level. The resistance provided by each FET is controlled by controlling the depth of the non-depleted channel in the device. unfortunately,
Varying the depth of the non-depleted channel in this way
High intermodulation level (hi
gh intermodulation 1 levels
) tends to result in a nonlinear transfer characteristic. This generates undesired frequency components.

To minimize such harmonic distortion, some prior art attenuators further utilize circuit elements connected to the attenuation FET. Such additions to the circuit undesirably increase cost, size, and weight, and undesirably reduce the reliability of such prior art attenuators. Additionally, these prior art attenuators require precise control of the magnitude of the analog control signal. Achieving such precision is difficult because analog signal quantities tend to drift due to temperature, aging of semiconductors, variations in process parameters between devices, and the like.

Monolithic microwave integrated circuit (MMIC) applications using GaAs semiconductor materials are currently under development due to the high frequency handling and miniaturization capabilities of such circuits. These applications can be achieved using currently commercially available MMICs.
requires an electronically variable attenuator that is compatible with semiconductor manufacturing processes.

The aforementioned prior art attenuators tend to be too expensive to manufacture, occupy too much space, and/or have very high failure rates for some of these applications. have. Also, some complex prior art attenuators that utilize analog control signals tend to operate too slowly to take advantage of the inherent speed characteristics of MMIC circuits.

[Problem to be solved by the invention]

Therefore, one of the objects of the present invention is to provide a digitally controlled variable attenuator using a field effect device that can perform digital control operations at high speed.

One of the other objects of the invention is to provide an integrated circuit which is compatible with MMIC applications and which can be provided in monolithic integrated circuit form.
An object of the present invention is to provide a digitally controlled variable attenuator using a field effect device.

[Means to solve the problem]

A digitally controlled variable attenuator using a field effect device according to an embodiment of the invention includes a series semiconductor region providing a series signal path between an input electrode and an output electrode. A first set of gate electrodes is arranged to operate in series semiconductor regions.

These gate electrodes control the resistance value provided between the input and output electrodes. At least one parallel semiconductor region may be connected between the input or output electrode and the reference potential conductor. A second set of gate electrodes is arranged to operate in parallel semiconductor regions to control the resistance provided to the reference potential conductor from the series signal path.

A gate electrode control line is coupled to selected gate electrodes of the first set and/or the second set of gate electrodes. These control lines selectively apply digital control signals in the form of "1" or "0" to the selected gate electrode to control the conductivity of the gate region connected to that gate electrode, thereby controlling the attenuator. controls the amount of attenuation provided by Each set of gate electrodes has a different width, tailoring the resulting attenuation characteristics to meet the needs of a particular application.

〔overview〕

A digitally controlled variable attenuator using field effect devices is disclosed that is adapted to provide digitally controlled attenuation characteristics. The attenuator may include a first semiconductor region connected in a series path between the input terminal and the output terminal and at least one parallel semiconductor region connected between the series path and the reference potential conductor. can. The first gate electrode is
The second gate electrode is arranged for operation in a series semiconductor region, and the second gate electrode is arranged for operation in a parallel semiconductor region.

The gate electrode control line is connected to the select gate electrode, so that the digital signal can be selectively applied to the gate electrode.
A region of semiconductor material connected thereto can be either conductive or non-conductive and provides a plurality of predetermined amounts of attenuation between the input and output terminals in response to a digital code. I can do it.

A more complete understanding of the invention may be obtained by reference to the detailed description and claims considered in conjunction with the accompanying drawings, in which like reference numbers indicate like parts.

〔Example〕

FIG. 1 is a schematic diagram of a π-type attenuator network IO. The RF multiplied signal to be attenuated is applied to the input pad or terminal I2, which terminal 12 is electrically connected to ground level, or reference potential conductor 14, by a variable parallel resistance element 16 via node 13, and also; It is connected to the output pad, ie, terminal 18, via a series variable resistance element 20.

Further, the parallel variable resistance element 22 connects the node 24 to the ground conductor 1
It is electrically connected to 4.

FIG. 2 illustrates a top view of one possible layout configuration of an electronically variable field effect attenuator device 30 according to one embodiment of the invention. device 3
0 is a π-type configuration IO as schematically illustrated in FIG.
A variable attenuator circuit or network is provided.

Digitally controlled RF attenuator device 30 functions as a circuit-matched attenuator. The amount of RF attenuation is selected using a digitally encoded signal. The particular level of attenuation is selected depending on the arrangement of "I" and "0" digital signals applied to device 30. Device 30 can also be manufactured using a number of different technologies, including standard silicon technology or GaAs technology. For many microwave circuit applications, device 3o can be used as a depletion mode Ga.
It may be useful to manufacture with AsMESFET technology. This technology is also compatible with MMIC manufacturing methods.

More specifically, device 30 is comprised of three semiconductor resistive regions, elements 32, 34 and 36, which correspond to resistors 16, 20 and 22, respectively, in FIG. 1. The ohmic contact 38 connected to the input bat 40 and one terminal of the input parallel resistance element 32 corresponds to the node 13 in FIG. Additionally, ohmic contact 42 is connected to the other terminal of series resistive element 34 and to one terminal of output parallel resistive element 36, generally corresponding to node 24 in FIG. Output pad 44 is also connected to ohmic contact 42.

The semiconductor resistive parallel regions 32 and 36 are terminated by ohmic contact electrodes 46 and 48, respectively. The connection for electrical grounding is a direct via pole connection through the semiconductor substrate of device 30.
This can be accomplished either by a ct via hole connection or also by wire connections from ground conductors 46 and 48 to electrical ground conductors.

Control lines 50, 52, 54 and 56 are connected to various gate electrodes of semiconductor resistive elements 32, 34 and 36. Crosshatched area 60.62.6
4.66 and 68 show an "air gap" crossover structure for the control lines. Each crossover ensures that the control lines do not come into electrical contact with each other in the aforementioned crossover region. Although four gate control lines are illustrated in FIG. 2, a larger number (or fewer) of control lines is easily achievable. Limits are determined by the particular manufacturing technology being applied.

FIG. 3 shows a cross-sectional view of device 3o along line 70 of FIG. More specifically, ohmic contacts 38 and 42 are arranged on surface 71 of semiconductor 72 of resistive element 34 . A rectangle 57 indicates a cross section of the gate electrode 57,
It is integrated with the control line 56. Active N-channel semiconductor layer 72 also includes ohmic contacts 38 and 42.
and supports a rectifying Schottky gate electrode contact 57. Regions 74 and 76 are N+ regions provided under each of ohmic contacts 38 and 42 by known processes.

Schottky gate electrode 57 can be provided in known manner using any suitable combination of metals such as tungsten, gold and titanium. Gate electrode 57 includes a portion of conductor 56 overlying region 34 . The electrode 57 has a free charge (fr
A region 72 of semiconductor material containing ee charges) is depleted. This effect occurs due to the difference in electron affinity between the Schottky metal 57 and the semiconductor at the barrier interface 71. The resulting depleted region automatically exists even under zero bias potential conditions. The depth of the second depletion region can be varied by changing the magnitude of the voltage applied to contact 57.

For example, a sufficiently large negative voltage applied to gate electrode 57 may cause the depletion region to
to form a depletion region surrounded by line 82;
This region renders a portion of device 30 non-conducting.

The voltage required to cause this non-conducting state is defined as the pinch-off voltage (V,). During pinch-off, the resulting carrier depletion forms a region of very high resistance surrounded by line 82 in semiconductor material 72 between ohmic contacts 38 and 42, thereby causing at least A portion of device 30 is rendered nearly non-conductive. Conversely, if a more positive voltage is applied to contact 57, the depth of zero bias depletion region 78 decreases, thereby reducing the depth of gate electrode 57 between ohmic contacts 38 and 42. The conductivity of the lower conductive path portion of the device 30 increases, thereby making at least a portion of the device 30 more conductive. Thus, for the portion of device 30 below electrode 57, a zero bias or positive voltage on gate 57 provides an "on state" and a negative voltage on gate 57 provides an "off state". supply

The magnitude of the resistance of each resistive element 32, 34 and 36 may also be determined by the geometry and material properties of the active semiconductor region. More specifically, the resistance of any individual conduction path is given in first order approximation as follows.

(rho)”1 R-A (1) where (rho) is the bulk resistivity of the active semiconductor material,
L is the distance between the ohmic contacts and A is the cross-sectional area of the active semiconductor region. The bulk resistivity of the semiconductor 72 can be evaluated as follows in a first-order approximation.

However, q is unit charge, U. is the low field mobility of the semiconductor material and N is the free carrier density of the semiconductor. The cross-sectional area of an active semiconductor is the product of the depth of the active region and the width of the active region. maximum active depth
region depth), for example, as illustrated by distance 84 in FIG. The dimensions of series resistor element 34 in FIG. 2 are indicated as "LT";
The dimensions of each parallel resistive element 32 and 34 are designated as "LS". In Figure 2, the width of the maximum operating area is
“WT” for series resistive elements, each parallel resistive element 32
and 36 are displayed as "WS".

Parallel gate electrode 94.96.102.104.11O1
and 112, and the series gate electrodes 57, 114, and 115 connect the gate control lines 50, 52, 54, and/or
or 56 or is integrally formed. Each of these gate electrodes is in rectifying contact to all of the underlying semiconductor material elements 32, 34 or 36.
act).

Each gate electrode operates to modulate the resistance between the ohmic contacts at its ends by varying the conductive cross-sectional area of the underlying semiconductor material. Under normal operating conditions, each of these electrodes will be biased to one of two voltage levels. One of these voltage levels corresponds to the digital value "I". When the gate electrode receives this bias level,
The underlying semiconductor material is in the "on" state. So the current is
It is possible to flow through the underlying semiconductor material of the rectifying electrode. For depletion mode GaAs MESFET technology commonly used for ~1 MIC circuits, the voltage of this digital value "1" is preferably 0.0 volt.

Another voltage level corresponds to the digital value "0". When the gate electrode is at this bias level, the underlying semiconductor is "off" and no current can flow under the electrode. Depression moat GaAsM'
In ESFET technology, the voltage of this digital value "0" is equal to the pinch-off voltage Vp, or even a negative voltage. The pinch-off voltage of a material is a function of the doping density of the semiconductor material and the depth of the active operating region. GaAs
In MESFET technology, the voltage level Vp can be expressed approximately as:

where a is the depth of the active semiconductor region, (ε) is the dielectric constant of the material, and Vbi is the diffusion potential of the rectifying contact, typically about 0.8V.

Control line 50 includes a conductive element 90 that is integrally formed with conductive element 92 and oriented perpendicularly thereto. The conductive element 92 is integrally formed with a gate electrode 94, and the electrode 94 has a dimension W3S extending over the first parallel semiconductor material 32. The conductive element 92 is also integrally formed with another gate electrode 96, and the electrode 96 has dimensions W3S extending over the parallel resistive semiconductor material 36.

Control line 52 also has conductive elements 98 and 100 that are orthogonal to each other. Device 100 includes parallel semiconductor materials 32
A gate electrode 102 having a width W2S extends over the semiconductor material 36, and an electrode 104 having a width W2S extends over the semiconductor material 36. Element 9
8 is integrally formed with a gate electrode 115 having a width of W2T extending above the semiconductor material 34. Similarly, control line 54 includes conductive elements +06 and 1 that are orthogonal to each other.
Including 08. The device 108 is integrally formed with a gate electrode 110 having a width WIS extending over the semiconductor material 32 and also integrally formed with another gate electrode 112 of the same width WIS extending over the semiconductor material 36. . Element 1
06 is integrally formed with a gate electrode 114 having a width W3T extending above the semiconductor material 34. Furthermore, control line 56 includes only one element that is integrally formed with a gate electrode 57 of width W4T extending over semiconductor material 34.

When a control voltage of digital value "0" is applied to control line 56 and a control voltage of digital value "1" is applied to control lines 50, 52 and 54, device 30 of FIG. 44, giving the maximum attenuation amount. In this case, parallel resistance paths 32 and 3
4 is not restricted and the current flows through the gate electrode 9 of the parallel resistor 32.
4. Flows under 102 and 110, and also parallel resistor 3
6 electrodes 96, 104 and 112. However, series resistive path 34 is significantly limited by gate electrode 57. The underlying semiconductor region of electrode 57 is pinched off so that current only flows around the edges of this electrode. Therefore, the effective cross-sectional area for current flow is the product of the depth of depletion region 78 in FIG. 2 and the width of the unrestricted region. From FIG. 2, the unrestricted width is W=WT-W4T. Here, WT is reference number 1
It is displayed as 20. Under this bias condition, the series resistance value will be maximum. More specifically, this combination of maximum series resistance and minimum parallel resistance causes terminal 40
The maximum attenuation will occur between and 44.

Either control line 52 or 54 is "on"
That is, when receiving a voltage with digital value "l" and the remaining control lines receiving "off" voltages, device 30 would be set to an intermediate attenuation magnitude, for example. .

The practical magnitude or value of the resistance provided by the semiconductor elements 32, 34 and 36 can be designed by controlling the doping density of the semiconductor, the operating channel depth and appropriate device dimensions. Because the resistance value corresponding to each given digital state is chosen, a particular amount of attenuation and optimal matching conditions are achieved. More specifically, Table 1 shows the optimal resistance values for parallel resistive elements 32 and 36 that are equal to each other and equal to the value of R2, and
Both optimal resistance values are shown for a resistive element 34 having a resistance equal to . The individual magnitude of attenuation is 50Ω
shown to be compatible with the system.

Table 1 FIG. 4 shows a top view of another embodiment of a digitally controlled RF attenuator device 130. device 130
The basic principles of operation are similar to those already described with respect to the operation of device 30 of FIGS. 2 and 3. Device 130 also provides a π-type network equivalent to circuit 10 of FIG. Device +30 has a different arrangement of control lines and gate electrodes than device 30. Otherwise, the structure of device 130 is identical to that previously described with respect to device 30.

More specifically, device 130 includes gate electrode 12
5.126, +27.128.129.131.13
3 and 135 and includes gate electrode control lines 132, 134, 136 and 138 for driving them, and changing the parallel resistance value represented by semiconductor elements 32 and 36. Control line 140.142.
144 and 146 are gate electrodes 141.14, respectively.
3.145 and 147 are controlled to change the equivalent series resistance value of the semiconductor element 34. The gate electrode of device 130 simply forms a rectifying contact to its underlying semiconductor material. The control voltages provided by these control lines can individually turn the associated gate region "on" or "off". control line 14
0.142.144 and 146 allow the series resistance value to be set to 32 different resistance values. Similarly, the four control lines 132, 134, 136 and 138 drive the gate electrodes connected thereto and the parallel resistive elements 32 and 3.
6 to 32 different resistance values. It is easy to add many more control lines to device 130. Device 130 may require more complex digital codes than device 30, but device +30 may require more complex digital codes than attenuator device 30. Offers considerable versatility.

Intermodulation distortion results from the generation of undesired frequency components due to the nonlinear (linear) transfer characteristics of the device. Intermodulation tends to be worse when the channel is partially pinched off in response to a non-zero bias or control voltage. In current devices 30 and 130, the portion of the channel underlying the gate electrode is either completely pinched off in response to the negative control voltage, Vp;
or conductive in response to a zero level control voltage. There, devices 30 and 130 tend to provide a minimal amount of intermodulation distortion, thereby reducing spurious responses.
Sponse). Additionally, the structures of devices 30 and 130 are arranged to reduce their parasitic capacitance.

What has been described above is attenuator devices 30 and 130 responsive to various digital signals to provide various predetermined amounts of attenuation.

Because devices 30 and 130 operate digitally, they are free from the problems associated with analog attenuators, such as being undesirably overly sensitive to noise, aging, and process-induced changes in device parameters. Not affected. Furthermore, attenuators 30 and 1
30 can be provided in an MMIC structure and incorporates the complex amplitude compensation circuit (comp) often associated with prior art solutions.
lex magnetic compensati
on circuits). This represents significant savings in terms of size and power consumption. Further, the reduced component count of devices 30 and 130 increases reliability.

Furthermore, since the channel portions underlying the gate electrodes of devices 30 and 130 are either completely pinch-off or conductive at zero voltage level C, devices 3o and 130 are partially non-zero in pinch-off mode. Provides less intermodulation distortion than other types of attenuator circuits that utilize FETs driven by control voltages.

Furthermore, the structures of devices 30 and 130 are arranged to have minimal parasitic capacitance, thereby facilitating high speed operation for which GaAs MMIC circuits are well suited.

While the invention has been particularly illustrated and described with reference to a preferred embodiment, those skilled in the art will recognize that changes therein may be made in form and detail without departing from the scope of the invention. You will understand that.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a π-type attenuator network. FIG. 2 is a top view of one embodiment of an attenuator using field effect devices. FIG. 3 is a cross-sectional view of an attenuator using the field effect device of FIG. FIG. 4 is a top view of an attenuator using another field effect device. lO... π-type attenuator circuit network 12, 18... Terminals 13, 24... Node 14... Reference potential conductor (ground conductor) 16, 22
...Parallel variable resistance element 20...Series variable resistance element 30, 130...Variable attenuator (device, RF attenuator device) using field effect device 32, 34 .36...Semiconductor resistance elements 38, 4
2...Ohmic contact 40...
Input pad (terminal) 44... Output pad (terminal) 46.48... Ohmic electrode 50, 52.5
4.56...Gate control line 57...
・(Schottky) Gate electrode (contact) 60, 6
2.64.66, 68...Cross hatch area 7
0...Cross section cutting line 71...Boundary surface 72...N channel semiconductor layers 74, 76...N+ source and drain regions 78
... Depth of the depletion region 80 ... Top surface 82 ... Line 8 representing the expanded part of the depletion region
3... Semiconductor substrate material 84... Thickness 90, 92.98.100.106.108... of N layer 72...
- Conductive element 94, 96.102.104.110.1
12...Parallel gate electrode 114.115...
...Series gate electrode 120...Reference numbers 125, 126.127.128.129.131.1
33.135.141.143.145°147...
...Gate electrode 132, 134.136.138...Gate electrode control line 140, 142.144.146...
... Control line patent applicant Motorola Incorporated agent Patent attorney Hisashi Tamamushi Department 5 ↑ F”IO,1 ＼ F'IO-2

Claims (2)

[Claims] 1. A digitally controlled variable attenuator employing a field effect device responsive to a digital control signal and adapted to provide different predetermined amounts of attenuation, comprising: an input electrode, an output electrode, and the input electrode. a first semiconductor region having a controllable electrical conductivity connected between the output electrodes and having a first terminal and a second terminal; and a first semiconductor region arranged to control the electrical conductivity of the first semiconductor region. selectively applying a digital control signal that varies the amount of attenuation provided between the first plurality of gate electrodes and the input electrode and the output electrode to provide different predetermined amounts of attenuation; and a gate control line selectively connected to a plurality of gate electrodes of the digitally controlled variable attenuator using a field effect device. 2. an input electrode means; an output electrode means; a reference potential conductor means; a first active semiconductor region coupled between the input electrode and the reference potential conductor means; and between the input electrode and the output electrode. a third active semiconductor region coupled between the output electrode and the reference potential conductor means; a third active semiconductor region arranged to operate in the first active semiconductor region; a first plurality of gate electrodes having different gate widths; a second plurality of gate electrodes having different gate widths arranged to operate in the second active semiconductor region; and a second plurality of gate electrodes having different gate widths arranged to operate in the second active semiconductor region. a third plurality of gate electrodes having different gate widths arranged to operate in a region, and connected to a selected one of said gate electrodes for applying a digital control signal; A gate electrode is provided in the form of a monolithic integrated circuit including a plurality of gate control lines adapted to be responsive to said control signal to control the amount of attenuation between said input electrode means and output electrode means. A digitally controlled variable attenuator using a field effect device, suitable for