JPH04167537A - Test chip - Google Patents

Abstract

PURPOSE:To enable the yield of LSI to be easily presumed with high precision by a method wherein the title test chip is provided with a circuit block designed under specified rules and another circuit block performing the same functions having exceeding double area under the same rules as that of the former block so that the yields of respective blocks may be mutually and individually evaluated. CONSTITUTION:The title test chip is provided with a SRAM block 1 and another SRAM block 2 while respective blocks 1 and 2 are independently provided with respective pads such as power supply, address, signal line, etc., so that respective blocks 1, 2 may be composed not to be affected by the mutual defects thereby enabling the yields of respective blocks 1, 2 to be independently evaluated. The test chip is also provided with a process control monitor 3 for the process evaluation. At this time, assuming the areas of SRAM blocks 1, 2 respectively to be A3, A4, A3:A4 1:2 or more, e.g. 1:4. Through these procedures, the yield of LSI can be easily estimated with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a test chip for estimating yield, and particularly to a test chip for easily estimating large-scale LSI yield with high accuracy. Technology Conventional yield estimation focused only on the chip area and considered the yield to be a function of only the chip area.Therefore, test chips for yield estimation were also used that consisted of only a single block. Based on the Poisson distribution assumption, if the device area is A and the yield is Y, it is expressed as Y = EXP(-D A') (1). , D is the defect density specific to the applied semiconductor process. Test chip area A-1 yield Y- is (
Substituting LD into equation 1) On the other hand, take the logarithm of both sides of (1) and set In(Y)=-DA (2) Find D
is substituted into equation (2) to express the yield Y as a function of the device area A. An example is shown in FIG.

From FIG. 3, it is estimated that the yield of an LSI having an area A1 is Yl, but the problem to be solved by the invention is, however, it is difficult to accurately estimate the LSI yield using the method described above.A For example, in FIG. , using the results in Figure 3, the yield of an LSI with area A+ is estimated to be Yl. However, the actual measured value is higher than this, Yl, which causes a yield error Y*-Y+, but this error Ya-Y
+4;L This error may be caused by the fact that the actual defects are not randomly distributed. Ferris-
Prabhu proposed a new defect distribution using a defect cluster model (IEEE Trans, Sem
1cond, Manufact, IEE Transmission 1in * Miko 7'l'99
v:z7yrift, Vo13. No, 2. P54-5
9). If the test chip area is A, the yield is Y- and L, the LSI area is A1, and the estimated yield is Yl, then it can be expressed as where b is the cluster rate of defects, and all defects are reduced to one point. If all defects are concentrated, b = 1; if all defects are randomly distributed, b = o. Therefore, the range of b is 0≦b≦1, and the LSI yield is estimated using equation (3). In order to do this, it is necessary to find the defect cluster rate specific to the applied semiconductor process.In order to find 4b, it is necessary to have multiple test blocks with different areas on the same chip.The conventional test chip uses a single block. In view of this problem, the present invention provides a test chip for easily estimating the yield of a large-scale LSI with high accuracy. According to the present invention ζ, a circuit block designed according to a predetermined design rule, and a circuit block designed according to the same rule as the circuit block 2
Equipped with a circuit block with the same function that has more than twice the area.
The present invention is characterized in that the yield of each block is evaluated independently of each other.The present invention has the above-mentioned configuration to improve the yield of two circuit blocks having different areas (areas of A3 and A3, respectively). Even if Ys and Y4 are obtained at the same time, calculate b by substituting A3, A4, Ys, and Ya into equation (3).Substituting the value of 5b into equation (3) again, area A
Calculate the LSI yield Y1 of 1. As a result, large-scale LSI
SI yield can be easily estimated with high accuracy. Embodiment Figure 1 shows a configuration diagram of a test chip in an embodiment of the present invention. RAM blocks 1 and 12
Equipped with 8K bitS RAM M block 2, each block is equipped with independent pads such as critical address input, inertia line, etc., and even if the configuration is such that a defect in each block does not affect other blocks, each block can be used immediately. Although it is possible to evaluate the yield of blocks independently of each other, there is a process control monitor 3 inside the test chip for process evaluation.
The area of 432Kbit SRAM block 1 is A3. The area of 128Kbit SRAM block 2 is A4.
Then, A s : Aa + l; 4. When the test chip shown in Fig. 1 is prototyped, the yield Y2 of 32Kbit SRAM block 1 and the yield Y2 of 128Kbit SRAM block 2 are
Even if the yield Y of is obtained at the same time, by substituting this into equation (3), we get Ya = [Ys] (A・/A・)1−b, and (4)
Calculate the clustering rate of defects from the formula a Result of prototyping the test chip shown in Figure 1 using a certain process b = 0.5
Next 71. FIG. 2 shows the results of substituting ob=0.5 into equation (3) to determine the relationship between device area and yield. (3
) using A1 and Y・<, t At and Ys of the formula 9
According to the yield estimation curve 11 according to the present invention, the yield of an LSI with an area AS (area As:As=6:1) is estimated to be YS. The actual measured yield of A*: A s = 6.1) is YLll. By the conventional method, A and Y
The broken line in FIG. 2 shows the result of substituting S into equation (1) to find D and substituting it back into equation (1). According to the yield estimation curve 12 according to the conventional method, the LSI yield of area As is estimated to be Y6'; 5 Comparing YLll, Ys, and Ys', Ys
shows a value much closer to YLll than YI', and it is clear that the yield estimation method using the test mask according to the present invention has higher accuracy than the conventional method. The school was made up of blocks only.
Since test blocks with different areas were manufactured separately, it was not possible to determine the defect cluster rate specific to the semiconductor process. However, the test chip of the present invention contains multiple test blocks with different areas. As described above, according to this embodiment, the test block can be prototyped at one time, and the defect cluster rate can be determined.
2KbitS RAM block 1 and 128KbitS
By providing RAM block 2, large-scale LS
In this embodiment, test blocks 1 and 2 are SRAM, or DRAM.

Memory such as SRAM and DRAM is used because it is easy to identify the defective location.If it is not necessary to identify the defective location, other functional blocks such as adders may be used. In the example, using block 1.2 with a memory capacity ratio of 1:4, the power <% 1:2 or l
:3 blocks may be used (~ In this example, two test blocks are used.) Three or more test blocks may be mounted on the test chip (
- It goes without saying that the accuracy of yield estimation improves as the number of test blocks increases. Great practical effect 1. %

[Brief explanation of the drawing]

Figure 1 shows the configuration of a test chip in an embodiment of the present invention. Figure 2 shows the yield estimation results of the same embodiment. Figures 3 and 4 show the results of yield estimation by the conventional method and actual measurements. The diagram showing the difference is 1...32KbitS RA arm 2
...128KbitS RA 3...Process control monitor 11...Yield estimation curve according to the present invention 12...Yield estimation curve according to the conventional method Name of agent Patent attorney Akira Okaji and two others 1st Zutomi 2 figure a AJ A4 Aste'
〕＼゛Ice surface→Beak A Fig. 3＾o Al device resistance flA I4Fig.＾Q At ヂ2

Claims (3)

[Claims] (1) A circuit block designed according to predetermined design rules and a circuit block with the same function designed according to the same rules as the circuit block and having more than twice the area, and the yield of each block can be controlled independently of each other. A test chip characterized by evaluating. (2) A test chip characterized in that an SRAM is used as the circuit block according to claim 1. (3) A test chip characterized in that a DRAM is used as the circuit block according to claim 1.