JPH04162147A - Microprocessor test method - Google Patents

Abstract

PURPOSE:To observe a desired register in a period when no external access is carried out with an external bus shared by providing a selection register which selects a register to be observed. CONSTITUTION:A selection register 108 is divided into an S part 108A and an E part 108B. The registers 106 and 107 are selected with the bit pattern of the part 1088A, and the selected register is connected to a monitor bus 121 via a selector 120. The contents of a PC register can be dynamically observed via the bus 121 serving an internal bus in the timing of a normal operation HiZ state when the part 108B of the register 108 is set at '1' in a test state of a microprocessor 101. That is, the time transitions of the registers 106 and 107 showing the internal states are observed so that the operating transition of the microprocessor 101 is grasped.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a microprocessor testing method for observing the internal state of a microprocessor during testing. Microprocessors with internal cache 4: The more accesses between the LCPU and the cache, the fewer external accesses and the less information that can be observed externally. As the number of accesses to the microprocessor increases, the number of external accesses decreases, and as a result, the amount of information that can be observed externally decreases, making it difficult to observe the changes in the internal operation of the microprocessor. Since the transition of the internal operation of a microprocessor is grasped from information, the decrease in information observed externally makes it difficult to grasp the transition of the internal operation of the microprocessor.

Conventionally, when a malfunction occurs in a microprocessor during a test, it is necessary to observe the contents of the internal registers at the time of the malfunction to infer the cause of the malfunction. The problem to be solved by the present invention is that it is necessary to insert multiple instructions necessary to sequentially observe the contents of internal registers into a test program according to the registers to be observed. It is necessary to secure a CPU register for temporary storage as the instruction is executed, and registers that can be observed by the instruction (i.e., registers that can be read and written are limited to registers that are coded as instructions). Causes of malfunctions in microprocessors (Part 1) It takes a lot of time to trace the process of inferring and examining the internal state transitions from the registers that can be observed by the above instructions, and to detect the causes of malfunctions. In addition, as mentioned above, it is possible to observe the contents of the internal registers of a microprocessor using commands.However, it was difficult to maintain or observe the contents of the registers at the desired timing.・As microprocessors become more highly integrated (cache, TLB, etc. tend to be installed in microprocessors, it becomes even more difficult to observe the internal state, and testing tends to take a lot of time). It is necessary to improve the efficiency of testing/depacking by making it possible to observe more internal states at the appropriate timing. An object of the present invention is to provide a method for testing a microprocessor that is capable of observing the changes in the operation of the microprocessor and understanding the changes in the operation of the microprocessor. A select register that selects a register from among the observation target registers that exist in the processor can be used.By rewriting the select register with software, it is possible to select more observation target registers. The register has a function of sequentially outputting the contents of the register to be observed selected by the select register through an internal bus during an idle period not used in normal operation so that the register to be observed can be observed.

Furthermore, the register to be observed is stored in the FIFO register at the programmed timing, and the
By observing the contents of the IFO register, it is possible to detect the flow of the register to be observed in the test program and to easily grasp the status of the internal operation of the microprocessor.

Effects of the present invention With the above-described configuration, by providing a select register for selecting a register to be observed, it is possible to observe a register to be observed by sharing an external bus during a period when the external bus is not accessed. Further, by storing the register to be observed in the FIFO register at the programmed timing, it is possible to observe the transition of the register to be observed. (Embodiment 1) FIG. 1 shows an embodiment of the present invention. 1 is a block diagram of the microprocessor testing method in FIG. 1. In FIG.
3. Data cache 104, bus-based all device 105
, a select register 108, L CP
There are registers 106 and 107 that hold the internal state in the U102 and instruction cache 103 modules, respectively.
The registers 106 and 107 are selected according to the bit pattern of the three parts 108A.
When connected to 1, 4 is also a monitor enable bit, and when 8 part 108B is 1'', it becomes a mode to externally observe the contents of monitor bus 121. At reset (8 part 108B is set to 0). Here, let us consider the case where the observed registers 106 and 107ζ respectively represent the PC (program counter) and the register that fetches the instruction code. [l]: Input “10” in binary to the select register 108.
000001'' is written. In this case, 58108A corresponds to ``1000000'' in binary, and LE section 108B corresponds to ``1''. 1) ~
(3) From a The operation during the test will be explained below with reference to FIG.

State (1): Part 8 108B of select register 108
When is 11011, it is the normal mode and the CPU 102
When the instruction/data cache hits the address accessed by the CPU 102 and there is no external access, even if the external address bus 122 is in the Hin state, the request signal CIREQII to the instruction cache 103 of the CPU 102 is sent to the instruction cache 103.
When there is a miss to O, the instruction cache 103
U State (2) where the request signal IBREQ115 is output to the bus control device 105 and the address is output via the external address bus 122: Inserting the instruction code [1] into the existing test program Three parts of the select register 108 The most significant bit of 108A! & Since it is an enable signal to connect the register 106 of the CPU to the monitor bus 121, instruction code [1] causes the register 106 to be connected to the monitor bus 121.
Hit against QIIO and data cache 10
4, when the request signal CDREQI 13 to the data cache of the CPU 102 is hit, the hit signal CIHIT 109 of the instruction cache 103 is used to provide the request signal TBREQ 119 for outputting the monitor bus 121 to the outside to the bus control device 105.
The bus control device 1051 to which the request signal TBREQI 19 is applied does not access the outside, unlike state (1).The contents of the internal register 106 of the CPU are output to the external address bus 122 via the monitor bus 121.

(3) Instruction cache 103 power < CPU 102 C
hL for rREQl 10, data cache 104 power (request signal TBR, EQ119i1 for outputting monitor bus 121 to the outside when there is a miss to CDREQ113 of CPU 102)
Data cache request signal DBREQI 17
The data cache 104 L outputs an address to the external address bus 122 in response to the request signal 117.

As described above, in this embodiment, the contents of the monitor bus 121 are output when the external address bus 122 is in the HiZ state, so it does not interfere with the microprocessor's access operation to the outside, and the external address bus 112 is shared. In other words, by setting the E part 108B of the selector register 108 to ``l'''' during testing of the microprocessor, the contents of the internal PC register can be observed sequentially at the timing when it is in the HiZ state during normal operation.
The contents of the PC register are transferred to the monitor bus 121, which is an internal bus.
With this information, it is possible to understand the PC changes in CPU and cache accesses, that is, the program flow, which are completely invisible to the outside, and to improve the efficiency of testing/depacking. Furthermore, since the external address bus 122 is shared and used during observation, there is no need to add a new test bin. It takes almost no time to modify the test program at the time of testing, and the test can be handled by software.

(Embodiment 2) FIG. 2 is a block diagram of a microprocessor testing method according to Embodiment 2 of the present invention. In FIG. 2, parts having the same functions as those in FIG. 1 are given the same numbers and detailed explanations will be omitted. Microprocessor 20 of Example 2
1! ! The microprocessor 101 of Embodiment 1 has a function that allows the contents of a specific register to be observed from the outside via the monitor bus, as well as the ability to sequentially observe the contents of a plurality of registers from the outside via the monitor bus. 4 microprocessors 20 l i & mainly CPU (
The select register 20g? ;As part 208A and 0 part 20
It is divided into 8B and 8 part 208C, and the observation target register 106 and 107 is selected using the decoder 209 and counter circuit 210 according to the bit pattern of 8 part 208A.
Connect the selected register to the monitor bus 121 via the selector 120.
It is a setting section of the counter circuit 210, and also an E section 20g.
C1;i Monitor enable bit, 8 parts 208C
When the bit is 1'', it is a mode for observing the monitor bus 121 externally.
Let's consider the case where the registers 106 and 107i to be observed represent the PC (program counter) and the register that fetches the instruction code, respectively.The instruction codes used in the explanation below are defined. Program instruction code [2]: Write "10100101'" in binary to the select register 208. In this case, S
"101" corresponds to part 208A in binary notation, which is part 0 20.
"0010" corresponds to 8B, n I to LE section 208C
n corresponds.

FIG. 5 is a timing chart showing a microprocessor testing method, and includes states (1) to (3).A The operation during the test will be described below with reference to FIG.

State (1): Part 8 208C of selector register 208
When is 0'', it is the normal mode and the external address bus 12
2 is in HiZ state except when outputting the internal address bus 116.118. In that case JiCPU1
When there is no external access to the address accessed by tcPU 102 and there is a miss in response to the request signal CIREQ110 for the instruction cache of instruction cache 103 and tcPU102, Request signal IBREQ1 to device 105
15 is output to the bus control device 105 and accessed externally (2): Inserting instruction code [2] into the existing test program 8 part 20 of the select register 208
The 3 bits of 8A are enable signals that connect the register 106 of the CPU 102 and the register 107 of the instruction cache 103 to the monitor bus 121, so the instruction code [2] allows registers 106 and 1 to be connected to the monitor bus 121.
The timing at which registers 106 and 107 are connected to the monitor bus 121 is determined by the counter value in the 0 part 208B of the select register 208.
Using the counter value of the unit 208B, the counter circuit 210 counts the internal clock by -1 in rows t and %.
At the timing when the count reaches #0'', the registers designated by the 8 part 208A of the select register 208 are sequentially connected to the monitor bus 1214. That is, the instruction code [2] is executed, and the E part 208C of the select register 208 is executed. When "l'" is written to , the register 106 of the CPU indicated by the 8 part 208A of the select register 208 is connected to the monitor bus 121, and when the count based on the counter value indicated by the 0 part 208B ends, the next Even if the instruction cache register 107, which is an observation register, is connected to the monitor bus 121, the order of the observation target registers connected to the monitor bus 121 is the observation corresponding to "1" in the bit pattern of the 8 part 208A of the select register 208. Determined by the decoder 209 for the target register.Counter circuit 210
Even if the count fL E section is repeated for I+ 111, the 8 section 2 of the select register 208 is
For the plurality of observation target registers specified by 08A, the plurality of registers 106 and 107 are sequentially connected to the monitor bus 121 with a count width specified by the 0 section 208B.

Instruction cache 103 power <, CIREQ of CPU 102
Hit L for IIO and data cache 10
When the request signal CDREQI l 3 for the data cache of the 4k CPU is hit, the hit signal CBREQI O of the instruction cache 103 is hit.
9 is used to send the request signal TBREQI 19 for outputting the monitor bus 121 to the outside to the bus control device 10.
5, the bus control device 1051 to which the request signal is given does not access the outside, unlike state (1), but only outputs the monitor bus 121 to the external address bus 122. All you have to do is observe the data on the address bus 122 during a period when no access is being made (- State (3): Instruction cache 103 power <, CPU 10
When there is a hit to CIREQI 10 of the data cache 104 and a miss to CDREQ 113 of the CPU 102, the data cache request signal DBREQI 1 is output from the request signal TBREQI 19 for outputting the monitor bus 121 to the outside.
7 is prioritized and provided to the bus control device 105, and the internal address bus 118 is output to the external address bus 122 to access the outside.
22 outputs the data on the monitor bus 1221 when the external address 122 is in the HiZ state.
In other words, by setting the E part of the selector register 208 to ``1'', it is possible to see the contents of the internal PC register and cache address in sequence by sharing the contents of the internal PC register and the contents of the address of the cache. , a monitor bus 12, which is an internal bus, is used to sequentially program the contents of PC registers and cache addresses at counter intervals.
1. With this information, it is possible to observe PC fluctuations and cache addresses that are completely invisible to the outside in CPU and cache accesses, and it is possible to directly understand the program flow. Test efficiency can be improved. Furthermore, since the external address 122 is shared and used during observation, there is no need to add a new test bin.Also, the select register 208 can be rewritten by an instruction, so it is only necessary to add one instruction to an existing test program. Testing is possible by changing software (Third Embodiment) FIG. 3 is a block diagram of a microprocessor testing method according to a third embodiment of the present invention. In FIG. , CPU310, and decoding 307
, counter circuit 306, and FrF○ counter circuit 3
The CPU 31O of the microprocessor 301 has registers 302 and 303 to be observed.The instruction codes used in the explanation are defined below.

Instruction code [3]: Write °″10000111″ in binary to the select register 304. The bit pattern is stored in the 8 part 304A of the select register 304.
10'''', 0 part 304B'''00011''°, 8
"'1'" is shown in the portion 304C.

Instruction code [4] + FIF○ register 305 data addressed according to counter circuit 312
The data is sequentially accessed from the address of the IFO register 305 to the outside.

FIG. 6 is a timing chart showing a microprocessor testing method. The operation during the test will be explained below with reference to Figure 6. In the existing test program, at the timing when you want to observe the register to be observed, input the instruction code [3] and send the FIF to the outside.
Insert instruction code [4] at the timing when you want to store the contents of the O register 306.

Now, even if the upper bits of the 8th part 304A of the select register 304 (Yo) are selected, the microprocessor cannot be operated by adding the above test program.
Instruction code [3 codes are executed selector register 304
``0x87'' is written in hexadecimal format, and the counter circuit 306 counts down the count in the 0 section 304B of the select register 304 using the 8 section 304C of the select register 304 as a count start signal.

After the count of the 0 section 304B is completed, the counter circuit 306 generates a count end signal 311, and the counter circuit 312 generates a count end signal 311.
The addressed address is sent to the FIFO register 305 via the FIFO address 309, and the content of the register 302 is transferred to the register indicated by the FIFO address 309 using the count end signal 311 as an enable signal. At this time, the counter circuit 306
The count +;t is repeated as many times as there are registers included in the FIFO register 305. In addition, the counter circuit 3061; A counts in synchronization with the internal clock. That is, when the instruction code [3] is executed, the contents of the register 302 (select register 30
Every 3 clocks, which is the value specified in the 0 part 304B of 4, the contents of the register 302 are changed to F for the number of stages of the FIFO register.
It is stored in the IF○ register 305.

Then, by instruction code [4], FIFO register 3
The contents of the register 302 every three clocks stored in 05 are addressed by the FIF○ counter circuit 312 and sequentially output.

This allows you to easily change the test program without being aware of the registers used in the program, and temporarily stores the contents of internal registers at programmable regular intervals and outputs them externally. The history over time can be observed, and the registers to be observed during testing can be set by changing only the instruction code [3]. This not only improves the observation of the internal state of the microprocessor, but also makes it easier to understand the internal operation of the microprocessor and improve testing/debugging. Further efficiency can be achieved.

Please send the external signal to part 8 of the instruction code [3] above, 304C.
The same effect can be achieved by using this instead of , and timing the writing of the register specified by part 8 of the selector register 304 to the FIFO register 305.
In this case, there is an effect that the timing of sequentially storing the contents of the register specified by the select register 304 in the FIF○ register 305 can be controlled by an external signal.The effect of the present invention is that when the microprocessor is equipped with a cache,
As the number of accesses between the CPU and cache increases, the number of external accesses decreases. However, during testing, the transition in the internal operation of a microprocessor is determined by information observed externally, so as mentioned above, external accesses are reduced. As a result, information observed externally will also decrease.
Forces that make it difficult to observe the transition of internal operations of a microprocessor and increase test time I can,
By sharing the external bus and outputting the contents of the internal register specified by the selector register, it is possible to dynamically observe the changes in the contents of the internal register. By sequentially storing the contents of the internal registers, it is possible to insert instructions to observe the contents of the internal registers without being aware of the registers being used in the test program. It is something that can be observed statically.It plays a role in making testing and debugging of microprocessors, which are becoming more sophisticated and highly integrated, easier and faster.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a microprocessor testing method according to a first embodiment of the present invention. Figure 2 is a configuration diagram of a microprocessor testing method according to a second embodiment of the present invention. A configuration diagram of a processor testing method. FIG. 4 is a timing chart showing a microprocessor testing method in the first embodiment. FIG. 5 is a timing chart showing a microprocessor testing method in the second embodiment. FIG. 6 is a timing chart showing a microprocessor testing method in the second embodiment. 101.201,301...Microprocessor, 1
02.310...CPU (central processing unit), 10
3... Instruction cache x104... Data cache, 105... Bus control device 106, 107, 302
,303...Internal Registry 108,208,304
...Selector register 108A...Select field, 108B...Monitor enable bit, 1
21...Monitor buff, 122,3Cl...Address bar/, 208A...Select field,
208B...Counter field, 208C...
Monitor enable bit, 209.307...Decoder, 210,306...Counter circulation 304A-
...Select field 304B...Counter field, 304C...Monitor enable bit,
305...FIFO Regis Hisashi 308...Name of the data server's agent Patent attorney Akira Okaji and 2 others Figure 1 Figure 2

Claims (3)

[Claims] (1) A microprocessor is equipped with a plurality of registers to be observed that hold internal states, and a select register used to select a register from among the registers to be observed, and the cache is In a state where there is a hit and there is no access to the outside,
The hit signal of the cache is used as an access request signal to the outside of the register of the selected observation target, the register of the selected observation target is output to the outside via an internal bus, and the register of the selected observation target is output to the outside via an internal bus. A microprocessor testing method characterized by observing the registers of a microprocessor. (2) In the microprocessor according to claim 1, a counter feed is installed in a select register used for selecting a register from among a plurality of internal registers to be observed, and a counter feed is installed in a select register used to select a register from among a plurality of internal registers to be observed; A method for testing a microprocessor, characterized in that the value of the counter feed is observed in time series. (3) A microprocessor, comprising a plurality of internal registers to be observed that hold internal states, a select register used to select a register from among the registers to be observed, a counter register, and a FIFO register, and Generate timing for the number of stages of the FIFO register from the count value of the counter register, sequentially store the contents of the register selected by the select register at the timing in the FIFO register, and
A microprocessor testing method characterized by observing the contents stored in an IFO register.