JPH04159826A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To automatically optimize the tap factor of an automatic equalizer against the time as well as the amplitude by making the delay time of a training pattern variable during the training period of the equalizer. CONSTITUTION:This automatic equalizer is constituted of transversal filters 1 and 2, a tap factor control circuit 3, a detector 4, and subtracter circuits 5 and 6. The circuit 3 is constituted of a training pattern generator 31, control circuit 32, switch 33, minimum value detection circuit 34, delay circuit 35, selective circuit 36, and storage circuit 37 and sets the delaying amount of the variable delay circuit 35 which detects the minimum value. Therefore, the automatic equalizer can fully follow a phase change in impulse response caused by the variations of the distance, wire diameter, etc., of the transmission line, as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer for compensating amplitude and phase characteristics of a communication system transmission system.

[Conventional technology]

The transmission system of the communication system is composed of a transmitter 7, a line 8, and a receiver 9, as shown in FIG.

Furthermore, in the receiver 9, a decision feedback type equalizer is often used as the equalization amount 9'1, which is composed of an equalization amount 91 and a detector 92.

The tap coefficients of the decision feedback °-shaped equalization amount are aj(k) and b
j(k), they are expressed by the following equation using the LMS method, for example.

aJ(k):ajl(k)+2α(x(j-L)-y(
J) ) h(J-k)...(1)bj(1):bj
m)+2α(x(j-L)-y(j)) z(j-1
)・(2) Here, X (j) is the transmission signal, y (j) is the output signal of the equalization amount, and z (j) is the output signal of the detector.

Further, j is time, and k and l are variables representing tap positions, respectively.

Further, L indicates a number equivalent to the delay time of the received signal.

As shown in equations (1) and (2), the transmission signal x (j) needs to be known in order to update the tap coefficients.

However, in a real-time system, x (j) is unknown, so before starting communication, the sender sends a certain transmission pattern, and the receiver independently generates the same pattern. By this, the virtual transmitted signal x(j
), and this can be used to update the coefficients.

FIG. 3 is a block diagram showing an example of a conventional automatic equalization amount configured as described above.

In FIG. 3, the conventional automatic equalizer is comprised of transversal filters 1 and 2, a tap coefficient control circuit 3, a detector 4, and subtraction circuits 5 and 6.

As is well known, a transversal filter is a basic circuit of a linear time-invariant time-discrete system that is the basis of digital signal processing, and is composed of a unit delay element, a coefficient multiplier, and an adder.

The transversal filter 1 on the input side is connected to a terminal TI to which an input signal I is input, and includes cascade-connected delay elements DLII to DLIN, which are unit delay elements, and variable gain amplifier circuits AIO to AIN, which are coefficient multipliers. and an accumulation circuit 11 which is an adder.

The transversal filter 2 of the feedback section is similarly connected to the terminal O from which the output signal 0 is output, and is connected to the cascade-connected delay elements DL21 to DL2 and the amplifier circuits A21 to A2.
and an accumulation circuit 21.

The tap coefficient control circuit 3 includes a training pattern generator 31, a control circuit 32, and a switch 33.

Next, the operation of the conventional automatic equalizer will be explained.

First, train the automatic equalizer.

During the training period, the output of the training pattern generator 31 is connected to the subtraction circuit 5 by the switch 33.

Since the outputs A and B of the transversal filter 1.2 are applied to the other input C of the subtraction circuit 5 via the subtraction circuit 6, this difference signal is applied to the control circuit 32 that controls the tap coefficient. It becomes an amplifier gain control signal that sets the tap coefficients of the transversal filters 1 and 2.

The training pattern generation W31 outputs a signal corresponding to x(J - L) in equations (1) and (2) as a training pattern, and the subtraction circuit 5 outputs a signal corresponding to x(J - L) of equations (1) and (2), and the subtraction circuit 5 outputs a signal corresponding to x(J - L) of equations (1) and (2). is subtracted from the output C, and the tap coefficients are set according to equations (1) and (2).

After the tap coefficients of the transversal filters 1 and 2 are set, the output of the detector 4, that is, the output signal O is
Since it almost coincides with the transmitted signal x(j), the tap coefficient can be updated using the output 0 of the detector 4 instead of x(j-L) in equation (I).

[Problem to be solved by the invention]

In the conventional automatic equalizer described above, since the training pattern output from the training pattern generator is generated at a fixed timing set in advance, the number corresponding to the delay time of the received signal, that is, in equation (l) This means that L is fixed. Therefore, there is a drawback that phase changes in the impulse response due to changes in the distance, wire diameter, etc. of the transmission line cannot be adequately followed.

[Means to solve the problem]

The automatic equalization amount of the present invention includes a plurality of unit delay elements having a predetermined unit delay amount connected to an input terminal and connected in cascade, and a unit coefficient circuit connected to the input terminal and the output side of each of the unit delay elements. automatic equalization comprising: a transversal filter having an accumulation circuit to perform equalization processing on an input signal; and a training pattern generation circuit generating a training pattern for initial setting for the transversal filter that simulates a transmission signal. a variable delay circuit that variably delays the training pattern for each unit delay amount; a subtraction circuit that subtracts the output of the variable delay circuit and the output of the transversal filter and outputs a difference signal; a storage circuit that stores the difference signal for each output of the variable delay circuit that is variably delayed for each unit delay amount; a minimum value detection circuit that detects the minimum value of the difference signal stored in the storage circuit; and a delay amount control circuit that sets the delay amount of the variable delay circuit whose minimum value has been detected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the automatic equalizer of the present invention.

As shown in FIG. 1, the automatic equalizer of the present invention consists of a transversal filter 1.2, a tap coefficient control circuit 3, a detector 4, and subtraction circuits 5 and 6, similar to the conventional example. It is configured.

The transversal filter 1 on the input side is connected to a terminal TI to which an input signal I is input, and includes cascade-connected delay elements DLII to DLIN, which are unit delay elements, and variable gain amplifier circuits AIO to AIN, which are coefficient multipliers. and an accumulation circuit 11 which is an adder.

The transversal filter 2 of the feedback section is similarly connected to the terminal TO from which the output signal O is output, and is connected to the cascade-connected delay elements DI, 21 to DL2, and the amplifier circuit A2.
1 to A2, and an accumulation circuit 21.

The tap coefficient control circuit 3 includes a training pattern generator 31, a control circuit 32, and a switch 3 similar to the conventional example.
In addition to 3, the circuit includes a minimum value detection circuit 34, a delay circuit 35, a selection circuit 36, and a storage circuit 37.

The delay circuit 35 is for variable delaying the output of the training pattern generator 31, and is composed of cascade-connected delay elements DL31 to DL3M.

The selection circuit 36 selects the delay time of the delay circuit 35.

The storage circuit 37 holds a difference signal between the output of the selection circuit 36 and the outputs of the transversal filters 1 and 2 via the subtraction circuit 6.

The minimum value detection circuit 34 detects the minimum value of the data in the storage circuit 37.

Next, the operation of this embodiment will be explained.

First, train the automatic equalizer.

During the training period, the switch 33 inputs the training pattern signals from the training pattern generator 31, the delay circuit 35, and the selection circuit 36 to the subtraction circuit 5.

The training pattern generator 31 generates the formula (J) shown in the above-mentioned conventional example as a training pattern.
A signal corresponding to x(j-L) in (2) is output.

The output of the training pattern generator 31 is sent to the delay circuit 3.
The input side of 5 is selected by the selection circuit 36, and is therefore inputted as a signal to the subtraction circuit 5 without delay.

The other input C of the subtraction circuit 5 is the output A and B of the transversal filter 1.2.
Since this difference signal is applied to the control circuit 32 that controls the tap coefficients, it also becomes an amplifier gain control signal that sets the tap coefficients of the transversal filter 1.2.

In the subtraction circuit 5, the output C of the transversal filters 1 and 2 via the subtraction circuit 6 is subtracted from the output of the selection circuit 36, and tap coefficients are set according to equations (1) and (2). The output r(0) of the subtraction circuit 5 at this time is a residual error at the time of convergence, and is written into the storage circuit 37 of the tap coefficient control circuit 3.

Next, the output of the training pattern generator 31 is selected by the selection circuit 36 as the output of the delay element DL31 of the delay circuit 35, and is input to the subtraction circuit 5 after being delayed by the delay time of DL31.

Similarly to the above, the output C of the transversal filter 1.2 via the subtraction circuit 6 and the output of the selection circuit 36 are subtracted, and the residual error r(1) at the time of convergence is calculated by the tap coefficient control circuit 3. It is written into the memory circuit 37.

Similarly, DL32. DL33. ..., the training pattern signal delayed by each delay element of DL3M is selected by the selection circuit 36, and the residual errors r (2), r (3), ..., r (M) at the time of each convergence are It is written into the memory circuit 37.

Residual errors r(0), r(1), ・
. . , the minimum value of r(M) is detected by the minimum value detection circuit 34, and the value of the delay time at that time is set by the control circuit 32.

The control circuit 32 controls the selection circuit 36 to select the output of the delay circuit 35 corresponding to the set delay time value.

Next, using the training pattern delayed by the set delay time, the transversal filters 1 and 2 are again
The calculation of the tap coefficient is performed. Training ends when the tap coefficient settings are completed.

When the above training period ends, the switch 33 switches the subtraction circuit 5 to the output of the detector 4, that is, the output signal O.
When connected to the side, normal operation will occur.

Thereafter, the coefficients are updated using the difference between the signal waveform before the detection of the difference signal C by the subtraction circuit 6 of the output of the transversal filter 1.2 and the waveform of the signal O after the detection as a residual error.

〔Effect of the invention〕

As explained above, the present invention automatically optimizes tap coefficients not only for amplitude but also for time by changing the delay time of the training pattern during the training period for the automatic equalization amount. It has the effect of being able to.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a professional diagram showing a transmission system of a general communication system, and Fig. 3 is a block diagram showing an embodiment of the present invention.
The figure is a block diagram showing an example of a conventional automatic equalizer. 1.2... Transversal fill, 3... Tap coefficient control circuit, 4... Detector, 5, 8... Subtraction circuit, 7... Transmitter, 8... Line, 9 ···Receiving machine,
11° 21... Accumulation circuit, 31... Training pattern generator, 32... Control circuit, 33... Switch, 34... Minimum value detection circuit, 35... Delay circuit,
36... Selection circuit, 37... Memory circuit, 91...
Equalization amount, 92...Detector, Al0-AIN, A21~
A2K...amplifier circuit, DLII~DLIN, DL21
~DL2K. DL31 to DL3M...delay elements.

Claims (1)

[Scope of Claims] A plurality of unit delay elements having a predetermined unit delay amount connected to an input terminal and connected in cascade, a unit coefficient circuit and an accumulation circuit connected to the input terminal and the output side of each of the unit delay elements. and a training pattern generation circuit that generates a training pattern for initial setting for the transversal filter that simulates a transmission signal, a variable delay circuit that variably delays the training pattern for each unit delay amount; a subtraction circuit that subtracts the output of the variable delay circuit and the output of the transversal filter and outputs a difference signal; a storage circuit that stores the difference signal for each output of the variable delay circuit that has been variably delayed by the time; a minimum value detection circuit that detects the minimum value of the difference signal stored in the storage circuit; and a minimum value detection circuit that detects the minimum value. and a delay amount control circuit for setting the delay amount of the variable delay circuit.