JPH04159698A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption, voltage of a ROM by providing switch means at a bit line, and shutting OFF a connection of the bit line to a power source when the potential of the bit line is raised to a predetermined potential. CONSTITUTION:A transistor Tr 6 is turned ON in a state that the potential of a bit line 4 connected to a selected memory cell 3 is 'L'. When an 'L' precharging signal PC is input in this state, a Tr 1 is turned ON, and storing charge is stored in the cell 3 from a power source VCC through the Trs 1, 6. When the potential of the line 4 is raised so as to exceed a threshold value near 1/2VCC of an inverter 11d, the output signal of the inverter 11d becomes 'L', the Tr6 is turned OFF, and a current to the cell 3 is blocked. The drain potentials of the Trs 1, 2 are raised even after the Tr 6 is turned OFF, and when it is raised substantially to the VCC, a Tr 7 is turned OFF, a Tr 8 is turned ON, a Tr 3 is turned OFF, and this state is latched by the operations of the Tr 2 and inverters 11f, 11g. Thus, power consumption, voltage are reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding ROM, in order to reduce power consumption and improve the operating speed of a sense amplifier, the present invention precharges the human line connected to the memory cell based on a precharge signal, and Next, the semiconductor memory device detects the potential of the bit line with a sense amplifier to read out cell information stored in advance in the memory cell, the bit line is connected to the bit line when the potential of the bit line rises to a predetermined potential. and a switch means for cutting off the connection between the power source and the power source.

[Industrial application field]

This invention relates to ROM.

In recent years, microcomputers built into portable electronic devices are required to operate at low voltages using low-voltage power supplies.
It is now necessary for OM to operate with low power consumption and low voltage. [Prior art] The basic structure of a conventional mask ROM is explained with reference to FIG. 3. The cell area for storing cell information is many R
It is composed of an OM cell section 1, each ROM cell section 1 is composed of a large number of cell groups 2, and each cell group 2 is composed of a large number of memory cells 3. A bit line 4 is connected to each memory cell 3, and a selection signal is input from a row decoder 5 to the gates of a plurality of transistors Tr constituting each memory cell 3. The plurality of transistors Tr constituting each memory cell 3 are configured by, for example, one enhancement type N-channel MOS transistor and a plurality of depletion type X-channel MO3h transistors connected in series between the power line 4 and the ground G. All the transistors Tr of the memory cell 3 are turned on based on the selection signal of the row decoder 5, and the hit line 4 is turned on.
Cell information is read out to the bit line 4 depending on whether the bit line 4 is at an L level or whether at least one transistor of the memory cell 3 is turned off and the bit line 4 is maintained at a precharge potential.

Each human line 4 is connected to a transfer gate 7 which is opened and closed based on a selection signal C3I output from a column decoder 6.
The bit line 4 is precharged by the operation of the sense amplifier 8, and the potential of the bit line 4 is detected by the sense amplifier 8. be done. The output signal of each sense amplifier 8 is output to the output circuit 10 via the transfer gate 9 which is opened and closed based on the selection signal C82 output from the column decoder 6.
Cell information of each memory cell 3 selected from the above is output as an H level or L level digital signal.

ROM sense amplifier 8 and output circuit 10 as described above
The configuration of the sense amplifier 8 will be explained according to FIG. 4. The sense amplifier 8 includes an inverter 11a to which the bit line 4 is connected, P-channel MoS transistors T rl and T r2 connected between the input terminal of the inverter and the voltage JMVcc, and an inverter. N-channel MOS that inputs the output signal of
1-transistor Tr3, and a transistor T
The precharge signal PC is input to the gate of rl, and the gate of transistor Tr2 is input to the inverter lla.
is connected to the output terminal of And transistor T
The source of r3 is grounded, and the drain is connected to the output circuit 10 via the transfer gate 9.

The output circuit lO includes inverters 11b and l connected in series.
P-channel MoS transistor Tr4 connected between the input terminal of lc and the same inverter llb and the power supply Vcc.
．． Similarly to the transistor Tri, the precharge signal PC is input to the gate of the transistor Tr4, and the transfer gate is connected to the output terminal of the inverter llb, and the input terminal of the inverter llb is connected to the input terminal of the inverter llb. It is connected to transfer gate 9.

With this configuration, the sense amplifier 8 and the output circuit 10
When an L-level precharge signal PC is input to the circuit, transistors T rl and T r4 are turned on, and the potential of the bit line 4 is raised to the power supply voltage Vcc, that is, to the H level, and the inverter is activated based on the potential of the bit line 4. lla outputs a signal at L level, and the output signal turns on transistor Tr2, and the output signal of inverter lla is latched at L level, and transistor Tr3
is turned off.

Furthermore, by turning on the transistor Tr4, the human input signal of the inverter llb goes to H level, the output signal of the inverter llb goes to the L level, and the transistor Tr4 goes to the H level.
By the operation of r5, this L level output signal is latched, and the output signal of inverter llc becomes H level.

On the other hand, when the precharge operation is completed and the precharge (signal becomes H level), transistors Tri and Tr4 are turned off, and at this time, for example, all transistors Tr of the selected memory cell 3 are on, and the bit line The potential of
When the output signal of inverter lla goes to H level, transistor Tr3 is turned on and the input signal of inverter llb goes to L level, and inverter lla output signal goes to H level.
L level cell information is output from c. Further, when at least one of the transistors Tr of the selected memory cell 3 is turned off and the potential of the bit line 4 is maintained at the H level, the inverter llc of the output circuit 10 outputs an H level signal to the transistor Tr. Information is output. In addition,
Transistors Tr2, latching the output signals of inverters lla and 11b. Tr4 is constituted by a high resistance transistor whose source current is kept small even in its on state.

(Problem to be solved by the invention) However, in the above-mentioned ROM, the memory cell 3 that stores L level cell information constitutes the same memory cell 3 when that memory cell 3 is selected. Since each transistor Tr is all in the on state, if a pre-charging operation is performed in such a state, as shown in FIG. Because the through current Ip flows,
Unnecessary power consumption increases.

In addition, since the inverter 11a that detects the potential of the bit line 4 is near its threshold value or l/ZVcc, the inverter 11a detects the potential of the bit line 4 at the L level after the precharge operation is completed.
To detect the level potential, it is necessary to take the time required for the charge accumulated in the bit line 4 to be drawn to the ground G via each transistor Tr of the memory cell 3 and for the potential of the bit line 4 to drop to around 72 Vcc. Therefore, the operating speed of the sense amplifier 8 is slow. Since the threshold value of the inverter lla is easily affected by variations in the manufacturing process, such as the threshold values of the transistors constituting the inverter lla, variations in the operating speed of each sense amplifier 8 are caused by R
There was a problem that the operating speed of the entire OM was reduced.

An object of the present invention is to provide a ROM that can reduce power consumption and improve the operating speed of a sense amplifier.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. That is, a semiconductor device that precharges a bit line 4 connected to a memory cell 3 based on a precharge signal PC, and then detects the potential of the bit line with a sense amplifier 8 to read cell information stored in advance in the memory cell 3. In the storage device, the bit line 4 is provided with a switch means 12 for cutting off the connection between the bit line and the power supply Vcc when the bit line rises to a predetermined potential.
has been established.

Further, as shown in FIG. 2, the sense amplifier 8 has an input stage composed of a P-channel MOS transistor Tr7 whose source is connected to the voltage ff1Vcc, and the bit line 4 is connected to the gate of the P-channel MOS transistor.

The switch means 12 also includes an N-channel MOS transistor T6 interposed in series with the bit line 4, an input terminal connected to the bit line 4, and an output terminal connected to the gate of the N-channel MOS transistor T6. It consists of an inverter lld.

[Effect]

During the precharge operation of the bit line 4, when the bit line 4 rises to a predetermined potential, the switch means 12 switches the power supply V
Since the connection between cc and bit line 4 is cut off, the power supply Vc
The through current flowing from c to ground via the human line 4 and the memory cell 3 is blocked.

Furthermore, the sense amplifier 8 is configured such that the potential of the bit line 4 is set to the power supply Vcc.
If the threshold height of the P-channel MOS transistor Tr7 is further lowered, it becomes possible to continuously output cell information at the L level of the human line 4.

In addition, when the line 4 becomes H level, the inverter 11 (
] becomes L level, the N-channel MOS transistor Tr6 is turned off, and precharging of the bit line 4 is stopped.

[Embodiment] Hereinafter, an embodiment embodying the present invention will be described with reference to FIG. Incidentally, the same components as those of the conventional example are given the same numbers and the explanation thereof will be omitted.

The bit line 4 connected to the sense amplifier 8 is connected within the sense amplifier 8 to a train of transistors Trl and Tr2 via an N-channel MO5) transistor Tr6, and the bit line 4 is connected to a train of transistors Tr6 via an inverter 11d. connected to the gate of the transistor Tr
6 and the inverter 11d constitute a switch means 12.

The drains of the transistors Trl and Tr2 are connected to the gate of a P-channel MOS transistor Tr7,
The source of the transistor Tr7 is connected to the power supply Vcc, the train is connected to the train of the N-channel MOS transistor Tr8, the source of the transistor Tr8 is grounded to the ground G, and the gate is connected to the precharge signal PC or via the inverter 11e. It is input inverted.

In addition, transistor Tr7. The train of Tr8 is connected to the gate of the transistor Tr3 and the gate of the transistor Tr2, and the inverter 11f,
A latch circuit composed of 11g is connected. Note that the memory cell 3 and the output circuit IO have the same configuration as the conventional example.

Now, in the ROM configured as described above, when the potential of the bit line 4 connected to the selected memory cell 3 is at the L level, the transistor Tr6 is in the on state, and in this state, the precharge signal PC at the L level is When the transistor TrI is inputted, the transistor TrI is turned on and charge is accumulated in the memory cell 3 from the power supply Vcc via the transistors Trl and Tr6. Then, the potential of the bit line 4 rises due to the charged charge, and the potential of the inverter 11d increases to 1/2 Vcc.
When the threshold value in the vicinity is exceeded, the output signal of the inverter 11d becomes L level, the transistor Tr6 is turned off, and further current flow into the memory cell 3 is blocked.

Furthermore, the train potentials of the transistors Trl and Tr2 rise even after the transistor Tr6 is turned off,
When the voltage rises to Vcc, the transistor Tr7
is turned off, and the transistor Tr8 is turned on based on the inverted signal of the precharge signal PC, so the transistor Tr3 is turned off, and this state is latched by the operation of the transistor Tr2 and inverters Ilf and I1g. At this time, the output circuit 10 operates in the same manner as in the conventional example and outputs an H level signal.

When the precharge operation is completed and the L level cell information of the memory cell 3 is read out, all transistors Tr of the memory cell 3 are turned on and the charge on the bit line 4 is drained to the ground G, and the same bit is When the potential of the line 4 falls below the threshold value of the inverter 11d, the inverter 11d
The output signal becomes H level, the transistor Tr6 is turned on, and the charge accumulated in the gate of the transistor Tr7 is drained to the ground G via the memory cell 3.

If such an operation causes a slight potential difference between the gate potential of the transistor Tr7 and the power supply voltage Vcc to the same level as the threshold clavicle of the transistor Tr7, the transistor T
Since r7 is turned on and transistor Tr8 is turned off, the gate potential of transistor Tr3 becomes H level, and this state is latched by the operation of inverters lIg and llf. Then, the transistor Tr3 is turned on and the cell information at L level is output from the output circuit IO.

On the other hand, when the precharge operation is completed and the H level cell information of the memory cell 3 is read out, the transistor T
r6 continues to be turned off, and the transistor Tr7 continues to be turned off by the charge charged during precharging, so that the transistor Tr3 is maintained in the off state, and the output circuit 10 outputs an H signal.
Level cell information is output.

As described above, in this ROM, when the memory cell 3 is precharged, if the bit line 4 or the inverter 11d is charged to a level exceeding the threshold value, the transistor Tr6 is immediately turned off, so the L level precharge signal P
Even if VCC continues to be input, further current is prevented from flowing into the memory cell 3, so that a through current flowing from the power supply Vcc to the ground G can be prevented from occurring.

Furthermore, when reading the L level cell information of the memory cell 3, if the gate potential of the transistor Tr7 drops from the power supply Vcc by the threshold value due to the operation of the memory cell 3, the transistor Tr7 is immediately turned on. Output circuit 10
At the same time, since the precharge potential of the bit line 4 is not the power supply Vcc but the threshold value of the inverter 11d, the time for the storage cell 3 to absorb the charge from the bit line 4 is shortened. , it is possible to speed up the read operation compared to the conventional example.

Further, the gate potential of the transistor Tr7 is set to the power supply Vcc.
If the transistor Tr is lowered by the threshold value,
Since the sense amplifier 7 is turned on immediately, the sense amplifier 8 can be stably operated even if the power supply VCC is lowered to a low voltage.

〔Effect of the invention〕

As described in detail above, the present invention exhibits the excellent effects of reducing the power consumption of the ROM and improving the operating speed of the sense amplifier.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a block diagram showing the configuration of a ROM related to the invention, and Fig. 4 shows a conventional example. It is a circuit diagram. In the figure, 3 is a memory cell, 4 is a bit line, 8 is a sense amplifier, 12 is a switch means, Vcc is a power supply, and PC is a precharge signal.

Claims (1)

[Claims] 1. A bit line (4) connected to a memory cell (3) is precharged based on a precharge signal (PC), and then the potential of the bit line is detected by a sense amplifier (8). A semiconductor memory device for reading cell information stored in advance in a memory cell (3), wherein the bit line (4) is connected to a power source (Vcc) when the bit line rises to a predetermined potential. A semiconductor memory device characterized in that a switch means (12) for cutting off connection is provided. 2. The sense amplifier (8) connects the source to the power supply (Vcc)
2. The semiconductor memory device according to claim 1, wherein an input stage is formed by a P-channel MOS transistor (Tr7) connected to a gate of the P-channel MOS transistor, and a bit line (4) is connected to the gate of the P-channel MOS transistor. 3. The switch means (12) is an N-channel MOS transistor (Tr6) interposed in series with the bit line (4).
and an inverter (11d) whose input terminal is connected to the bit line (4) and whose output terminal is connected to the gate of the N-channel MOS transistor (Tr6). 2. The semiconductor storage device according to 2.