JPH04159690A - Memory - Google Patents

Abstract

PURPOSE:To reduce power consumption corresponding to inactivation by detecting timing of establishing input/output data by data establishment detector, and inactivating part of each circuit system by a control signal from the detector. CONSTITUTION:A data establishment discriminator 1 connected to a node Z of an input side of an output buffer 15 detects a level transition of the node Z, and outputs a control signal FIX when the level is transited. The signal FIX is supplied to a column gate 12, a sense amplifier (write circuit) 13 and a bus gate 14, and operations of the circuits are stopped at the time of level transition. Thus, low power consumption is realized. Further, the signal FIX is supplied to a word line driver 19, and supplied to an equalizing pulse generator 2. The driver 19 temporarily stops the driving operation of the word line by the signal FIX to suppress power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device configured with a semiconductor integrated circuit and from which data stored in memory cells is read.

[Summary of the invention]

The present invention provides a memory device having a configuration in which data is stored in a memory cell, the data is read externally using a read circuit system, and further the data is written using a write circuit system. A data confirmation judgment circuit that generates a necessary control signal from the detection of a level transition is provided, and a part of the circuit system described above is temporarily inactivated by the control signal, or a control signal from the data confirmation judgment circuit is provided. By operating an equalization circuit to balance the voltage between the pair of conductive lines, lower power consumption and higher speed due to reliable equalization are realized.

[Conventional technology]

2. Description of the Related Art Semiconductor memory devices such as RAMs and ROMs are desired to have higher integration density and lower power consumption.

FIG. 7 shows an example of a conventional memory device. This memory device has a memory cell array 101 in which a plurality of memory cells are arranged in a matrix, and data from the memory cell array 101 is amplified by a sense amplifier 102. The data amplified by sense amplifier 02 is transferred to output buffer 104 via bus gate 103. Data is read externally from output buffer 104. Word line drive circuit 106 drives word lines of memory cell array 101.

In order to reduce power consumption, this memory device is provided with a timer circuit 107.

This timer circuit 107 is a circuit for deactivating a part of the circuit within the device after data is determined. A control signal from this timer circuit 107 is supplied to the word line drive circuit 106, sense amplifier 102, and pass gate 103, and stops each of these circuits after data is read from the memory cell. This temporary stop reduces power consumption. Since a latch circuit 105 is provided at the input terminal of the output buffer 104, data can be continued to be output using the latch circuit 105.

However, as shown in FIG. 7, in the method of reducing power consumption using the control signal from the timer circuit +07, the time until the output data is finalized is not controlled by the timer circuit 107. It must be set in advance. At this time, since the settings are made with some margin in mind, at least the time from when the data is actually determined until the control signal is output from the timer circuit 107 results in a loss of power consumption. Malfunction will occur.

Generally, in memory devices, bit line pairs and data line pairs are equalized for the purpose of speeding up, etc., but the timing of equalization is mainly based on pulses from the ATD (address transition detection) circuit. Therefore, the timing of equalization shifts due to a difference in the timing of the pulse, and as a result, a problem arises in that the bit line pairs are not sufficiently balanced.

Therefore, in view of the above-mentioned technical problems, the first object of the present invention is to provide a memory device that reliably achieves low power consumption without problems such as malfunction, and furthermore, a memory device that realizes improved equalization. The second purpose is to provide the following.

[Means to solve the problem]

In order to achieve the above object, one memory device of the present invention is a memory device in which data stored in a memory cell is read out to the outside via a read circuit system, and a level transition in the read circuit system is detected. A data confirmation determination circuit is provided for determining whether the output data is confirmed or not, and a part of the readout circuit system is temporarily inactivated by a control signal from the data confirmation determination circuit. shall be.

Here, the read circuit system is a group of circuits used for reading data, and includes, for example, circuits such as a sense amplifier, various gates, and selectors, an internal data bus, and an I10
Refers to circuits such as lines, output buffers, and word line drive circuits. Further, the data determination circuit detects level transition. In order to determine whether or not this signal transition has occurred, the memory device of the present invention has a structure in which the signal taken into the data determination determination circuit is equalized before the output data is determined. For example,
Inverters with different input/output characteristics can be connected in parallel to detect data transitions.

Further, another memory device of the present invention is characterized in that a data confirmation determination circuit is provided on the writing side, and detects a level transition of a writing circuit system used during writing, and detects a level transition of a writing circuit system used during writing. It is characterized by temporarily inactivating a part of the system. Here, the write circuit system refers to a group of circuits used during writing, such as a write circuit, a selector, or a data bus.

Still another memory device of the present invention is a memory device in which data stored in a memory cell is read out to the outside via a pair of conductive lines and a read circuit system, and detects a level transition in the read circuit system to output data. A data determination determination circuit is provided to determine whether or not the data determination circuit is determined, and an equalization circuit is provided between the conductive wire pair to balance the voltage, and a part or all of the equalization circuit is It is characterized in that it operates in response to at least a signal from the data confirmation determination circuit. Here, the conductive line pair refers to wiring that forms a pair, such as a bit line pair or a data line pair.

[Effect]

By inactivating a part of the read circuit system and the write circuit system using a control signal from the data determination circuit, power consumption can be reduced accordingly. Also,
Since the timing of inactivation is associated with data confirmation, mechanisms such as timers and margin settings are not required, and power consumption can be reduced without any time loss.

In addition, in a memory device where the equalization circuit is activated by a data determination circuit, it is possible to equalize the conductive line pair prior to the address transition timing after the output data is determined, and as a result, reliable equalization is performed. .

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The memory device of this embodiment has a structure in which a part of the read circuit system is inactivated by a control signal from a data determination circuit.

FIG. 1 is a block diagram of the memory device of this embodiment. The memory device of this embodiment has a memory cell array 1O consisting of a plurality of memory cells 11 arranged in a matrix. This memory cell array IO includes a word line WL for row selection and a bit line BL for data transfer.
Although not shown in the figure, the data in each memory cell 11 is connected to a pair of bit lines BL.
It is designed to input and output via .

Adjacent to this memory cell array 10, a column gate 1
2 are arranged. The column gate 12 is a gate circuit for controlling the connection between the memory cell array 10 and the sense amplifier (write circuit) 13, and is provided to be connected to each bit line BL to select a bit line column. . The sense amplifier 13 is an amplifier that detects and amplifies data on the bit line pair, and its output is transferred to the pass gate 14. The output of the pass gate 14 is sent to the output buffer 15
is input. Here, a latch circuit 16 is connected to a node Z, which is an input terminal of this output buffer 15, and an input terminal of a data finalization determination circuit 1, which will be described later, is also connected. Therefore, the memory device of this embodiment detects the level transition of the input terminal of the output buffer 15 to determine whether the data to be output has been determined. Since the latch circuit 16 is connected to the input terminal of the output buffer 15, data can be held in the latch circuit 16, and data can be continuously output even after the pass gate 14 is turned off, for example. The above column gate 12. The sense amplifier 13 and the pass gate 14 are each supplied with a FIX signal from the data determination circuit 1. These column gates 12. Sense amplifier 13. The hash gate 14 is controlled to operate or stop when the FIX signal is at a high level, and as a result, power consumption can be kept low.

The above column gate 12. Sense amplifier 13. For data transfer between the pass gate 14 and the output buffer 15, conductive line pairs (bit line pairs or data line pairs) are used.

An equalize circuit 21 is disposed between the column gate I2 and the sense amplifier 13, an equalize circuit 22 is disposed between the sense amplifier 13 and the pass gate 14, and an equalize circuit 22 is disposed between the pass gate 14 and the output buffer 15. node 2
An equalization circuit 23 is disposed therein. Each of these equalization circuits 21 to 23 is a circuit that shorts the pair of conductive wires by an equalization signal from the equalization pulse generation circuit 2, and the voltages of the pair of conductive wires are balanced by this equalization signal. In particular, in the memory device of this embodiment, a pulse (signal p
EQ), so more reliable equalization is performed.

In the memory device of this embodiment, an address signal is input to the address buffer 17 from the outside. A part of the input address signal is transferred to the column gate 12 and controls the column gate 12.

The other part of the input address signal is transferred to the row selection decoder 18, and the word line drive circuit 19 for driving the word line WL is activated by the signal from the decoder 18. Furthermore, an address transition detection (ATD) circuit 20 is connected to the address buffer 17, and the address transition detection circuit 20 detects transitions of address signals from the outside. The ATD pulse from the address transition detection circuit 20 is sent to the equalize pulse generation circuit 2, which generates an equalize signal EQ using the ATD pulse as a trigger input.

The bit line load/equalization circuit 24 is provided adjacent to the memory cell array 1O, and functions as a bit line load for each bit line arranged in the memory cell array 1O, and also acts as a bit line load for each bit line arranged in the memory cell array 1O. Each bit line is equalized by an equalization signal. Therefore, the bit line is equalized every cycle, or in this embodiment, the equalize pulse generating circuit 2 generates a preliminary equalize signal pEQ in addition to the original equalize signal EQ, and the equalize signal pEQ Since it is also equalized by , reliable equalization is achieved. In addition, the signal from the equalization pulse generation circuit 2 is
The signal is also supplied to the decoder 18 mentioned above. Therefore, the decoder 18 can perform a precharge operation in accordance with the timing of the equalize signal, as will be described later.

Next, the data determination circuit 1 connected to the node Z on the input side of the output buffer 15 will be explained. The data determination circuit 1 detects the level transition of the node Z, and when the level transition occurs, the control signal FIX Output. This control signal FIX is applied to column gate 12. Sense amplifier (
The signal is supplied to the write circuit) 13 and the pass gate 14, and stops the operation of each of these circuits at the time of level transition. Therefore, lower power consumption is achieved. Furthermore, the control signal FIX
is supplied to the word line drive circuit 19 and also to the equalize pulse generation circuit 2.

The word line drive circuit 19 uses the control signal FIX to
The word line drive operation is temporarily stopped, reducing power consumption. In addition, the equalize pulse generating circuit 2 generates a brake equalize signal pEQ having a pulse having a timing preceding the pulse of the original equalize signal, based on the supplied FIX signal.

FIG. 2 shows a specific circuit example of the data confirmation determination circuit 1. Two inverters 31.3 in parallel to the above node Z
2 input terminals are connected. The output terminals of the inverters 31 and 32 are connected to EX through buffers 33 and 34, respectively.
- connected to the NOR circuit 35; The AND circuit 36 compiles a plurality of outputs from each EX-NOR circuit when outputting in parallel. A FIX signal indicating that the output data has been determined appears at the output terminal of the AND circuit 36. In this case, the inverters 31 and 32 are set to have different input/output characteristics, for example, as shown in FIG.
c (indicated by curve 1 in the figure), inverter 3
The threshold voltage vth of 2 is larger than %Vec (curve ■
Indicated by ) is set. Then, if the potential of the node Z is between the threshold voltage Vt1l of the inverter 31 and the threshold voltage of the inverter 32 (for example, Raku Vcc), the output levels of the two inverters 31 and 32 will be different values, and each EX connecting via buffer 33.34
-N.

The output level of the R circuit 35 is a low I level. vice versa,
When the level of layer 1'Z is close to the ground voltage level or the power supply voltage VCCI level, as when the output data is determined, the output levels of the two inverters 31 and 32 become equal, and the EX-NOR circuit: The output level of No. 35 is a high level. EX for all parallel output lines
- When the output level of each of the NOR circuits reaches a high level, the output of the AND circuit 36 also becomes a high level, and a FIX signal is output.

Therefore, by connecting inverters 31 and 32 having such two different threshold voltages vth in parallel to one node Z, it is possible to determine whether the output data has been determined from one novel of that node Z. .

Next, a specific structural example of the decoder 18 will be briefly described with reference to FIG. 4. This decoder 18 has a load transistor 45 made of a PMOS transistor and four decoding transistors 45 to 48 connected in series between the power supply voltage Vcc and the ground voltage GND.
The gates of each decode transistors 45 to 48 are connected to decode lines 44 to -41 provided in parallel.

In this decoder, a precharge transistor 40 is provided in parallel with a load transistor 49, and an inverted equalization signal is supplied to the gate of this precharge transistor 40. Therefore, the equalization signal (EQ
(or pEQ) becomes high level, the precharge transistor 40 is activated and the level of the input terminal of the buffer 50 can be pulled up. Here,
The load transistor 49 is normally on or has a small size in order to suppress the through current. At the same time, the precharge transistor 40 is made relatively large in size in order to perform recovery at high speed. These two transistors 40 and 49 provide both high speed coverage and low through current.

Next, referring to FIG. 6, we will explain the address information regarding the read operation of the memory device of this embodiment. I will explain step by step starting from the beginning.

First, time t. At a stage before this, the data of the previous cycle is determined and output using the latch circuit 16 and the output buffer 15 (the level of node Z (see el).

), the FIX signal (f) is at a high level at this stage.

And time t. Assume that the address signal (a) supplied from the outside to the atno buffer 17 changes. Then, the output of the decoder 18 and the selection of the column gate 12 change depending on the address signal, or the address transition detection circuit 20 changes the A signal depending on the transition of the address signal.
A TD pulse (b) occurs at time t1. The ATD pulse from the address transition detection circuit 20 is supplied to the equalize pulse generation circuit 2, and the equalize pulse generation circuit 2 generates a pulse of the equalize signal EQ(C) at time t. This equalize signal EQ is supplied to equalize circuits 21 to 23 connected to the conductive line pairs between the column gate 12 and the output buffer 15, and equalizes the level of each conductive line.

Furthermore, since the equalization signal EQ is also supplied to the decoder 18 and the bit line load/equalization circuit 24,
Within the decoder 18, high-speed coverage is performed, for example, via a precharge transistor 40 shown in FIG.
The operation of the bit line load/equalize circuit 24 equalizes the line BL to the pin 1 arranged in the memory cell array 10. Due to the operation of the equalize circuit 23, the level (e) of the node Z is set to +AVcc at time t4.

As a result, the level of the FIX signal if+ transitions from a high level to a low level (at time t), indicating a state in which the output data is not determined.

In this manner, in parallel with equalization at various locations within the device, the selected word line WL is boosted at time t by the operation of the word line drive circuit I9. By boosting the word line WL, the memory cells 11 in the selected row of the memory cell array IO are connected to each bit line BL, and the level of the bit line BL is changed according to the data.

Next, by the operation of the sense amplifier 13, the bit line BL
The minute potential difference appearing at the node Z is amplified by the sense amplifier I3, and the level of the node Z (el changes depending on the data) via the pass gate 14.As a result, at time t, the paired data line at the node Z It will be latched to low level and high level respectively.

As the level of the node 2 changes in this way, the FIX signal of the data finalization detection circuit 1 changes from a low level to a high level (time ti). This transition of the FTX signal means the determination of output data. FIX signal is column gate 12
．． The sense amplifiers 13 and 13 are respectively supplied to the pass gates 14 to stop the operation of these circuits. Further, this FIX signal is supplied to the word line drive circuit 19, and at time t from the rise of the FIX signal, the word line drive circuit 19 is also inactivated, and the selected word line WL is The level transitions to a lower level.

Furthermore, the FIX signal of the data confirmation detection circuit 1 is supplied to the equalize pulse generation circuit 2, and in response to the rise of the 20FIX signal, the breaker equalize signal pEQf
A pulse of gJ is generated. In other words, at time t after the output data is determined, the preliminary bracolization signal pEQ(g
) is generated, which is transmitted to the equalizer circuits 21 and 22.
, the decoder 18 and the bit line load/equalization circuit 2
4, and equalization is performed prior to the original equalization operation. This brake equalization operation corresponds to equalization (signal 1c) at the time of address transition. ) will become more reliable, and the margin for timing etc. will also be much better.

As described above, in the memory device of this embodiment, at the time of reading, the FIX signal from the data confirmation determination circuit 1 rises at the timing of confirmation of output data, and as a result,
The column gate 12, sense amplifier 13, word line drive circuit 19, etc. that are part of the read circuit system are temporarily rendered inactive. Therefore, the power consumption of the memory device can be reduced accordingly. Further, the equalization signal pEQ generated in response to the FIX signal allows equalization to be performed prior to the original equalization, which is advantageous for speeding up, etc.

Other Embodiments (FIG. 5) FIG. 5 is a block diagram showing another embodiment of a memory device. In the memory device of this embodiment, a data determination circuit 51 as in the embodiment described above is connected to a local data bus 52 which is a part of the write circuit system. The local data bus 52 connects each bit line B via a column selector 53.
Connected to L. In this embodiment, the local data bus 5
The level transition at step 2 is the timing of data confirmation for writing, and the WFIX from the data confirmation determination circuit 51
Depending on the signal, the operation of, for example, a write circuit, a word line drive circuit, etc. is stopped immediately or after a certain period of time has elapsed.

Therefore, in this embodiment, power consumption in the write circuit system can be reduced.

〔Effect of the invention〕

In the memory device of the present invention, the timing of confirmation of human output data is detected by the data confirmation detection circuit, and a part of each circuit system is inactivated by the fII signal from the data confirmation detection circuit. become. Therefore, power consumption can be reduced by the amount of inactivation. Further, in the memory device of the present invention, the preliminary equalization operation on the conductive line pair can be performed prior to the actual equalization operation by the control signal of the data confirmation detection circuit. Therefore, the equalization timing margin can be increased through reliable equalization, which is advantageous for increasing the speed of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a memory device according to the present invention, and FIG.
Figure 3 is a circuit diagram of a data determination circuit in one example, Figure 3 is a characteristic diagram showing the input/output characteristics of an inverter used in the data determination circuit, and Figure 4 is an example of a decoder used in the above example. 5 is a circuit diagram of a main part of another embodiment of the present invention, FIG. 6 is a timing chart for explaining the operation of an example of the above memory device, and FIG. 7 is a circuit diagram of a conventional memory device. FIG. 2 is a block diagram showing an example. l...Data confirmation judgment circuit 2...Equalize pulse generation circuit IO...Memory cell array 11...Memory cell 12...Column gate 13...Sense amplifier (write circuit) 14...Pass gate I5... ... Output buffer 16 ... Latch circuit 18 ... Decoder 19 ... Word line drive circuit 20 ... Address transition detection circuits 21 to 23 ... Equalization circuit 31, 32 ... Inverter 40 ... Precharge transistor patent applicant Akira Kowa, patent attorney for Sony Corporation (and 2 others) ■Special input/output input/output design for α-binverter Figure 4

Claims (3)

[Claims] (1) In a memory device in which data stored in a memory cell is read out to the outside via a read circuit system, a method for detecting level transitions in the read circuit system to determine whether or not output data has been determined. 1. A memory device comprising a data finalization determination circuit, and a part of the reading circuit system is temporarily inactivated by a control signal from the data finalization determination circuit. (2) In a memory device in which data stored in a memory cell is read out to the outside via a pair of conductive lines and a readout circuit system, it is determined whether the output data is determined by detecting a level transition in the readout circuit system. A data confirmation determination circuit for making a determination is provided, and an equalization circuit is provided between the pair of conductive lines, and part or all of the equalization circuit operates in response to at least a signal from the data confirmation determination circuit. A memory device characterized by: (3) In a memory device that is capable of writing and reading data to and from memory cells, detecting level transitions in the write circuit used during writing and temporarily inactivating part of the write circuit. A memory device characterized by: