JPH04157428A - Thin film transistor substrate, liquid crystal display panel and liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent a defect from harmfully working practically in driving, even if a TFT substrate is defective, by making the first capacitance 10 times as large as or lager than both the second and third capacitance. CONSTITUTION:A gate electrode 4 is electrically connected to a gate wire 2 through the first capacitance 3. The value Cc of the first capacitance 3 is 10 times as large as or larger than both value Cgs of the second capacitance 5 generated between the gate electrode 4 and a source electrode 8 and the value Cgd of the third capacitance generated between the gate electrode 4 and a drain electrode 9. Even if a short circuit occurs between a gate G and source S or between the gate G and drain D due to the first capacitance Cc between the gate wire 2 and gate electrode 4, a short circuit does not occur directly between the gate wire 2 and source electrode 8 or between the gate wire 2 and drain electrode 9. By this constitution, even if a defect occurs in a gate insulation film due to dust, for example, it practically does not work harmfully.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) substrate, a liquid crystal display panel using the same, and a liquid crystal display device using the liquid crystal display panel.

[Prior Art] Conventionally, TPT substrates have been used in liquid crystal display devices and the like. To make display devices larger and cheaper, T
There is a need to reduce defects in the PT insulating film. As a TPT substrate with fewer defects in the insulating film, a TPT substrate whose gate insulating film is a #@green film obtained by anodizing Ta or A1 is known. Also. JP-A-61-133662 describes a TPT substrate using a two-layer insulating film of SiN:H and an anodized film of gate line metal. [Problems to be Solved by the Invention] The above-mentioned prior art provides a TPT substrate with fewer defects to some extent. However, it is difficult to completely eliminate defects. Therefore, line defects, which are fatal defects, may occur in display devices and the like. Furthermore, it is difficult to completely eliminate the occurrence of point defects. The object of the present invention is to provide a TPT substrate, a liquid crystal display panel using the TPT substrate, and a liquid crystal display panel using the same, in which even if the TPT substrate has a defect, the defect does not appear to be a problem from the perspective of driving. The purpose of the present invention is to provide a liquid crystal display device with a high level of performance. [Means for Solving the Problems] The above objects include (1) a gate electrode disposed on a substrate; a semiconductor layer provided on the gate electrode via a gate insulating film for forming a channel; In a thin film transistor substrate having a thin film transistor including a source and drain electrode for flowing current through the semiconductor layer, the gate electrode is electrically connected to the gate line via a first capacitor, and the capacitance value of the first capacitor is is 10 times the capacitance value of the second capacitance generated between the gate electrode and the source electrode and the capacitance value of the third capacitance generated between the gate electrode and the drain electrode. A thin film transistor substrate characterized by having the above value. (2) The thin film transistor substrate described in 1 above, wherein the dielectric film forming the first capacitor includes at least an anodic oxide film of the gate line; (3) the thin film transistor substrate described in 1 or 2 above. (4) a thin film transistor substrate according to 1 above, wherein the semiconductor layer is made of amorphous silicon;
．． (5) The thin film transistor substrate according to any one of 1 to 4 above, wherein the thin film transistor and the first capacitor are provided at different positions in a plane. In the substrate, in order for the thin film transistor to function as a switching element, the gate line is connected to a scanning line terminal, and the drain electrode is connected to a signal line arranged to intersect with the gate line. Characteristic thin film transistor substrate (6) The thin film transistor substrate according to any one of 1 to 5 above, and disposed opposite thereto. A liquid crystal display panel characterized by having at least a substrate having a counter electrode and a liquid crystal disposed between them, (7) the liquid crystal display panel described in 6 above, and for providing a video signal to the liquid crystal display panel. A video signal drive circuit, a scanning circuit for providing a scanning signal to the liquid crystal display panel, and a control circuit for providing information for the liquid crystal display panel to the video signal drive circuit and the scanning circuit. This is achieved by using a liquid crystal display device. Regarding the value of the first capacitance at (1) L,
This will be explained using FIGS. 10, 11, and 17. Figure 10 shows the value of the first capacitance (Cc) and the second capacitance (Cgs) provided between the gate line and the gate electrode when the drain potential is ○■ and a voltage is applied to the gate line. This is the result of examining the voltage actually applied to the gate electrode with respect to the ratio of . The transmission rate on the vertical axis is the ratio of the voltage applied to the gate electrode to the voltage applied to the gate line. As can be seen from the figure, the transmission rate improves as the capacitance ratio increases. Figure 11 shows the ratio of the first capacitance (Cc) to the third capacitance (Cg d ) when -20V is applied to the gate line and 15V is applied to the drain, and the actual value at the gate electrode. This is the result of examining the voltage (Vg) applied to. This result also shows that as the capacitance ratio increases, the potential of the gate electrode becomes closer to the voltage applied to the gate line. In both figures, it can be seen that when the capacitance ratio is small, slightly increasing the capacitance ratio has a large improvement effect of 5, but the absolute value is insufficient. It can be seen that when the capacitance ratio is around 10, the potential of the gate electrode also takes a value close to the voltage applied to the gate line, and even if the capacitance ratio is increased beyond that value, no significant improvement effect can be obtained. In FIG. 11, -20V is applied to the gate line, but in actual TPT operation, the most severe driving condition is when a negative potential is applied, and the above parking conditions are taken into consideration. Further, FIG. 17 shows the gradation display ability of the liquid crystal display panel. The gradation display capability is determined by the voltage resolution of the TPT itself and the switching characteristics of the liquid crystal for the video signal transmitted by the TPT. The results shown in the figure are obtained when a twisted nematic liquid crystal, which is commonly used in liquid crystal display panels, is used and λ is used. Since television requires at least 16 gradations, it can be seen that the TPT capacitively coupled to the gate requires a transmission rate of 80% or more. From this, when comparing the value of the first capacitance with the value of the second capacitance and the value of the third capacitance,
It can be said that it is particularly important to double or more.

[Effect]

By providing the first capacitance between the gate line and the gate electrode, even if a defect occurs in the gate insulating film due to, for example, dust, the gate insulating film can function without any problem. This will be explained with reference to FIG. FIG. 2(a) shows a TPT circuit according to the present invention. Here, the first
By providing a capacitance (Cc) of gate (G)
Even if a short-circuit defect occurs between the source (S) or the gate (G) or the drain (D), there will be no direct short-circuit between the gate line and the source electrode or between the gate line and the train electrode. Further, even if a short circuit occurs due to a defect in the first capacitor, the circuit type will be similar to that of the conventional TPT shown in FIG. 1(b), and the problem will not materialize. The value of the first capacitance (Cc) is at least 10 times the value of the second and third capacitances (Cgs and Cgd) occurring between the gate electrode and the source electrode or between the gate electrode and the drain electrode. By doing so, a sufficient potential can be transmitted to the gate electrode, and it can be driven in the same way as a normal TPT.

【Example】

Example 1 An example of the present invention will be described with reference to FIGS. 1 to 4. First, the manufacturing method will be explained. FIG. 1(c) is a plan view of the device, FIG. 1(a) is a sectional view of the transistor section at the position indicated by line AA', and FIG. 1(b) is a cross-sectional view of the transistor section at the position indicated by line BB'. FIG. 3 is a cross-sectional view of the capacitor section. Note that the relationship between the plan view and the sectional view is the same in the following figures, but the AA' line and the BB' line are not shown in order to simplify the plan view. 0.2 μm of A1 is deposited on the insulating substrate 1 by vacuum evaporation method.
The gate line 2 was formed by depositing the film to a thickness of 100 nm and patterning it by a conventional photoetching method (FIG. 1). Thereafter, a positive photoresist 0FPR-800 was applied to a thickness of 2 μm, and ultraviolet rays were selectively irradiated using a desired photomask. This was developed and post-baked to form a mask at the position indicated by the broken line in FIG. 2(c). Selective anodic oxidation was performed using this photoresist as a mask. The oxide film growth region in anodic oxidation needs to be grown at least in the capacitor formation portion. In this example, the dotted line area was masked with photoresist, and an oxide film was formed on the gate line 2 other than this area. The method of applying voltage in this anodic oxidation is to gradually increase the voltage at a current density of 50 μA / cm 2 at the initial stage, and when the voltage reaches 100 V, a constant voltage (1
00V) was applied for 15 minutes. As a result, the Al gate l without photoresist is
&! 2 to a thickness of about 140 nm. This oxide film is used as the first capacitor #@edge film 3 (
dielectric film). Next, Cr was deposited to a thickness of 0.2 μm by a sputtering method, and this was processed by a normal photoetching method to form a gate electrode 4 (Figs. 2(a), (b), and (c)).
)) - Here, for the step part where Cr crosses over the gate line 2, as in the normal method, A1
was placed to prevent step breakage, but in order to provide a detailed explanation of the present invention, explanation and illustration of a specific method are omitted (the same applies to the following examples). Here, in the portion where the gate line 2 and the gate electrode 4 overlapped, a first capacitor having a structure with the insulating film 3 interposed therebetween was formed. This capacitance value (Cc) is determined by the thickness of the insulating film 3 and the area of the overlapped portion of the gate line 2 and gate electrode 4, and is designed to be 3PF here. Next, a SiN film with a thickness of 0.3 μm was formed using the plasma CVD method.
The film (gate insulating film 5) is further coated with a film thickness of 0.2
A semiconductor layer 6 of amorphous silicon (a-Si) with a thickness of μm is further added with P of lwt. An ohmic contact layer 7 made of n-type amorphous silicon doped with 50 nm in thickness was deposited. Next, the ohmink contact N7, the semiconductor layer 6, and the gate insulating film 5 were each processed by photoetching to form the shapes shown in FIGS. 3(a), (b), and (c). Further, a portion of the gate insulating film 5 was removed from the portion where the oxide film was not grown on the gate line. This portion is shown as a contact hole 10 in FIG. 3(c). The processing of the gate insulating film is performed in order to apply a potential to the gate line and perform measurement, and does not limit the gist of the present invention. What is particularly important up to this point is that the regions where the first capacitor and TPT are formed are separated from each other in a plane. Next, Cr with a thickness of 100 nm and A1 with a thickness of 0.5 μm are sequentially deposited by a sputtering method, and each of these is processed by a photoetching method to form a source electrode 8 and a drain electrode 9. The ohmink contact layer 7 between the drain electrodes 9 was removed using the source electrode 8 and drain electrode 9 as masks (
Figure 4 (a), (b), (C)). Here, the gate electrode 4, the source electrode 8, and the drain electrode 9 overlap each other with the gate insulating film 5, semiconductor layer 6, and ohmic contact layer 7 interposed therebetween. The capacitance value (Cgs) at the overlapping portion of the gate electrode 4 and the source electrode 8 is approximately determined by the respective film thicknesses of the gate insulating film 5 and the semiconductor layer 6, and the area of the overlapping portion. The same applies to the capacitance value (Cgd) on the drain electrode side. In this example, both Cgs and Cgd were set to 0.2 pF. That is, the capacitance value (Cc) of the first capacitor is
and the capacitance value (Cgs) of the third capacitor and (C g d )
15 times. Note that C.I. is also formed on the contact hole 10 on the gate line. r
．． A gate terminal 21 was formed by covering it with Al. Thereafter, a TPT was formed by covering it with a SiN passivation film or the like using a conventional method. The thin film transistor thus obtained was evaluated as follows. The source electrode is set to O, a constant voltage of IOV is applied to the train electrode, and -20V is applied to the gate terminal 21.
A voltage from +20 V to +20 V was gradually applied, and the current flowing from the drain electrode to the source electrode, ie, Ids, at this time was measured. On the other hand, for comparison, a separate device was manufactured in which the gate insulating film above the first capacitor portion was partially removed. This device has a voltage applied directly to the gate electrode. A voltage from -20 V to +20 V was gradually applied to the gate electrode 4 of this device in the same manner as applied to the gate terminal 21, and the current flowing from the drain electrode to the source electrode, ie, I dso, was measured. When IdS obtained by measurement and Idso were compared, there was almost no difference between the two when the applied voltage was -20V and when +20V was applied, indicating that the TPT with the first capacitance of this example performed well. It was confirmed that he was embarrassed. Further, although many TPTs having the above structure were fabricated on one substrate, there were no short circuits between the gate line and the source electrode or between the gate line and the drain electrode. Therefore, it was confirmed that the TPT according to the present invention has a particularly low occurrence of defects. Example 2 A second example of the present invention will be described using FIGS. 5 to 8. 0.1 μm of Cr is deposited on the insulating substrate 1 by vacuum evaporation method.
A SiN film is deposited to a thickness of 0.35 μm and patterned by a normal photoetching method to form a gate 4!2. Further, a SiN film is deposited to a thickness of 0.35 μm by a plasma CVD method to form an insulator for the first capacitor. 5 (a) and (b).
) and (c). Next, Cr was deposited to a thickness of 0.18 μm by sputtering, and then patterned by photoetching to form gate electrodes 4 as shown in FIGS. 6(a), (b), and (c). After this, a film of S with a thickness of 0.25 μm was formed by plasma CVD method.
A gate insulating film 5 made of iN is followed by a semiconductor layer 6 made of amorphous silicon (a-5i) with a film thickness of 0.2 μm, and a film thickness 4 doped with P by Q, 8 wt%.
An ohmic contact N7 made of n-type amorphous silicon with a thickness of 0 nm was deposited. Next, the ohmic contact layer 7, the semiconductor layer 6, and the gate insulating film 5 are formed by photoetching.
were processed to obtain the structures shown in FIGS. 7(a), (b), and (Q). Further, a contact hole 1o was formed in the same manner as in Example 1. In the following, the source electrode 8 and the train electrode 9 are formed in the same manner as in Example 1, and as shown in FIGS. 8(a), (b), and (c).
A TPT with the structure was obtained. In this embodiment, the capacitance value Cc of the first capacitor is 2PF, and the capacitance value Cc of the first capacitor is 2PF.
and the capacitance values Cgs and Cgd of the third capacitor are both O, l.
It was set as pF. Therefore, Cc is 20 times greater than Cgs and Cgd. When we measured the transistor characteristics of this TPT, we found that the characteristics were almost the same when a gate voltage was applied to the gate electrode and when a voltage was applied to the gate line. There were no TPTs that were short-circuited between the line and the drain electrode or between the gate line and the source electrode. Embodiment 3 A third embodiment of the present invention will be described with reference to FIGS. 12 to 15. #@ On the edge substrate 1, 0.2μ of Ta is deposited by vacuum evaporation method.
The gate line 2 is formed by depositing the film to a thickness of m and patterning it by a normal photoetching method, as shown in FIG. 12(a).
The shapes shown in (b) and (c) were used. Thereafter, photoresist was applied to a film thickness of 2.5 μm, selectively irradiated with ultraviolet rays using a desired photomask, developed, and post-baked to form a photoresist mask. This position is shown by the dashed line area in FIG. 13(c). Next, selective anodic oxidation was performed to form an oxide film on the gate line other than this area. Through this anodic oxidation, it was possible to grow Ta2O to a thickness of about 180 nm on Ta. This oxide film was used as the first capacitor insulating film 3. Next, the gate electrode 4 was formed in the same manner as in Example 1, and had the shape shown in FIGS. 13(a), (b), and (c). Here, in the portion where the gate line 2 and the gate electrode 4 overlapped, a first capacitor having a structure with the insulating film 3 interposed therebetween was created. This capacitance value (Cc) is determined by the thickness of the insulating film 3 and the area of the overlapped portion of the gate line 2 and gate electrode 4, and was designed to be 3.4 pF here. Next, a SiN film with a thickness of 0.3 μm was formed using the plasma CVD method.
Further, the gate insulating film 5 of 0.1 μm in thickness is formed.
A protective film 1 of SiN film with a thickness of 0.25 μm is formed on the semiconductor layer 6 of amorphous silicon (a-3i).
1 was deposited sequentially. Thereafter, first, the protective film 11 is processed by photoetching so as to remain on the gate electrode in an area narrower than the area of the gate electrode, and then the semiconductor layer 6 and the gate insulating film 5 are processed, as shown in FIG. 14(a). (b) and (c) were done. The gate insulating film 5 was removed on a part of the first capacitor because
This is to enable voltage to be directly applied to the gate electrode from here as well. Similarly, part of the gate insulating film 5 on the gate line is removed so that a voltage can be applied to the gate line from this contact hole 10. Next, 1.2 wt of P was added using the plasma CVD method. % doped n-type amorphous silicon with a thickness of 35 nm was deposited, and further, Cr with a thickness of 1100 nm and A1 with a thickness of 0.5 μm were sequentially deposited by sputtering. Next, the ohmic contact layer 7, Cr and A1 are each processed by a photoetching method to form a source electrode 8 and a drain electrode 9, as shown in FIG.
), (b), and (c) were obtained. When we measured the transistor characteristics of this TPT, we found that the characteristics were almost the same when a gate voltage was applied to the gate electrode and when a voltage was applied to the gate line. There were no TPTs in which short-circuit defects occurred between lines and drain electrodes and between gate lines and source electrodes. Embodiment 4 A fourth embodiment of the present invention will be described using FIG. 16. This figure is a conceptual diagram of the TPT substrate. The difference from the above embodiment is that there are multiple rows of gate lines 2 and multiple columns of signal lines 12 that intersect with them, and that the source electrode 9 is connected to a pixel electrode 91 made of a transparent conductive film. , there is no provision of a measuring electrode section for each TFT on the gate line. Here, as in Example 1, TPTs having a first capacitor provided in the gate line for each pixel were formed in a matrix on a glass substrate as shown in FIG. 16. Here, in processing the gate insulating film, the outermost portion of the gate insulating film was removed in order to create a terminal portion for external connection of the gate line and drain electrode. After the TPT was fabricated, SiN was further deposited to a thickness of 0.7 μm using the CVD method to form a passivation film. In this case too, the passivation film at the outermost periphery was removed in order to create a terminal section for external connections. A liquid crystal display panel was manufactured using the TPT substrate thus obtained. i.e. counter electrode and blue, red,
A transparent substrate with a green color filter array and the above T
A PT substrate was attached using a spacer, and a liquid crystal was sealed between them to obtain a liquid crystal display panel. As a result, we were able to manufacture liquid crystal display panels with a high yield, which is generally considered to have a low manufacturing yield. Furthermore, this liquid crystal display panel achieved image quality equivalent to that of a liquid crystal display panel having a conventional structure in which the gate line and the gate electrode were directly connected. Similarly, the TPT described in Example 2 or 3 is placed on the substrate.
A TPT substrate was manufactured by forming a TPT substrate, and a liquid crystal display panel was manufactured using this. This liquid crystal display panel also showed the same effect as above. Example 5 A fifth example of the present invention will be described using FIG. 18. This figure is a schematic diagram of a liquid crystal display device. This device includes a liquid crystal display panel 31, a video signal drive circuit 33 for giving a video signal to the liquid crystal display panel 31, a scanning circuit 34 for giving a scanning signal to the liquid crystal display panel 31, and a video signal drive circuit 33 for giving a video signal to the liquid crystal display panel 31. It has a control circuit 32 for providing information for the liquid crystal display panel to a circuit 33 and a scanning circuit 34. Control circuit 3
2 transmits information from the power supply circuit and upper processing unit to TPT
Contains circuits that convert into information. When each of the liquid crystal display panels obtained in the above examples was incorporated into this device, image quality equivalent to that of a conventional liquid crystal display device was obtained. [Effects of the Invention] As explained above, according to the present invention, the first capacitance is formed between the gate line and the gate electrode, and the capacitance value (Cc) of the first capacitance is set to be the same as that of the gate electrode. Capacitance generated between the source electrode, gate electrode, and drain electrode, that is, the second
The capacitance value of the capacitor (Cgs) and the capacitance value of the third capacitor (Cgs)
gd) by more than 10 times, T
It was possible to completely eliminate short-circuit defects between the gate line and the source electrode and between the gate line and the drain electrode without impairing the characteristics of the PT. Therefore, a liquid crystal display panel could be manufactured at a high yield, and this liquid crystal display panel had the same image quality as a liquid crystal display panel with a conventional structure. Furthermore, a liquid crystal display device incorporating this liquid crystal display panel achieved image quality equivalent to that of a conventional liquid crystal display device.

[Brief explanation of the drawing]

1, 2, 3, and 4 are sectional views and plan views of the TPT according to the first embodiment of the present invention, and FIGS. 5, 6, 7, and 8 are , a sectional view and a plan view of the TPT of the second embodiment of the present invention, FIG. 9 is a circuit diagram for explaining the present invention, FIGS. 10 and 11 are diagrams showing the effects of the present invention, 12, 13, 14, and 15 are a sectional view and a plan view of a TPT according to a third embodiment of the present invention, and FIG. 16 is a
FIG. 17 is a conceptual diagram showing a TPT substrate according to an embodiment of the present invention, FIG. 17 is a diagram showing the effects of the present invention, and FIG. 18 is a schematic diagram showing a liquid crystal display device according to an embodiment of the present invention. 1.Substrate 2.Gate line 3..Insulating film 4..Gate electrode 5.Gate insulating film 6.Semiconductor layer 7..Ohmic contact layer 8..Source electrode 9..Drain electrode 10.
... Contact hole 11 ... Protective film 12 ... Signal line 21 ... Gate terminal 31 ... Liquid crystal display panel 32 ... Control circuit 33 ... Video signal drive device

Claims (1)

[Claims] 1. A gate electrode disposed on a substrate, a semiconductor layer provided on the gate electrode via a gate insulating film for forming a channel, and a semiconductor layer for flowing current through the semiconductor layer. In a thin film transistor substrate having a thin film transistor consisting of a source and a drain electrode, the gate electrode is electrically connected to the gate line via a first capacitor, and the capacitance value of the first capacitor is equal to the capacitance value between the gate electrode and the source. The capacitance value is 10 times or more of both the capacitance value of the second capacitance generated between the electrode and the capacitance value of the third capacitance generated between the gate electrode and the drain electrode. thin film transistor substrate. 2. The thin film transistor substrate according to claim 1, wherein the dielectric film forming the first capacitor includes at least an anodic oxide film of the gate line. 3. The thin film transistor substrate according to claim 1 or 2, wherein the semiconductor layer is amorphous silicon. 4. The thin film transistor substrate according to claim 1, 2 or 3, wherein the thin film transistor and the first capacitor are provided at different positions in a plane. 5. In the thin film transistor substrate according to any one of claims 1 to 4, in order to cause the thin film transistor to function as a switching element, the gate line is connected to a scanning line terminal, and the drain electrode is connected to the gate line. A thin film transistor substrate characterized in that it is connected to signal lines arranged to intersect. 6. A liquid crystal comprising the thin film transistor substrate according to any one of claims 1 to 5, a substrate disposed opposite to the thin film transistor substrate and having at least a counter electrode, and a liquid crystal disposed between them. display panel. 7. A liquid crystal display panel according to claim 6, a video signal drive circuit for providing a video signal to the liquid crystal display panel, a scanning circuit for providing a scanning signal to the liquid crystal display panel, the video signal drive circuit, and A liquid crystal display device comprising: a control circuit for providing information for a liquid crystal display panel to a scanning circuit.