JPH04156659A - Multiplexed computer control system - Google Patents

Abstract

PURPOSE:To avoid wired-OR connection by controlling input/output means corresponding to respective busese so that both multiplexed devices do not always and simultaneously use one bus in correspondence with the operation state of respective buses. CONSTITUTION:Respective devices are duplexed in CPU devices 1 and 2 and in memory devices 3 and 4 and they are bus-connected to buses 21 and 22 which are similarly duplexed. The combination of the CPU devices and the driving data buses is initialized so that the CPU control circuit 6 of CPU 1 drives the data bus 21 through an input/output circuit 8 and the CPU control circuit 10 of CPU 2 drives the bus 22 through an input/output circuit 11 when both systems are normal. Thus, the simultaneous driving of the data buses by two duplexed input/output circuits connected to the same data bus can be prevented by initialization. That is, a wired-OR operation can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplexed computer control system, and more specifically,
Relating to a multiplex computer control method that prevents changes in bus drive capacity depending on operating conditions, such as whether all or some of the multiplexed CPU devices are normal, in a computer in which devices, memory devices, etc. are multiplexed and connected via a bus. .

[Conventional technology]

Traditionally, in order to realize highly reliable computers, CPU
Methods for multiplexing devices, memory devices, etc. have been developed.

FIG. 2 shows the conventional configuration of a typical redundant computer as a highly reliable computer. In FIG. 2, 1 and 2 are duplicated CPTJ devices, 3 and 4 are duplicated memory devices, and these are also bus-connected to duplicated data buses 21 and 22. The CPU device 1 consists of a microprocessor 5, a CPtJ control circuit 6, and a duplicated input/output circuit 7.8. Similarly, the CPU device 2 includes a microprocessor 9, a CP, a U control circuit 10, and duplex input/output circuits 11 and 12. The memory device 3 includes a memory 13, a memory control circuit 14, and duplicated input/output circuits 15 and 16, and the memory device 4 includes a memory 17, a memory control circuit 18, and duplicated input/output circuits 19 and 20.
Consisting of In FIG. 2, a duplex computer is schematically shown with only a CPU device, a memory device, and a data bus, but IO devices can also be duplexed and connected to the bus in the same way. This I
Since the O device can be considered in the same way as the memory device, a description thereof will be omitted.

In this way, when devices are duplicated, by comparing the states and output results of the devices, it is possible to detect that one of the duplicated devices is out of order if a mismatch occurs. However, it is not possible to identify a failed device simply by detecting a mismatch. For this reason, conventionally, in order to eliminate the influence of a failed device, means for identifying a failed device has been adopted for each target device.

(1) Microprocessor failure detection The following two methods are used to detect a failure in a microprocessor in a CPU device.

■ A method of comparing the parity bit predicted from the input data of the arithmetic circuit and the operation contents with the parity bit of the operation result.

■ A method of duplicating the arithmetic circuit or microprocessor itself, comparing the arithmetic results, and determining that a failure has occurred if they do not match.

By combining the redundancy for backup in case of a CPU device failure and the redundancy for failure detection in the method (2) above, the same processing will be executed by four microprocessors. This method has become possible because the price of high-performance microprocessors has decreased with the advancement of LSI technology. In FIG. 2, it is assumed that failure detection of the microprocessors 5 and 9 is performed by the CPU control circuits 6 and 10.

(2) Memory Failure Detection Parity bits or error correction codes are generally used to test memory. That is, a parity bit or an error correction code is added and written into the memory when writing to the memory, and the validity of the parity bit or error correction code is checked when reading. In FIG. 2, it is assumed that the memory control circuit 14.18 serves this role.

(3) Data bus failure detection Parity bits are used to detect data bus failures. That is, the parity bat is added during data bus transmission, and its validity is checked on the receiving side. Furthermore, in some cases, the parity bit is combined with checking of the transfer procedure protocol, etc.

In FIG. 2, failure detection of data bus 21.22 is performed by input/output circuits 7, 8, 11, 12, 15, 16°19.20
Suppose that it is done in

The operation of the conventional redundant computer will be explained below with reference to FIG.

First, a case will be described in which the duplicated CPU devices 1.2 are both operating normally. The CPU device 1 and the CPU device 2 execute the same processing, and have a redundant input/output circuit 7,
8, or send the same data to the data bus 21.22 via the input/output circuits 11.12. That is, the data sent from the input/output circuit 8 and the input/output circuit 12 are wired OR connected on the data bus 21, and the data sent from the input/output circuit 7 and the input/output circuit 11 are wired OR connected on the data bus 22.
Connected. CPU devices 1 and 2 are connected to data buses 21 and 22.
When receiving data, the input/output circuit is duplicated, so only data that has been transferred normally can be received. For example, by checking the parity bit in both the input/output circuit 7 and the input/output circuit 8 of the CPU device 1,
The duplexed data buses 21 and 22 are checked for data transfer errors, and only normally transferred data is transferred to the microprocessor 5. The same applies to the CPU device 2.

Next, a case will be described in which one of the duplicated CPU devices 1 and 2 fails. For example, if microprocessor 5 is normal and microprocessor 9 is broken,
After confirming the normal operation of the CPU device 1, the CPU control circuit 6 transfers the data sent from the microprocessor 5 via the input/output circuit 7 and the input/output circuit 8 to the data bus 21. The data is sent to the data bus 22. On the other hand, the CPU that detected the failure of CPU device 2
Control circuit 10 controls input/output circuits 11.12 not to send data to data bus 21.22.

Next, the operation of the memory devices 3 and 4 will be explained. Memory device operations include read operations and write operations.

First, the read operation will be explained. Read addresses from the duplicated memory devices 3.4 are sent to input/output circuits 15.16 via duplicated data buses 21.22, respectively.
The signal is transferred to the memory 13 through the input/output circuits 19 and 20, and then to the memory 17 through the input/output circuits 19 and 20. Since the input/output circuits of each memory device 3 and 4 are duplicated, for example, by checking the parity pits in both the input/output circuits 15 and 16 of the memory device 3, data on the duplicated data buses 21 and 22 can be checked. You can check for forwarding errors and only receive addresses that were successfully forwarded. If there is no abnormality in the address, data is read from the memory 13.17. The memory control circuits 14 and 18 each add and check parity pits or error correction codes,
The memory data is inspected, and if an error is detected, the memory data is controlled not to be output to the data buses 21, 22/\ to the input/output circuits 15, 16 or 19, 20.

When the duplexed memory devices 2 and 4 are both performing normal read operations, data read from the memory 13 is sent to the data bus 22 and the data bus 21 through the input/output circuits 15 and 16. - On the other hand, the data read from the memory 17 is sent to the data bus 22.21 through the input/output circuit 19.20, and the data read from the memory 17 is sent to the data bus 22.21 on each data bus.
The data read from and the wired ○R are taken.

When one of the duplexed memory devices 3 and 4 is out of order, for example, when the memory 13 is normal and the memory 17 is out of order, the following operation occurs.

If the memory control circuit 18 detects an abnormality in the parity pit or error correction code of the data read from the memory 17, and it is determined that the memory 17 has failed, the memory control circuit 18 transfers the data to the input/output circuit 19-20 via the data bus 22. .21. In this case, only the normally operating memory device 3 is connected to the data bus 22.
The data is sent to 21.

Next, the write operation will be explained. Memory device 3, 4
The operation is confirmed by checking whether the written data can be read correctly, as described above. Therefore, in general, the duplex memory 13.1
If one of the memories 13 and 7 is not found to be faulty, the same data is written to the same address in both memories 13 and 17.

That is, data written to the memory device 13.17 is sent to the input/output circuit 15.17 via the redundant data bus 21.22.
The data is written into the memory 13 through the input/output circuit 16 and into the memory 17 through the input/output circuits 19 and 20. Each memory device 13.
Since the input/output circuits 17 are duplicated, for example, by checking the parity pits in both input/output circuits 15 and 16 of the memory device 3, it is possible to check for data transfer errors on the duplicated data buses 21 and 22. Only data that has been successfully transferred can be received.

[Problems to be Solved by the Invention] As explained above, conventional redundant computers utilize wired OR connection of redundant CPU devices, memory devices, etc. to redundant data buses. Since the redundant CPU device and memory device automatically stop sending data to the bus in the event of a failure, the wired OR connection configuration has the advantage of not requiring controls such as disconnecting the failed device from the bus. Additionally, by making a wired OR connection, the same data is always sent to the duplicated data bus, so bus failures can be detected by comparing both buses or checking parity on the data receiving side. .

In other words, by wired ORing a redundant CPU device and a redundant memory device, etc. on a redundant data bus, even if one of the devices fails, a normal CPU
By combining the U device with a memory device, etc., operation can be continued, making it possible to create a highly reliable computer.

However, in the conventional redundant computer configuration as shown in Figure 2, there was a problem in that the data bus driving capacity differed depending on whether both of the redundant CPU units were operating normally or when only one unit was operating normally. . In other words, when both of the redundant CPU devices are normal, the data bus is driven by two CPU devices connected by wired OR, and when only one CPU device is normal, the data bus is driven by one CPU device. Driven by the device.

As the operating clock speed of microprocessors has become faster in recent years, the speed of bus transfer locking has also become faster.

The fact that the data bus drive ability changes depending on the operating conditions is
When the bus transfer lock is high-speed, for example, 10 MHz or more, it becomes a factor that makes design difficult for the following reasons.

Even if the data bus inside a computer is short, the wiring length is several tens of centimeters, and the wiring capacitance is large. However, as the transfer lock speed increases, the inductance of the data bus wiring cannot be ignored. In other words, data bus wiring is a resonant circuit composed of capacitance and inductance and has a unique resonant frequency of several tens of MHz, so if the transfer lock is 10 MHz or higher, high-speed transfer is impossible unless resonance is suppressed. .

In order to suppress resonance in such a high frequency band, it is essential to stabilize the drive circuit. However, the conventional wired OR
In a redundant computer that uses connections, the data bus drive conditions differ depending on whether the data bus drive capacity is high or low, making it impossible to perform an optimized design to suppress resonance in order to realize a high-speed data bus.

The purpose of the present invention is to provide a more reliable computer configuration than before.
In a widely used duplex computer (generally a multiplex computer), the data bus drive capacity does not change depending on operating conditions, such as when both duplex CPU devices are normal or when only one is normal. As long as both duplicated devices of the same type fail at the same time,
The object of the present invention is to provide a computer control method that allows a normal device to be reconfigured to continue processing.

[! Means for Solving Problem i] In order to achieve the above object, the present invention provides a multiplexing computer in which a CPU device, a memory device, a data bus connecting these devices, etc. are multiplexed. between installed CPIJ devices, memory devices, etc.
A signal line is provided to mutually notify the operating status of the multiplexing devices, and each multiplexed CPU device, memory device, etc. corresponds to the operating status of its own device, other multiplexed devices, and each data bus. Therefore, each input/output circuit is controlled so that one data bus is not used redundantly between the multiplexers.

[For production]

It is assumed that a CPU device, a memory device, and a data bus connecting these devices are each duplicated, and each of the duplicated CPU devices and memory devices is provided with two systems of input/output circuits (bus drive circuits).

If both CPU devices, memory devices, and data buses are normal, one CPU device or memory device drives one data bus using one input/output circuit, and the other CPU device drives one data bus using one input/output circuit.
The U device or memory device drives the other data bus by the other input/output circuit.

If one system of the CPU'U device or memory device is faulty and both data buses are normal, the normal CPU device or memory device drives each data bus using two input/output circuits. If one system of the data bus fails, a normal data bus is driven by one input/output circuit in each of the CPU device and memory device.

In this way, regardless of the operating status of each device or data bus,
Since each data bus is always driven by one system such as a CPU device or a memory device, it is possible to drive the bus without changing the data bus driving capacity depending on the operating conditions, and two duplexed devices of the same type can be driven at the same time. As long as neither unit fails, a normal device can be reconfigured and processing can continue.

〔Example〕

FIG. 1 shows a configuration diagram of a redundant computer according to an embodiment of the present invention. In FIG. 1, the CPU device is duplicated with CPU device 1 and CPU device 2 having the same configuration.
The memory device is also duplicated with memory device 3 and memory device 4 having the same configuration, and each device is connected to the data bus 2 which is also duplicated.
1.22 is connected to the bus. The CPU device 1 includes a microprocessor 5, a CPU control circuit 6, and a duplicated input/output circuit 7 and input/output circuit 8. Similarly, it is composed of a CPU device 2, a microprocessor 9, a CPU control circuit 10, and a redundant input/output circuit 11 and an input/output circuit 12. The CPU device 1 and the CPU 2 device are connected to each other by a failure information notification line 23 through the CPU control circuit 6 and the CPU control circuit 10. The memory device 3 includes a memory 13, a memory control circuit 14, and a duplicated input/output circuit 15 and input/output circuit 16. Similarly, the memory device 4 includes a memory 17, a memory control circuit 18, and a duplicated input/output circuit 19 and input/output circuit 20. The memory device 3 and the memory device 4 are connected by a failure information notification line 24 through a memory control circuit 14 and a memory control circuit 18.

The CPU control circuit 6 and the CPL7 control circuit 1o have a failure detection function for the microprocessor 5 and microprocessor 9, respectively. The memory control circuit 14 and the memory control circuit 18 have a failure detection function for the memory 13 and the memory 17, respectively. Input/output circuits 7, 8, input/output circuit 11,
12, input/output circuits 15, 16, and input/output circuits 19, 20 each have a failure detection function for the data bus 21 and data bus 22. The methods of these failure detection functions may be the same as those explained in FIG. In the embodiment shown in FIG. 1, the dual CPI, the CPU control circuit 6 of the
Between the CPU control circuit 10 of the device 2 or the memory device 3
The memory control circuit 14 of the memory device 4 and the memory control circuit 18 of the memory device 4 notify each other of the operating status (normal/failure) through the failure information notification line 23 or the failure information notification line 24, so that the duplex computer as a whole is normal. It can be controlled such that a single device is always used to combine the different parts and drive the data 21,22.

Before a specific description of the embodiment, a failure notification method between duplexed devices and a data bus failure detection and reporting method will be described.

(1) Failure notification method There are several possible failure notification methods.
Two typical implementation methods are shown below.

■ Configure the failure information notification line with two signal lines.

For example, the failure information notification line 23 is connected to two signal lines 23-1 and 2
It consists of 3-2. Of these, failure information notification line 23-1
is a signal line for notifying the CPU device 2 of a failure in the number of CPU devices, and the failure information notification line 23-2 is a signal line for notifying the CPU device 1 of a failure of the CPU device 2. The same applies to the failure information notification line 24. The signal transferred on the failure information notification line may be a level signal. That is, a high potential indicates a normal state, and a low potential indicates a faulty state.

■ Configure the failure information notification line with one signal line.

For example, in order to configure the failure information notification line 23 with one signal, the failure information notification line 23 may be a bidirectional signal line, and the transferred signal may be a level signal as in (2). The failure information notification line 23 is connected to the CPU device 1 and the CPU in order to form a single signal line.
It is driven by the U device 2 in a wired OR connection form.

Although it is an object of the present invention to eliminate the drive of the wired OR connection form of the data buses 21 and 22, the failure information notification line 2
3 is a single signal and is used to notify each other of the status of duplexed devices, rather than transferring periodically changing data like data buses 21 and 22, so it is exceptionally not wired. An OR connection type may also be used. The same applies to the failure information notification line 24.

(2) Data bus failure detection and reporting method Data bus 21
．． 22 is detected by checking the parity bit added to the data on the transmitting side during data transfer on the receiving side.

For example, when the CPU device 1.2 is on the sending side, the memory devices 3 and 4, which are on the receiving side, perform verification to determine whether the bus is normal or faulty and report it to the sending side. When the CPU device 1.2 is on the receiving side, the input/output circuit 7゜8.1 in the CPU devices 1 and 2
1. Based on the parity pit check result in 12, C
The CPU control circuits 6 and 10 in the PU devices 1 and 2 are connected to the bus 21.
．． 22 is normal/failure and reports to the sending side.

The normality/failure of the bus is reported using a control signal line (not shown) on the data buses 21 and 22, such as a bus error notification signal line. Generally, the data bus is multipath, VME bus, etc.
Although detailed specifications such as the number of signals and the meaning of the signals vary depending on the type, there is a bus error notification signal as a signal line that notifies of some kind of failure associated with data transfer on the data bus.

Next, the specific operation of the embodiment will be explained. In the duplex computer according to the embodiment of the present invention, as shown in FIG.
There are two systems for the PU device, data bus, and memory device, and each device can operate in three states (both systems normal ×
1. One system is normal x 2), so there are 27 combinations (= 3") that can operate as a computer.CPU devices and memory devices may be connected to increase the processing power and memory capacity. Yes. Even in that case, the basic combination remains the same.

If there are multiple redundant CPIJ devices, similar to general parallel computers, the priority order of data bus usage rights is set in advance among multiple CPU devices, so that even if data bus usage requests occur at the same time, the data The CPU device sending data to the bus can always be controlled by one CPU device. The same applies when a plurality of memory devices are provided for expansion.

As a detailed explanation of the present invention, a minimum configuration in which each set of a CPU device, a data bus, and a memory device, which are the basics of operation of a duplex computer, are duplexed will be described.

Even in the case of the redundant computer with the minimum configuration shown in Fig. 1, the explanation for each operating mode is complicated as there are as many as 27 combinations. This will be explained using FIGS. CPU
Since there are two systems for both the device and the data bus, there are nine types of operable combinations as shown in Table 1.

Table 1 However, #0-CPU device 1. #1-CPU device 2@O
- Data bus 21, @1 data bus 22x is abnormal (1) Bus drive when both the CPtJ device and the data bus system are normal Figure 3 is an explanatory diagram of the operation when both the CPU device and the data bus system are normal shows. Although the CPU device transmits or receives data to or from the data bus, here, to simplify the explanation, a case where data is transmitted (driven) will be explained.

If both systems are normal, the CPU control circuit 6 of the CPU device 1
drives the data bus 21 via the input/output circuit 8, and the CP
The CPU control circuit IO of the U device 2 initializes the combination of the CPU device and the driving data bus so as to drive the data bus 22 via the input/output circuit 11. In this way, C
By predetermining and initializing the driving data bus for each PU device, simultaneous driving of the data bus by two duplexed input/output circuits connected to the same data bus can be prevented. In other words, the wired ○R operation can be prevented.

(2) Bus operation when one CPU system is normal and both data bus systems are normal. FIG. . The CPU control circuit 10 that has detected a failure in the microprocessor 9 suppresses the input/output circuit 11 so that incorrect data is not sent to the data bus 22 from the failed CPU device 2, and also sends the own CPU via the failure information notification line 23. Notify the CPU device number PLI control circuit 6 that the device 2 has failed. On the other hand, the CPU control circuit 6, which has received a failure notification via the failure information notification line 23, causes the two input/output circuits 7 and 8 of the normal CPU device l to drive the two data buses 21 and 22. Control. That is, the input/output circuit 8 drives the data bus 21 and the input/output circuit 7 drives the data bus 22.

FIG. 5 is an explanatory diagram of the operation when the CPU device 2 is normal and the number of CPU devices is malfunctioning. The CPU control circuit 6 that has detected a failure in the microprocessor 3 inhibits the input/output circuit 8 so that incorrect data is not sent to the data bus 21 from the failed CPU device 1, and also controls the failure information notification line 23.
Then, the CPU of CPU device 2 reports that its own CPU device 1 has failed.
The U control circuit 10 is notified. On the other hand, failure information notification line 23
The CPU control circuit 10 that received the failure notification in
The two input/output circuits 11.12 of the PU device 2 are controlled to drive the two data buses 21.22. That is, the input/output circuit 11 drives the data bus 21 and the input/output circuit 12 drives the data bus 22. In this case, the failure information notification line 23 carries out the failure notification in the opposite direction to the case shown in FIG.

(3) Bus operation when both CPU systems are normal and one bus system is faulty Figure 6 explains the operation when both CPU systems 1 and 2 are normal, data bus 21 is normal, and data bus 22 is faulty. Show the diagram. The CPU device 1 drives the data bus 21 via the input/output circuit 8. The data bus 22
When the CPU device 2 detects a failure, it suppresses the output of the input/output circuit 11.

If the data bus 22 is normal and the data bus 21 is out of order, the normal operations of the CPU devices 1 and 2 will simply be reversed. That is, the CPU device 2 drives the data bus 22 via the input/output circuit 11.

CPU device 1 that has detected a failure in the data bus 21 based on bus error notification or verification of parity bits upon reception, etc.
suppresses the output of the input/output circuit 8.

(4) Bus drive when one CPU device is normal and one bus is faulty FIG. 7 is an explanatory diagram of the operation when the CPU device 2 and the data bus 22 are faulty. In this case, the failure can be divided into the following two types depending on which of the CPU device 2 and the data bus 22 fails first.

(4)-1 CPU device 2 fails, and then data bus 2
When CPU device 2 fails, both data bus systems are normal at the time when CPU device 2 fails, so the situation is the same as that shown in FIG. 4, and one CPU system drives both bus systems. That is, the normal CPU device 1
Two input/output circuits 7 and 8 are used, and the input/output circuit 8 drives the data bus 21 and the input/output circuit 7 drives the data bus 22.

If a failure occurs in the data bus 22 of one side while one CPU device 2 is out of order, the following operation is performed. When detecting a failure in the operating CPU device data bus 22, the CPU control circuit 6 of the CPU device
The operation of the input/output circuit 7 is controlled to be stopped in order to suppress sending of data to the data bus 22. Data bus failure detection is performed by notifying a bus error or by verifying the parity bit at the time of reception, as described above.

Thereafter, operation continues using the CPU device data bus 21.

(4)-2 When the data bus 22 fails and then the CPU device 2 fails At the time when the data bus 22 fails, both systems of the CPU device are normal, so the state is the same as that shown in Fig. 6, and the CPU One bus system is driven by one system. That is, the CPU device 1 drives the data bus 21 via the input/output circuit 8, but on the other hand, since the data bus 22 is out of order, the CPU device 2 suppresses the output of the input/output circuit 11.

When this one-side data bus 22 is out of order, the one-side CP
If another failure occurs in the U device 2, the operation will be as follows. When the operating CPU device 2 detects a failure, C
The CPU control circuit 10 of the PU device 2 is an input/output circuit 11.1
2 is controlled to stop the operation. At this time, the CPU device 1 receives the occurrence of a failure in the CPU device 2 through the failure information notification line 23, but since the data bus 22 has already stopped due to the failure, data is input to the data bus 22 instead of the CPU device 2. No output.

In this way, the operation with the CPU device device tabus 21 continues.

FIG. 8 is an explanatory diagram of the operation when the CPU device 1 and the data bus 21 are out of order. In this case as well, the CPU device is
Depending on which tabus 22 malfunctions first, it is divided into the following two series.

(4)-3 When the CPU device 1 fails and then the data bus 21 fails At the time when the CPU device 1 fails, both data buses are normal, so the state is the same as that shown in Fig. 5, and the CPU One-sided operation is performed. That is, the two input/output circuits 1.1.12 of the normal CPU device 2 are used; the input/output circuit 11 drives the data bus 22, and the input/output circuit 12 drives the data bus 21.

If a failure occurs in the data bus 21 of one side while the one-side CPtJ device 1 is out of order, the following operation is performed. When the operating CPU device 2 detects a failure in the data bus 21, the CPU control circuit 10 of the CPU device 2
controls to stop the operation of the input/output circuit 12 in order to suppress data transmission to the data bus 21.

Thereafter, operation continues using the CPU device 2 and the data bus 22.

(4)-4 When the data bus 21 fails and then the CPU device 1 fails At the time when the data bus 21 fails, both systems of the CPU device are normal, so FIG. The situation is the same as when the failure relationship is reversed, and one bus system is driven by one CPU system. That is, the CPU device 2 drives the data bus 22 via the input/output circuit 11, but on the other hand, since the data bus 21 is out of order, the output of the CPU device output circuit 8 is suppressed.

When this one-side data bus 21 is out of order, the one-side CP
If another failure occurs in the U device 1, the CPU 2
The occurrence of a failure in the PU device is received via the failure information notification line 23. At this time, since the data bus 21 has already stopped due to a failure, the CPU device 2 is converted into a CPU device and the data bus 21 is
No data bus input/output is performed on 1.

In this manner, the CPU device 2 and data bus 22 continue operating.

In addition to the above, there are cases in which the CPU device 2 and data bus 21 are out of order, and the CPU device 1 and data bus 22 are out of order. The operation differs depending on whether a failure occurs first, the CPU device or the data bus. Each case will be briefly explained below.

(4)-5 When the CPU device 2 fails and then the data bus 21 fails, both data buses are normal at the time the CPU device 2 fails, and the normal CPU device input/output circuit 8 is The data bus 21 is driven by the input/output circuit 7, and the data bus 22 is driven by the input/output circuit 7. In this state, if another failure occurs in the data bus 21 of one system, the CPU control circuit 6 of the operating CPU device 1
controls to stop the operation of the input/output circuit 8 in order to suppress sending of data to the data bus 21. In this manner, the CPU device 1 and the data bus 22 continue to operate.

(4)-6 When the data bus 21 fails and then the CPU device 2 fails At the time when the data bus 21 fails, both systems of the CPU device are normal, and the CPU device 1 is connected via the input/output circuit 8. Although it is possible to drive the data bus 21, since the data bus 21 is out of order, the CPU device 1 suppresses the output of the input/output circuit 8. On the other hand, the CPU device 2 sends data to the data bus 22 via the input/output circuit 11. In this state,
If another failure occurs in the CPU device 2 of one system, when the operating CPU device 1 receives the failure occurrence of the CPU device 2 via the failure information notification line 23, the CPU device-based PU control circuit 6 In order to send data to the data bus 22 instead of the device 2, the stopped input/output circuit 7 is controlled to start operating. In this manner, the CPU device 1 and the data bus 22 continue to operate.

(4)-7 When the CPU unit 1 fails and the data bus 22 also fails At the time when the CPU unit W fails, both data buses are normal, and the input/output circuit 12 of the normal CPU unit 2 drives the data bus 21, and the input/output circuit 11 drives the data bus 22. In this state, if another failure occurs in the one-side data bus 22, the CPU control circuit 10 of the operating CPU device 2 stops the operation of the input/output circuit 11 in order to prevent data from being sent to the data bus 22. Control as follows. In this manner, the CPU device 2 and data bus 21 continue operating.

(4)-8 When the data bus 22 fails and then the CPU device 1 fails At the time when the data bus 22 fails, both systems of the CPU device are normal, and the CPU device 2 is connected via the input/output circuit 11. Although it is initially set to drive the data bus 22, since the data bus 22 is out of order, the CPU device 2 inhibits the output of the input/output circuit 11. On the other hand, the CPU device 1 is sending data to the data bus 21 via the input/output circuit 8 as initially set. In this state, the single-system CPU device 1
When another failure occurs in the CPU device 1, the CPU device 2 in operation receives the failure occurrence in the CPU device 1 via the failure information notification line 23, and the CPU control circuit 10 of the CPU device 2 uses the data bus In order to send data to the input/output circuit 21, the input/output circuit 12, which has been stopped, is controlled to start operating. In this manner, the CPU device 2 and data bus 21 continue operating.

Next, focusing on the dual computer memory device and the dual data bus according to the embodiment of the present invention shown in FIG. 1, respective combinations will be explained using FIGS. 9 to 11. Since there are two systems for both the memory device and the data bus, there are nine types of operable combinations as shown in Table 2, similar to the aforementioned CPU device and data bus.

As shown, $0 military memory device 3, $1 country memory device 4 @
0 Data bus 21, @1 Data bus 22x is abnormal (1) Bus drive when memory device and data bus both systems are normal In Figure 9, memory devices 3 and 4 are An explanatory diagram of the operation when both are normal is shown.

Similar to the CPU device, the memory device transmits or receives data to or from the data bus, but to simplify the explanation, a case where data is transmitted (driven) will be described here.

When both systems are normal, the memory device 3 drives the data bus 21 through the input/output circuit 16, and the memory device 4 drives the data bus 22 through the input/output circuit 19. Initialize the combination of device and drive data bus. In this way, when driving a data bus, a driving data bus is determined in advance for each memory device, and the data bus is not driven simultaneously by two duplex input/output circuits connected to the same data bus. . That is, the wired ○R operation is not performed.

(2) Bus drive when one memory system is normal and both data bus systems are normal. In Figure 1o, memory device 3 is normal and memory device 4 is faulty.
FIG. 4 is an explanatory diagram of the operation when both data buses 21 and 22 are normal. Memory control circuit 18 that detected a failure in memory 17
This prevents the input/output circuit 19 from sending erroneous data from the failed memory device 4 to the data bus 22, and also sends information to the memory device 3 through the failure information notification line 24 indicating that the memory device 4 has failed. The control circuit 14 is notified. On the other hand, the memory control circuit 14 that has received the failure notification of the failure information notification line 24 connects the two input/output circuits 15 and 16 of the normal memory device 3 to the two data buses 21 and 22.
control to drive. That is, the input/output circuit 16 is connected to the data bus 21. The input/output circuit 15 drives the data bus 22.

FIG. 11 shows that memory device 4 is normal and memory device 3 is faulty.
FIG. 4 is an explanatory diagram of the operation when the data buses 21 and 22 are normal in the same system. Memory control circuit 14 detecting failure of memory 13
prevents the input/output circuit 16 from sending erroneous data from the failed memory device 3 to the data bus 21. On the other hand, the two input/output circuits 19. of the normal memory device 4.
20 drives two data buses 21 and 22. That is,
The memory control circuit 18 receives the failure of the memory device 3 through the failure information notification line 24, and the input/output circuit 19 connects to the data bus 2.
2, the input/output circuit 20 controls the data bus 21 so as to drive the data bus 21.

The operation of each combination of memory device both systems normal and one system normal when one data bus system is out of order corresponds to the case where one data bus system is out of order as explained in Figures 6 to 8. Since the operation is similar to that of the CPU device, the explanation will be omitted.

In order to make it easier to understand the operation of the redundant computer,
The description has been made separately for the CPU device and data bus, and the memory device and data bus. As can be seen from the above explanation, failures are notified to each other between the redundant CPU device and memory device via the failure information notification line, and the operating status of the data bus is monitored using the bus error signal line, etc. By,
Unless both duplicated devices of the same type fail at the same time, it is possible to realize a computer that continues processing by reconfiguring normal devices.

Although FIG. 1 shows an embodiment of the present invention in which the CPU device, memory device, and bus are each duplicated, in order to improve CPU performance and increase memory capacity,
It is possible to connect multiple PU devices and memory devices to the bus. In that case, control of bus usage acquisition between a plurality of CPtJPts and between memory devices can be handled by combining the bus usage right arbitration method used in conventional parallel computers and the like with the present invention.

Further, in FIG. 1, the computer is schematically illustrated with only a CPU, a memory device, and a data bus, but the IO device can also be duplicated in the same way. In this case, the operation of the IO device on the data bus can be considered in the same way as that of the CPU device and the memory device, so a description thereof will be omitted.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if operating conditions differ, such as when all multiplexed CPU devices, memory devices, etc. are normal, and only some are normal, in a multiplexed computer, data This has the effect of realizing a computer configuration that enables bus driving without any change in bus driving ability. Specifically, when driving a data bus using a conventional wired OR connection between two CPU devices, the higher the speed of the bus transfer clock, the more difficult it is to design the drive capacity and drive timing. Since the wired OR connection can be avoided, the design becomes easier and at the same time, it becomes possible to increase the speed limit of the data bus operation clock.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a duplex computer according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional duplex computer, and FIGS. 3 to 8 are illustrations of combinations of the CPU device and data bus in FIG. FIGS. 9 to 11 are explanatory diagrams of the operation of the combination of the memory device and data bus in FIG. 1 according to the present invention. 1.2...CPU device, 3,4...Memory device, 5.9...Microprocessor, 6,1o...
・CPU control circuit, 7, 8, 11.12... Input/output circuit, 13.17... Memory, 14.18...
Memory control circuit, 15, 16, 19.20... Input/output circuit, 21.22... Data bus, 23.2
4... Failure information notification line. Figure 3 Figure 6 Figure 4 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] (1) In a multiplexed computer in which a CPU device, a memory device, and a bus connecting these devices are multiplexed, each device has a bus for transmitting and receiving data with each multiplexed bus. It is equipped with corresponding input/output means and means for determining the operating status of its own device and each bus, and means for mutually notifying each other of the operating status of the multiplexed devices. Each multiplexed device is configured to control each bus so that the multiplexed devices do not use the same bus redundantly, depending on the operating status of the own device, other multiplexed devices, and each bus. A multiplexed computer control method characterized by controlling corresponding input/output means.