JPH04153751A - Buffer storage control system - Google Patents

Abstract

PURPOSE:To correct the errors with high efficiency by providing a move-in processing means and a store processing means which generates a new vertical parity from the store data and finally writes the store data and the vertical parity into a buffer storage part. CONSTITUTION:A move-in processing means 15 writes a vertical parity produced from the move-in data into a buffer storage part 13 in a move-in processing state. A store processing means 17 reads the data on a store destination and the vertical parity of the block to which the data belong out of an arithmetic unit in a store processing state. Then the means 17 produces a new vertical parity from those store data and finally writes the store data and the vertical parity into the part 13. Then the vertical parity read out of the arithmetic unit in the store processing state is compared with the produced vertical parity for correction of errors. In such a way, the errors are corrected with high efficiency.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figs. 10 and 11) Means for solving the problem to be solved by the invention (Fig. 1) Implementation of action Examples (Figs. 2 to 9) Effects of the invention [Summary] Buffer storage control method for a data processing device having a main storage device and a store-in type buffer storage section that holds a copy of the data in blocks. The purpose is to enable efficient hardware operation when horizontal/vertical parity is applied to the store iso type buffer storage, and the main memory and a copy of the data in the main memory are maintained in blocks. A data processing device equipped with a store-in type buffer storage unit, which has horizontal parity in units of a plurality of segments obtained by subdividing data in units of blocks, and vertical parity for each bit for each segment in the block, A move-in processing means that writes vertical parity generated from move-in data into a buffer storage unit during move-in processing, and a move-in processing means that first reads the data at the storage destination and the vertical parity of the block to which the data belongs during store processing from the arithmetic unit. , next generates a new vertical parity from these store data, and finally writes the store data and this vertical parity into a buffer storage section.

[Industrial application field]

Generally, the capacity and access speed of a storage device are in a contradictory relationship. Therefore, in a data processing device, for example, a main storage device using a low-speed, large-capacity storage element and a buffer storage section using a high-speed, small-capacity storage element are used. A configuration is adopted in which a copy of the block obtained by subdividing the data on the main storage device is provided in the main storage device, thereby increasing the apparent speed of access to the storage device.

The present invention relates to an error handling method in a store-in buffer storage section, in which a part of data on a main memory is stored in a buffer storage section, and normal access to the storage device is made to the buffer storage section.

[Conventional technology]

There are two main types of control over the buffer storage unit: a store-through method and a store-in method.

In the store-through method, in a fetch access, if the target data is not in the buffer storage, the corresponding block is moved in from the main memory to the buffer storage, and in a store access, it is stored in the buffer storage. If there is previous data, it is stored in both the buffer storage unit and the main memory, and if there is no data to be stored, it is stored only in the main memory.

In the store-in method, when there is no target data in the buffer storage unit, the data is moved in from the main storage device in both fetch access and store access, and store is performed only in the buffer storage unit in store access. If the block to be replaced during move-in is a block that has been stored in the past, or a block whose store has not yet been reflected in the main memory of another data processing device that shares the main memory. If necessary, the corresponding block is moved out from the buffer storage section to the main storage device.

In this way, the store-through type does not require a move-out operation, so it is easier to control than the store-in type. On the other hand, since a store to the main memory occurs every time a data processing device accesses a store, the waiting time for accessing the main memory inevitably increases, especially as the number of data processing devices that share the main memory increases. .

Therefore, when there are a large number of data processing devices that share a main storage device, a store-in buffer storage control method tends to be adopted.

By the way, if an error occurs in the buffer storage section, the latest data is only in this buffer storage section, so it is necessary to correct the part of the data containing the error on the buffer storage section side.

On the other hand, in a semiconductor memory, an error (soft error) may occur in which the value (0) stored in the memory changes due to the influence of alpha rays or the like. As a countermeasure for this,
A known method is to add an error correction code (ECC code) to data to perform single bit error correction or double bit error detection.

Note that this method is widely used in main storage devices or processing devices that store microprograms. 20 ECC code is, for example, 5 for 8-bit data.
8 bits are required for 64 bit data, and the memory section needs to store this ECC code in addition to the data portion. Further, a large amount of hardware is indispensable for generating ECC codes or correcting errors using ECC codes.

Therefore, it may be difficult to use this ECC code for buffer storage due to memory capacity and hardware limitations.

In that case, a horizontal/vertical parity method is adopted.

Parity is a value obtained by exclusive ORing the values of each bit of data, but in the following explanation, odd parity is used where the exclusive OR of all bits of the data part and the parity bit is logical "1". Here is an example using .

As shown in Figure 10, one block (32 bits)
When divided into multiple segments (8 bits),
There is one horizontal parity for each segment, and one vertical parity for each bit for all segments in the block.

Here, a soft error (1 →
0) occurs, an error correction method will be explained.

When each segment is sequentially accessed and a parity error occurs when accessing segment 1, an error correction processing step is entered.

That is, each segment is sequentially read out, each bit is exclusive-ORed, and compared with vertical parity. Here, the mismatch is detected for bit 2, so
It is found that there is a bit inversion in bit 2 of segment l, and error correction becomes possible.

Conventionally, in this horizontal/vertical parity method, a firmware routine is activated to perform error correction in response to detection of a horizontal parity error.

FIG. 11 is a block diagram showing an example of the configuration of a conventional buffer storage section.

In the figure, the buffer storage section has a capacity of 4 ways x 128 lines, with 1 block being 64 bytes, and uses a set associative method consisting of a tag section 71 shown at the top and a data section 73 shown at (b). It has become.

The tag unit 71 stores a valid flag V indicating whether the block is valid, a change flag C indicating that the block has been stored, and a part of the address of the block on the main storage device. Indicating address bits “00” ~
Consists of "18".

A copy of a block on main memory is placed in a predetermined way according to a predetermined algorithm among the four ways on one of the 128 lines selected by address bits "19" to "25" of the block. It will be destroyed. Furthermore, each way of the tag section 71 and data section 73 corresponds to each other.

This data section 73 can only be accessed at the same time by 32 bytes, but since it is divided into four banks, Bank A to Bank D, the bits of the address used to access each bank are
26'' arbitrarily, data within any 8 bytes within one block can be accessed at one time.

[Problem to be solved by the invention]

In such a configuration, if the required block is not in the buffer storage, a move-in is performed to read the block from the main memory to the buffer storage, but if there is no free block in the buffer storage at this time, For example, the known LRU (Least Recently
According to the algorithm of the ``Used'' method, a moveout is performed to remove one block from the buffer storage section to the main storage device.

If we apply the horizontal/vertical parity method to this buffer storage section and give horizontal parity to each byte, vertical parity will be applied to each bit (bits O to 7 and horizontal parity P) for all bytes in one block. This vertical parity is stored in the tag section 71, but there is a procedure for writing the vertical parity to the tag section 71 during a move-in operation and store access, or a procedure for error correction when a horizontal parity error is detected. There is a need for greater efficiency.

In particular, in store access, the new vertical parity depends on the current data at the store destination, the current vertical parity of the block at the store destination, and the store data, and an efficient way to handle this is also required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer storage control method that enables efficient hardware operation when horizontal and vertical parity is applied to a store iso type buffer storage section.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the data processing device includes a main storage device 11 and a store-in type buffer storage section 13 that holds a copy of data in the main storage device 11 in units of blocks.

A horizontal parity is provided for each of a plurality of segments obtained by subdividing data in a block, and a vertical parity is provided for each bit for each segment within the block.

The move-in processing means 15 writes vertical parity generated from move-in data into the buffer storage section 13 during move-in processing.

During store processing from the arithmetic unit, the store processing means 17 first reads the store destination data and the vertical parity of the block to which the data belongs, then generates a new vertical parity from these store data, and finally The store data and this vertical parity are written into the buffer storage section 13.

Furthermore, in the invention according to claim 2, when a horizontal parity error is detected when reading data from the buffer storage unit 13, the moveout processing means 19 generates vertical parity while reading all data in the block. Then, this vertical parity is compared with the true vertical parity held in the buffer storage unit 13 to detect error bits, and based on this, the 1-pin error in the data in the buffer storage unit 13 is corrected and the main Move out to the storage device 11.

[For production]

In addition to horizontal parity in units of bytes, the present invention has vertical parity for each bit for all bytes in a block, and during move-in processing, vertical parity generated from move-in data is written and stored from an arithmetic unit. During processing, by comparing the read vertical parity with the newly generated vertical parity and using it for error correction,
Particularly in store access, error correction can be efficiently performed according to the current data at the store destination, the current vertical parity, and the store data.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the buffer storage peripheral circuit according to the present invention.

In the figure, move-in data from the main memory is taken into a buffer data-in register (BDIR) 24 and a circuit A31 via a move-in data register (MIDR) 21. Further, store data from the arithmetic device is transferred to the buffer data in register 24 and the circuit B32 via the store data register (STDR) 22.
be taken in. The output of the buffer data in register 24 is stored in the buffer storage data section 25.

The byte mark input from the store control section is input to the circuit B32 via the byte mark register (BMR) 23.

The output data of the buffer storage data section 25 is sent to the selector 5.
1 to the align circuit 26, and further stored in the buffer data copy register (BDCR) 27,
The moveout data register (MODR) 28 and the fetch data register (F
CDR) 33. Fetch data register 3
The output of 3 is input to circuit B32, circuit C35, and corresponding parity check circuits 36 and 37. Vertical parity data from the buffer storage tag portion is stored in a vertical parity register (VFR) 34 and input to circuit B32 and circuit D38.

The output of circuit A31 is fed back via register 41. Further, the outputs of the circuit A31 and the circuit B32 are sent to the buffer storage tag section via the selector 54, and the output of the 0 circuit C35 is fed back via the register 42 and input to the circuit D38.

Further, the output of each parity check circuit 36, 37 is sent to a parity error detection register (PE) via a selector 55.
HR) 43, and further input to circuit D38. The output of circuit 03B is the moveout data register 2.
Incorporated into 8.

The output of the moveout data register 28 is sent to the selector 5.
6 through the memory request data register (MRQD
R) 29 and passed to main memory.

The operation of the circuit of this embodiment will be explained below with reference to the time charts of FIGS. 3 to 8.

Here, Fig. 3 shows fetch access, Fig. 4 shows store access, Fig. 5 shows move-in, Fig. 6 shows move-out,
Figure 7 shows the error processing when the change flag is 1;
The figure shows each operation of error processing when the change flag is 00.The operations that characterize the present invention are store access (Figure 4), move-in (Figure 5), and error processing ( 6 and 7).

First, the operation in fetch access will be explained with reference to FIG.

In the T cycle, the buffer storage tag section is read using bits "19" to "r25" (OOOOIOIC) of the T cycle logical address register, and the valid flag ■ is on and address bits "00" to "18" are -. Search for a way. Here, it is assumed that way 2 matches. In the following B cycle, the buffer storage data section 25 is read. Each way can read 32 bytes at the same time, but the fetch data is at the logical address r00001.
Since it is 8 bytes from "01c", it is byte r2B in one block.

~ "35" needs to be read, which would cross a 32-byte boundary.

Therefore, the address bits for reading the buffer storage data section 25 are bits "19" to "19" of the logical address.
"25", bank A is "1" as bit "26",
When bank D is accessed using bit “26” as “0”, all ways are read at the same time, but among them,
Way 2 whose tag part matches is selected.

In the following R cycle, the read 8-byte fetch data is rearranged by the align circuit 26 and set in the buffer data copy register 27. Also, the data within the two 8-byte boundaries that include that 8-byte data (
Here, data of bytes 24 to 31 and bytes 32 to 39) are set in the fetch data register 33.

Here, if an error is detected in the parity check circuits 36 and 37 corresponding to the fetch data register 33, the process enters an error processing step which will be described later.

Next, the operation in move-out will be explained with reference to FIG.

A move-out is a move-in operation in which a store has been stored in the move-in destination block in the past, or if the stored block is needed by another data processing device that shares the main memory. Φ in order to reflect the information in the main memory.

In Uni, the address of the block to be moved out (moveout address) and its writing number (
It is assumed that the way number) has been determined. The moveout request flows 4 times, and the 1 read in the B cycle
Sixteen byte data within six byte boundaries are set in each byte position of moveout data register 28 in sequence.

Further, the data set in the move-out data register 28 is once set in the memory request data register 29 in units of 8 bytes, and this is sent to the main storage device as 8-byte store data. Further, in the T cycle of the last request of the move-out, the valid flag of the corresponding block in the buffer storage tag section is set to OFF.

Although the above operations are no different from those of the prior art, operations that characterize the present invention are added to store access and move-in operations.

Next, the operation in store access will be explained with reference to FIG.

Note that store access is divided into two steps.

In the first step, the tag is searched in T cycles to see if the store destination block exists in the buffer storage section, and if it is found, the store address is set, and the matched way number is set.

In the next step, T cycle, the store data from the arithmetic unit is set in the store data register 22, and which byte of the 16-byte data (two pieces of data on 8-byte boundaries) in the store data register 22 is stored. A byte mark (16 bits) indicating whether the process has been performed is set in the byte mark register 23. At the same time,
Write "1" to the change flag C in the buffer storage tag section.

Furthermore, in the B cycle, the contents of the store data register 22 are written into the buffer storage data section 25 via the buffer data in register 24 with reference to the byte mark set in the byte mark register 23 .

The vertical parity is also changed when writing the tag part in the T cycle, and the method for generating this vertical parity will be described below.

Among the vertical parities of the tag part read in the T cycle of the first step of the store, the data of the way whose tag part matches is set in the vertical parity register 34. Furthermore, the data at the store destination location is set in the fetch data register 33 in the next cycle. This fetch data register 33 and the store data register 22 described above are both 16-byte registers, and each corresponding byte has the same address. The mark register 23 is set, but at this time, the circuit B3
2 generates a new vertical parity from each data in the fetch data register 33, store data register 22, byte mark register 23, and vertical parity register 34, and writes it into the buffer storage tag section.

Here, the function of the circuit B32 is the byte mark register 2.
Pies with valid byte marks indicated by 3) (00 to 15
), compare the values of the fetch data register 33 and store data register 22, and calculate the number of different bits for each bit (bits 0 to 7, parity bit P).
If there is an even number difference, the corresponding vertical parity is left as is, and if it is an odd number difference, the corresponding vertical parity is inverted. FIG. 9 shows this situation.

That is, bytes 04.05.06.07.08.09.10. whose value in the byte mark register 23 is "1".
11, and comparing the values (hexadecimal representation) of the fetch data register 33 and store data register 22 for each bit, -byte 06 has bits 0.1.2.
3.4.5.6.7 are different, byte 07 is bit 4.
5.6, P (parity bit) is different. therefore,
Since bits 0.1.2.3.7 and P differ by an odd number, the vertical parity is inverted, and bits 4,5.6 differ by an even number, so the vertical parity is left unchanged.

Next, the operation in move-in will be explained with reference to FIG.

When a move-in request is issued to main memory with the address (move-in address) in main memory of a block that requires move-in, the move-in data is sent from main memory in eight bytes each. It will be sent to you. The sent move-in data is set in the move-in data register 21, and when the first half 32 bytes are completed, it is sent via the buffer data-in register 24 to the corresponding way of the buffer storage data block 25 indicated by the move-in write number. will be written to.

Also, the latter 32 bytes are move-in data register 2.
When the numbers are all 1, they are similarly written to the corresponding way of the buffer storage data block 25. Two move-in requests flow through the pipeline, and in the T cycle of the latter step, a valid flag, address, and vertical parity, which is a feature of the present invention, are written in the buffer storage tag section.

The method for generating vertical parity will be described below. The register 41 is reset when a move-in request is issued to the main memory. First half of move-in data 32
When the bytes are set in the move-in data register 21, vertical parity for these 32 bytes is generated in the circuit A31 and set in the register 41. Also, when the latter half 32 bytes of the move-in data are set in the move-in data register 21, the circuit A31 generates vertical parity for these 32 bytes, and stores the previously determined first half 32 bytes in the register 41. Vertical parity of 64 bytes is generated by combining the vertical parity of .

The output of circuit A31 is passed to the buffer storage tag section and written to the tag section in T cycles of the latter step of the move-in request.

Next, the operation in error processing when the change flag is "1" will be described with reference to FIG.

The basic operation for processing this error is that when an error is detected in the buffer storage data section 25, the 1-bit error is corrected, the error is moved out to the main memory, and the buffer storage section turns off the valid flag. It is invalidated by setting it to .

That is, in an access (fetch access, store access) for reading the buffer storage data section 25, data in units of 16 bytes is read to the fetch data register 33. When the parity check circuits 36 and 37 detect a horizontal parity error for the fetch data register 33, the address at the time of the error (error address) is
Then, the error address write number indicating the way number in which the error occurred is held, and the byte position in which the error occurred is held in the parity error detection register 43, and the error processing step begins.

Here, if the change flag C of the block in error is 1 (on), four flows of pipeline requests flow during error processing. These steps are basically the same as for a moveout; the data read out in 16-byte units is set in the moveout data register 28, and in the final step, the tag section is written to set the valid flag to 1. It will be done. Also, moveout data register 2
After error correction, the data on 8 bytes are sent to the main memory via the memory request data register 29 in units of 8 bytes.

Here, a method for correcting errors in data on the move-out data register 28 will be explained.

When an error is detected by the parity check circuits 36 and 37, the register 42 is reset.

When the 16-byte data read in the error processing step is set in the fetch data register 33, the circuit C35 generates vertical parity in units of 16 bytes and holds it in the register 42. In subsequent steps, vertical parity for the amount read so far is generated based on the 16-byte data read to the fetch data register 33 and the value of the register 42, and is held in the register 42. When the 16-byte data is read into the fetch data register 33 in the fourth step, the circuit C35 outputs the vertical parity of 64-byte data including 1-bit error.0 The circuit D38 outputs this value and the vertical parity. A simple comparison of the values in the register 34 is performed to detect the bit position where the error occurred (bits θ to 7, P). Also, since circuit D38 inputs the value of parity error detection register 43, the output of this circuit indicates the byte and bit in error. The output of this circuit D38 is sent directly to the move-out data register 28, the bits of the indicated byte are inverted, and this corrected data is sent to main memory.

Although the data after error correction is moved out here, after the error is corrected in the move-out data register 28 by the output of the circuit D3B, a new path is created from there to the buffer data-in register 24. Also, by sending a new pipeline request, data in the buffer storage unit can be easily rewritten.

Next, with reference to FIG. 8, the operation in error processing when the change flag is "0" will be described.

The operation performed after detecting a horizontal parity error in the fetch data register 33, that is, setting the error address and error address write number (way number), is the same as when the change flag is "1". However, if the change flag is "Oj", a write is made to the buffer storage tag part so that only one error handling vibe line request is sent, and the valid flag of the corresponding block is set to 1 in the T cycle of this request. I do.

〔Effect of the invention〕

As described above, according to the present invention, horizontal parity is provided for each segment between the main storage device and the store-in type buffer storage section that holds copies of the data in blocks. By having a vertical parity for each bit, it is possible to perform efficient (error correction) by comparing the read vertical parity with the newly generated vertical parity during store processing.

[Brief explanation of drawings]

11th! 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the configuration of the data bus circuit around the buffer storage unit in the present invention, FIG. 3 is a time chart explaining the fetch access operation, and FIG. is a time chart explaining the store access operation, Figure 6 is a time chart explaining the move-in operation, Figure 6 is a time chart explaining the move-out operation, and Figure 7 is the error time when the change flag is "1". Figure 8 is a time chart explaining the processing operation of
FIG. 9 is a diagram explaining the operation of circuit B. FIG. 10 is a diagram explaining horizontal parity and vertical parity. FIG. 11 is a diagram explaining the conventional buffer. FIG. 2 is a block diagram showing an example of the configuration of a storage unit. In the figure, 11 is a buffer storage unit, 13 is a main storage device, 15 is a tag unit, 17 is a partial change flag processing means, 19 is a move-out processing means, 21 is a move-in data register (MIDR), and 22 is a store data register. (STDR), 23 is a byte mark register (BMR), 24 is a buffer data in register (BDIR), 25 is a buffer storage data section, 26 is an align circuit, 27 is a buffer data copy register (BDCR) 28
is a move-out data register (MODR), 29 is a memory request data register (MRQDR), and 31 is a circuit A. 32 is a circuit B1, 33 is a fetch data register (FCDR), 34 is a vertical parity register (VPR), 35 is a circuit C1, 36 and 37 are parity check circuits (PCK), 38 is a circuit D, 41.42 is a register, 43 is a Parity error detection register (PEHR) 51~
56 is a selector. A block diagram of the principle of the present invention. A diagram explaining the operation of circuit B. FIG. 9 A collection of illustrations explaining horizontal parity and vertical parity.
January 29, 1991 Commissioner of the Japan Patent Office Satoshi Uematsu Patent Application No. 278605 of 1990 Name of the invention Buffer storage control method Person making the amendment Relationship with the case Patent applicant Address Kanagawa 1015 Kamiodanaka, Nakahara-ku, Yozaki-shi, Ken. Name (522) Fujitsu Limited Agent 151 ft. (03) 3375-1631
Address: 1991, 2-11-2 Yoyogi, Shibuya-ku, Tokyo
January 22, 2019 (Shipping port) Contents of the amendment in the brief explanation of drawings in the specification subject to amendment

Claims (2)

[Claims] (1) A data processing device comprising a main storage device (11) and a store-in type buffer storage section (13) that holds a copy of data in the main storage device (11) in block units, wherein the data processing device comprises: horizontal parity in units of multiple segments obtained by subdividing the data of the block, and vertical parity for each bit for each segment in the block, and during move-in processing, the vertical parity generated from the move-in data is stored in the buffer storage section. (13) During store processing from the arithmetic unit, the move-in processing means (15) writes data to the store data and the vertical parity of the block to which the data belongs first, and then reads the new vertical parity from these store data. A buffer storage control system characterized by comprising a store processing means (17) that generates parity and finally writes store data and this vertical parity into the buffer storage section (13). (2) In the buffer storage control method according to claim 1, when a horizontal parity error is detected when reading data from the buffer storage section (13), vertical parity is generated while reading all data in the block. Then, this vertical parity is compared with the true vertical parity held in the buffer storage unit (13) to detect an error bit, and based on this, one bit of data in the buffer storage unit (13) is detected. A buffer storage control system characterized by comprising a moveout processing means (19) for correcting errors and moving out to a main storage device (11).