JPH04152431A - High speed operating method for horizontal processor - Google Patents

Abstract

PURPOSE:To shorten the decoding time and to increase the operating speed of e horizontal. processor by predecoding all fields and storing them in a control memory. CONSTITUTION:An instruction decoder 18 decodes the fields F2-F5 and F8 which are stored in a main control memory 14a and gives the decoding results f2-f5 and f8 to a control circuit 19. Meanwhile the decoding results f1-f6 and f7 stored in a shadow memory 14b are given to the circuit 19 as they are. The circuit 19 prepares a control signal 20 from all received results f1-f8 and controls each part of a horizontal processor.

Description

[Detailed Description of the Invention] [Summary] A method for increasing the data processing speed of a horizontal processor while maintaining compatibility with existing microprograms, using existing software and data resources as they are. The aim is to realize a processor that is capable of high-speed operation and stores coded horizontal micro-instructions in a control memory section, and an instruction decoding section reads and decodes the micro-instructions, and uses the decoded results as a processor. In a microprogram-controlled horizontal processor in which the instruction execution unit is controlled based on the instruction execution unit and executes instructions, when loading the microprogram into the control memory unit, a pre-decode unit having the same decoding function as the instruction decode unit , the microprogram is decoded in advance and then loaded into the control memory section, and when the instruction execution section executes an instruction, it is configured to operate under the control of the decoding result stored in the control memory section.

[Industrial Application Field] The present invention relates to a method for increasing the data processing speed of a horizontal processor while maintaining compatibility with existing microprograms.

There are two types of microprogram-controlled processors: horizontal processors, in which the length of the instruction word executed by the processor is always constant regardless of the type of instruction, and vertical processors, in which the length of the instruction word changes depending on the type of instruction. There is.

Horizontal processors have a larger control memory capacity for storing microprograms than vertical processors. On the other hand, horizontal processors are faster when processing data, and are used when high-speed data processing is desired.

By the way, there is no end to the social demand for faster data processing speeds, and processors with faster processing speeds are being developed and designed one after another.

However, if a newly developed or designed processor is not program-compatible with existing processors, the program resources and data resources that have been developed and used up to that point will be discarded. become.

Therefore, there is a need for a method for increasing data processing speed while maintaining program compatibility.

The present invention particularly relates to a method for increasing data processing speed in a microprogram-controlled horizontal processor.

[Prior Art] A microprogram-controlled horizontal processor is controlled and operated by horizontal microinstructions.

FIG. 4 is a diagram illustrating the format of horizontal microinstructions.

In other words, a horizontal microinstruction (hereinafter simply referred to as a microinstruction) has a fixed number of n bits as a whole, as shown in the figure, and it is divided into several parts according to the purpose of use and is divided into one instruction word. It constitutes M. In addition, each section F,,F
□, F3. ... is a field.

Then, each field Fl+FZ+F3. ...The information necessary to control the processor is stored in coded form, and these codes are decoded (deciphered) by the processor when executing instructions, and finally the necessary binary information is stored. I am getting .

For example, for each field F++F2+h+...
LU(ARITHMETICAND LOGICUNI
T) calculation designation information, input bus designation information, output bus designation information, etc. are assigned.

By the way, a certain amount of time is required to decode the code of each field Fl+h+F:I+. Therefore, if all the information in each field Fl+F2+h+ . . . is expressed in binary numbers, it is theoretically possible to realize a processor that operates at the highest speed.

However, if all the information in each field FI+h+Fy+ .

Therefore, usually, the processing speed of the processor is sacrificed to some extent to store coded information in each field F+Jz+F3+ . . . and decode it at the time of instruction execution to obtain the desired binary information.

In other words, it can be said that the reason for encoding is to shorten the word length of the microinstruction.

Next, a microprogram control type processor will be explained.

FIG. 5 is a block diagram illustrating the basic configuration of the processor. Note that, in the figure, the control circuit of the processor and the like are omitted.

That is, the coded microinstruction is stored in the control memory section 3.
The micro instructions are stored in the instruction decoding section 5.
reads and decodes it, and the instruction execution unit 6 is controlled based on the decoding result to execute the instruction.

The bootloader section 1 loads the microprogram from the floppy disk 2 into the control memory 3, and the section 110 inputs and outputs data to the processor 4.
This is part 7.

FIG. 6 is a block diagram illustrating a processor that uses microinstructions that partially include binary information.

That is, the processor uses microinstructions that express fields that require speeding up using binary information, and encode and represent fields that do not need speeding up.

In other words, it is a processor that expresses fields that require a long time to decode in binary information when microinstructions are coded, thereby reducing the decoding time.

Therefore, the coded fields of the microinstructions stored in the control memory unit 3 are stored in the instruction decoding unit 9.
reads out and decodes it, and controls the instruction execution unit 10 based on the decoding result, and also reads out the binary information representation field as it is to control the instruction execution unit 10.

In the figure, the microinstructions stored in the control memory section 3 are read out in parallel output.

[Problems to be Solved by the Invention] The horizontal processor 8 shown in FIG. 6 operates at a higher speed than the horizontal processor 4 shown in FIG.

However, there is no compatibility at all at the microinstruction level.

That is, while the horizontal processor 4 in FIG. 5 uses coded microinstructions, the horizontal processor 8 in FIG. 6 uses microinstructions that partially have fields using binary information representation. This is because it is used.

Therefore, it is not possible to increase the data processing speed by replacing the horizontal processor 8 shown in FIG. 6 with the horizontal processor 4 shown in FIG. 5.

In other words, microprogram compatibility cannot be obtained, and valuable software and data resources that have been historically accumulated up to that point will be thrown away.

Incidentally, although the processor 4 and the processor 8 themselves operate in machine language, the program for operating the processors is provided as source code in a high-level language or the like.
In a processor that translates the source code to obtain machine language each time the processor executes an instruction, and executes the instruction in the machine language, even if the processor is replaced with a faster processor by changing the microinstructions, By re-providing users with compilers and cross-assemblers for translating source code, software compatibility can be maintained.

However, for processors that can only process programs in translated machine language, it is necessary to retranslate and provide all the source code that the user has, which is a huge amount of work, so in reality it is almost impossible to do so. It's impossible.

The technical problem of the present invention is to solve the above-mentioned problems in increasing the data processing speed of a horizontal processor, and to establish a method for shortening the decoding time of microinstructions and increasing the data processing speed. By doing so, we can speed up the processor while maintaining software compatibility without changing the machine language, and realize a processor that operates at high speed and can use existing software and data resources as is. There is a particular thing.

[Means to solve the problem]

FIGS. 1(a) and 1(b) are block diagrams illustrating the basic principle of the present invention.

The present invention is characterized in that the microprogram is decoded in advance and then stored in the control memory.

That is, coded horizontal micro-instructions are stored in the control memory section, the instruction decoding section 5 reads and decodes the micro-instructions, and the instruction execution section 6 is controlled based on the decoding result to execute the instructions. The microprogram-controlled horizontal processor 4 is configured as follows to increase speed.

First, the first method will be explained. (FIG. 1(a)) That is, when loading a microprogram into the control memory section 3A, the microprogram is decoded in advance by a pre-decoding section 11a having the same decoding function as the instruction decoding section 5. When loading the instruction into the control memory section 3A and the instruction execution section 6 executes the instruction, this is a high-speed method in which the operation is controlled by the decoding result stored in the control memory section 3A.

Next, the second method will be explained. (FIG. 1(b)) That is, in order to store the microprogram, a control memory section 3B consisting of two parts, a first control memory section 3a and a second control memory section 3b, is prepared, and the microprogram is stored in the control memory section 3B. When coding in the control memory section 3B, the pre-decoding section 11b, which has the same decoding function as the instruction decoding section 5, codes the fields required by the microinstruction, that is, the fields that require a relatively long time to decode the microinstruction. , pre-decode one second
Fields to be loaded into the control memory section 3b and not to be decoded are loaded into the other first control memory section 3a, and when the instruction execution section 6 executes an instruction, the instruction decoding section 5 is loaded into the first control memory section 3a. 3a and the decoding result stored in the second control memory section 3b.

The boot loader section 1a loads the microprogram, and the processor 4 inputs and outputs data to the 110 section 7.

C Effect] In the case of the first method, the control memory 3A stores the decoding results of the microinstructions.

Therefore, when the instruction execution section 6 operates based on a microinstruction, the decoding operation by the instruction decoding section 5 is not necessary.

Therefore, the instruction execution unit 6 can be immediately controlled and operated based on the microinstructions stored in the control memory 3A.

As a result, the data processing speed of the processor 4 is increased by an amount corresponding to the decoding time of the microinstruction.

Further, since the pre-decoding section 11a has the same decoding function as the instruction decoding section 5, program compatibility is maintained.

In the case of the second method, the second control memory 3b stores the decoding results of fields that require a relatively long time to decode microinstructions. Further, fields that do not require much decoding time are stored as they are in the first control memory section 3a.

Therefore, when the instruction decoding unit 5 decodes a microinstruction, the decoding is completed in a relatively short time. That is, this is because the pre-decoding section 11b completes the decoding of the field that requires a long decoding time in advance, and stores the decoding result in the second control memory section 3b.

Therefore, when the instruction decoding section 5 completes decoding, the instruction execution section 6 stores the decoding result and the second control memory section 3b.
It can be controlled and operated based on the memory contents of.

As a result, the data processing speed of the processor 4 is increased by the amount that the decoding time of the instruction decoding section 5 is shortened.

Furthermore, since the pre-decoding section 11b has the same decoding function as the instruction decoding section 5, program compatibility is maintained.

[Examples] Next, examples will explain how the method according to the invention can be implemented in practice.

(1) Configuration FIG. 2 is a block diagram explaining the embodiment.

That is, the processor 15 of this embodiment performs the calculation
The internal bus 1 includes an LU 24, accumulators 22 and 23, a register group 25 including general-purpose registers, a program counter, a stack pointer, etc., and a data bus buffer 27.
6.

On the other hand, there is a control circuit 19 that controls each section, an instruction decoder 18 decodes the microinstruction fetched into the instruction register 17, and the control circuit 19 controls each section based on the decoding result.

On the other hand, the control memory 14 that stores and stores microprograms includes a main control memory 14a and a shadow memory +J14.
RAM (RANDOM ACCESS ME gate 0RY), which has a short read time, is used as the memory element. The name Shadow Memory is
The name comes from the fact that it is a type of memory that programmers are completely unaware of.

The boot loader 12 is the part that codes the microprogram in the control memory 14, and is loaded from the floppy disk 2. Of the instruction word fields, the fields that require a long decoding time are decoded by the predecoder 13 and then stored in the shadow memory 14b, and the other fields are stored in the main control memory 14 as they are.

Note that the predecoder 13 has the same decoding function as the instruction decoder 18 for the field to be decoded.

(2) Operation FIG. 3 is a block diagram illustrating the operation of the main parts of the embodiment.

In the figure, M is one instruction word, and F, to F8 indicate each field of the instruction word. Further, Ma consists of fields Fz, h, Pa, Fs, Fs, and Mb consists of fields Fl, F6 . F? Consists of.

Each field F I''F s has, for example, the following control designation.

■F,...ALU calculation specification ■F2...Power bus specification ■F3...Input bus specification ■F4...Output bus specification ■F,...Program counter increment specification ■
F6...Main memory operation specification ■F7...State control specification ■F8...Next microinstruction address And, in this embodiment, among the fields F1 to F, fields Fl, F6... The example is shown as requiring a relatively long decoding time for FT.

That is, fields F, , F6 . After predecoding F, via the predecoder 13, the decoding result f+
, fb, and f7 are stored in the shadow memory 14b. On the other hand, field F2. F3+ F4+ FS
+Fs is stored as is in the main control memory 14a.

Therefore, the instruction decoder 18 has the main control memory 14a.
Fields Fz+Fs, Fn, P stored in
s, Fs, and the decoding results fz, fs, f
a, fs, and fs are given to the control circuit 19. On the other hand, the decoding results f, , f stored in the shadow memory 14b
, , f7 are supplied to the control circuit 19 as they are.

Then, the control circuit 19 receives the total decoding result B.
, fz, fs, fa, fs, fh, fr, and fs to generate a control signal 20 to control each part of the processor 15.

Therefore, one instruction word M of the microprogram stored in the control memory 14 is read out, and the decoding result is sent to the control circuit 19, fz, fi, fn, fs, f6.
Considering the time it takes to provide +f and +fe, the main time is when the instruction decoder 18 inputs fields F2 . F3
The time to decode +F4+Fs+F8 is dominant.

That is, the field Fl, which requires a long decoding time,
F6. Since the FT has been decoded in advance, the decoding time is shortened and the control signal 20 output from the control circuit 19 is
can be obtained in a short time. Therefore, each part of the processor 15 is immediately controlled and its operating speed is increased.

As described above, the instruction word M remains the same and the processor 15
The operating speed, that is, the data processing speed can be increased. Furthermore, the programmer does not need to be aware of the predecoder 13 or the shadow memory 14b at all.

Note that in this embodiment, the reason why only the fields that require a relatively long decoding time are predecoded without predecoding all fields F, to F8 is that the capacity of the shadow memory 14b becomes unlimitedly large. This is a measure to effectively increase processing speed with a small memory capacity.

(3) Example of execution result Each field F, -F of the instruction word M contains information coded in 8 bits, and each logic circuit of the processor is -ASTTL, which is commercially available for boat fishing. An example is shown in which a system is configured using a system IC.

In the above-described processor, approximately 70 ns is required to process one instruction due to the delay time of each logic.

Further, among the instruction processing time, the decoding time until the instruction decoder obtains binary information is about Ions.

Therefore, if all fields F, -F8 are pre-decoded and then stored in the control memory, the decoding time described above becomes unnecessary, and one instruction process is completed in about 60 ns.

In other words, a speed increase of about 14% can be achieved.

[Effects of the Invention] As described above, according to the method of the present invention, by decoding the microprogram in advance and storing it in the control memory, the decoding time of the microprogram is shortened, and the operating speed of the pro-sensor is increased. Speed up. Also,
Software compatibility can also be maintained.

As a result, it is possible to realize a horizontal processor that operates at high speed and can use existing software and data resources as they are.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are block diagrams explaining the basic principle of the present invention, Figure 2 is a block diagram explaining an embodiment, and Figure 3 is a block diagram explaining the operation of the main parts of the embodiment. Block diagram: Figure 4 is a diagram explaining the format of a horizontal microinstruction; Figure 5 is a block diagram explaining the basic configuration of the processor; Figure 6 is a microinstruction partially containing binary information. FIG. 2 is a block diagram illustrating a processor using the . In the figure, 1. la, lb are bootloader sections, 2
is a floppy disk, 3.3A and 3B are control memory sections, 3a is a first control memory section, 3b is a second control memory section,
4.8.15 is a processor, 5 and 9 are instruction decoding units,
6゜10 is the instruction execution section, 7 is the 110th section, 11a, 11
12 is a boot loader, 13 is a BRIDGE decoder, 14 is a control memory, 14a is a main control memory,
14b is a shadow memory, 16 is an internal bus, 17 is an instruction register, 18 is an instruction decoder, 19 is a control circuit, 20
21 is a control signal, 21 is a clock, 22, 23 is an accumulator, 24 is an ALU, 25 is a register group, 26 is an address bus, 27 is a data buffer, and 28 is a data bus. Patent applicant Fujitsu Co., Ltd. sub-agent Patent attorney Yasushi Fukushima J30

Claims (1)

[Claims] 1. Store coded horizontal micro-instructions in a control memory section, and store the micro-instructions in an instruction decoding section (5).
) reads and decodes the microprogram, and the instruction execution unit (6) is controlled based on the decoding result to execute the instructions.In the microprogram control type horizontal processor (4), the microprogram is stored in the control memory unit (3A). When loading, a pre-decoding section (11a) having the same decoding function as the instruction decoding section (5) decodes the microprogram in advance and loads it into the control memory section (3A). (6) A method for increasing the speed of a horizontal processor, characterized in that when executing an instruction, the operation is controlled by the decoding result stored in the control memory unit (3A). 2. Store the coded horizontal micro-instructions in the control memory section, and transfer the micro-instructions to the instruction decoding section (5
) is read out and decoded, and the instruction execution unit (6) is controlled based on the decoding result to execute instructions. A control memory section (3B) consisting of two parts, a control memory section (3a) and a second control memory section (3b) is prepared, and when loading a microprogram into the control memory section (3B), the instructions are A pre-decoding section (11b) having the same decoding function as the decoding section (5) decodes the fields required by the microinstruction in advance and loads it into one second control memory section (3b) for decoding. If the instruction execution unit (6) executes an instruction, the instruction decoding unit (5) reads out the first control memory unit (3a). A method for increasing the speed of a horizontal processor, characterized in that the operation is controlled by a decoding result decoded by the second control memory section (3b) and a decoding result stored in the second control memory section (3b).