JPH04151567A - Electronic type watthour meter - Google Patents

Abstract

PURPOSE:To make it possible to remove an offset voltage which is overlapped in an OP amplifier and the like, to decrease measuring errors and to improve accuracy by inputting the divided voltage at the midpoint between impedance elements into the input terminal of an inverted integrator. CONSTITUTION:Integrated outputs eop and eon, on which an offset voltage eos is superimposed, respectively, are outputted to switches Sa and Sb from a multiplier 5. Then, the voltage at a midpoint (a) between resistors R6 which are connected in series becomes the sum of the divided voltage (eop+eon)/2 and the offset voltage +eox. Since the divided voltage eop+eon becomes zero, however, the midpoint voltage becomes only the voltage eos. The voltage eos is detected at the ground level of a power supply and taken out. The voltage oos is inverted at the inverted input terminal of an OP amplifier A3 and becomes the voltage -eos. Furthermore, the voltage -eos and the voltage +eos which is intrinsically present in the amplifier A3 are offset and integrated. Thus, the influence caused by the offset voltage on an electronic type watthour meter is eliminated. Therefore, the measuring errors can be decreased.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to an electronic watt-hour meter that measures the amount of electric power.

(Prior Art) FIG. 3 is a block diagram showing a conventional electronic watt-hour meter. In the figure, auxiliary transformers 1 and 3 convert signals proportional to the load voltage of the distribution line, and auxiliary current transformers 2 and 3 convert signals proportional to the load voltage of the distribution line.
4 is for converting into a signal proportional to the consumed current. Pulse width modulation time division multiplication circuit (power-voltage conversion circuit) 5,
6 calculates electric power from the signals from the auxiliary current transformers 1 and 3 and the auxiliary transformer 2.4. The voltage-frequency conversion circuit 7 integrates the outputs of the pulse width modulation time division multiplication circuits 5 and 6 and converts them into pulses, and the display section 8 displays these pulses.

FIG. 4 shows a pulse width modulation time division multiplication circuit 5 as a multiplier.
, 6, and FIG. 5 is a diagram showing a voltage-frequency conversion circuit 7 as an integrator.

As shown in FIG. 4, OP amplifier A1 constitutes an integrator with resistor R1 and capacitor C1, and comparator A2
The integrated output from the amplifier AI is input, and a logic output is generated by comparing it with a comparison voltage eh generated by hysteresis. The switch 5t-54 is controlled by the output of the comparator A2.

First, the operation at ev-0 will be explained. Comparator A2
Assume that the output of is set to logic "1". Then, the inverting input terminal voltage eh of the comparator A2 becomes -er/2 due to the equal dividing resistors R1. The output er of the comparator A2 is input to the integrator by the resistor R1, and the output of the OP amplifier A1 exhibits an integration slope in the negative direction. When this integral value reaches -er/2, the comparator A2 is inverted and becomes logic "0".

Then, er/2 is applied to the inverting input terminal e'h of comparator A2, and -e' is applied to the integrator, so
The output of OP amplifier A1 shows an integral slope in the positive direction. When this integrator reaches e r /2, comparator A2 is inverted and becomes logic "1".

In this way, at ev-0, self-sustained oscillation is repeated. That is, a pulse with a duty of 1 is generated.

Next, the operation when input signal ev is applied will be explained. The time period in which the output of the comparator A2 is logic "1" is t3. Assuming that the time section of logic "0" is tb, the output of the integrator in each section is as follows.

ek (ta) --(, l' ev d t + fer d t)
/RI C1-ta (ev +er) /
RI C1-er ek (tb) --Cf ev d t +fer d
t) /RI C1-tb (er -ev
) /RI C1 deu e" ta-er RI C1/ (er +ev
)tb-er RI C1/ (er-ev)
It is. From the above, when examining the ratio, duty, and cycle of changes in ta and tb due to er, we find that D - ta/ (ta + tb) - (er - ev )/2er D - tb / (ta + tb) - (er + e
V)/2er, and this output causes the analog switches 81 to S
Drive 4. This leads to ei, and when it is integrated by low-pass filter resistor R2 and capacitor C2, eop=el (D) +
(-ei) D-eve1/er eon-el (D) + (-ei) D-ev
eI/er is obtained, and a multiplication output proportional to the product of voltage signal ev and current el can be obtained.

Next, the operation of the integrator shown in FIG. 5 will be explained. It has the same configuration as the multiplier shown in FIG. 4 above.

That is, OP amplifier A3 constitutes an integrator, A4 is a hysteresis comparator, and S a and S b are switches.

By opening and closing switch Sa or sb, switch Sa,
The voltage e2 at the common connection terminal of Sb is such that the voltages eop and eon from the multiplier are taken in alternately.

First, in the interval tc, the switch Sa is turned on and eop is inputted, and in the interval td, the switch sb is turned on and eon is inputted to perform integration.

At the same time, comparator A4 has a reference voltage ec for comparison.
is applied with hysteresis, and in the interval tc, ec-
-ep/2. In interval td, ee''+e9/2 is applied to the inverting input terminal of comparator A4.

In the interval tC, since the positive input voltage eoρ is introduced into the integrator, the integral output eq decreases, and the comparator A4 becomes
It is reversed when C9 reaches -ep/2. Here, it is switched to section td. In the interval td, the negative input voltage eon is introduced into the integrator, so the integrator output eq increases. Then, the process returns to section tC again.

Therefore, the inversion period 10 of the comparator A4 becomes to-tc +td-ep-R3·C3/10ep-R3C3/-2ep-er R3C3. Therefore, the output frequency f0 Qp On /eI aev becomes fO-ei-ev/2ep-e "・R3C5.Here, ep and er are reference voltages, so the output frequency fO is e
It is proportional to v-ei, that is, the power consumption in the feeder line. The power consumption in the power supply line is displayed on the display circuit 8 using this output frequency fO.

However, the aforementioned OP amplifier At, comparator A2, and multiplier output voltages eop and eon include an offset voltage, and there is a problem in that the error of the watt-hour meter increases due to the influence of this offset voltage. Therefore, conventionally, the influence of the offset voltage has been eliminated by using an integrator 10 shown in FIG. 6 to which an error elimination circuit is added. This integrator IO is connected between the inverting input terminal of the OP amplifier A3 serving as the multiplier and the inverting buffer 11. An integrator 12 composed of a capacitor C4 and resistors R4 and R5 is connected in antiparallel. The output is integrated by this integrator 12 to detect the offset voltage eos shown in FIG. 7, and this detected voltage is fed back to the inverting input terminal of the OP amplifier A3 in the voltage-frequency conversion circuit 7 to automatically adjust the offset voltage. That's what I was doing.

(Problem 8 to be solved by the invention) However, the above conventional circuit system has the following problems. In other words, the OP amplifier A5 used in the automatic offset voltage adjustment circuit also contains offset voltage, and there is also a small amount of offset voltage on the current circuit side (for example, auxiliary current transformer 2.4, etc.), so these There has been a problem in that the offset voltage causes measurement errors in electronic watt-hour meters.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an electronic watt-hour meter that can remove as much as possible the offset voltage superimposed on an OP amplifier, etc., and improve the accuracy of the watt-hour meter against measurement errors.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems and achieve the objects, the present invention takes the following measures. In other words, the present invention includes an auxiliary transformer that converts the signal into a signal proportional to the load voltage, an auxiliary current transformer that converts the signal into a signal proportional to the load current, and a system that calculates power from the auxiliary current transformer and the signal from the auxiliary transformer. An electronic watt-hour meter comprising: a multiplier using a pulse width modulation time division multiplication method; an integrator that converts the output of the multiplier into pulses; and a display section that displays the output of the integrator. An impedance element is connected to both ends of the multiplier output, and the divided voltage at the midpoint of the impedance element is input to the input end of the integrator.

(Effects) By taking such measures, the following effects will be exhibited. The voltage across the output of the multiplier e Qp.

Since an offset voltage (+e os) is superimposed on each of eon, the midpoint voltage of the resistors connected in series is the sum of the divided voltage (eop+eon)/2 and the offset voltage (+e os). . These voltages are then detected and extracted from the ground level of the power supply,
This detection voltage is inverted by an integrator and the offset voltage (-
eos). Furthermore, the offset voltage (-eos) and the offset voltage (+e o
s) are canceled out and integrated, so the offset voltage can be largely removed. As a result, measurement errors in the electronic watt-hour meter due to the offset voltage are reduced, and changes in the offset voltage over time can be eliminated, resulting in a highly accurate and stable watt-hour meter.

(Embodiment) FIG. 1 is a configuration diagram showing an embodiment of an offset voltage adjustment circuit in an electronic watt-hour meter according to the present invention. Note that the same parts as those explained in FIGS. 3 to 7 will be described with the same reference numerals. This offset voltage adjustment circuit 20 is configured as follows.

Switches Sa and Sb provided in the voltage-frequency conversion circuit 7 are connected to integral both-end outputs e op and e on of the pulse width modulation time division multiplication circuit 5 as a multiplier, respectively. Also, the outputs at both ends of the multiplier e op.

eon has a dividing resistor R6 that is equal to the counterpart and connected in series.
is connected from the midpoint a of this dividing resistor R6 to (eop+
eon)/2 is taken into the inverting input terminal of the operational amplifier A3 via the resistor R7.

FIG. 2 is a diagram showing the offset voltage eos at the midpoint a. The output voltage across the multiplier e op.

An offset voltage eos is superimposed on each Eon. The voltage at midpoint a is the divided voltage (eop+
eon) / 2 and the offset voltage (eos + eo
s)/2, that is, the sum of eos.

Next, the operation of the embodiment configured as described above will be explained. First, it is assumed that the integral outputs eop and eon, which are respectively superimposed with the offset voltage eos from the multiplier 5, are output to the switches Sa and Sb. Then, the voltage at the midpoint a of the resistors R6 connected in series is the divided voltage (e□p+e
on)/2 and the offset voltage (+eos). Note that the output voltage e op.

Since the positive and negative phases of eon are equal, the divided voltage (e Op+ e
on) becomes zero, and the midpoint voltage is the offset voltage eo
Only s is available. This offset voltage eos is detected and taken out from the ground level of the power supply, and this detected voltage eos is inverted at the inverting input terminal of the OP amplifier A3 to become an offset voltage (-eos). Furthermore, since the offset voltage (-eos) and the offset voltage (10eos) originally present in the OP amplifier A3 are canceled out and integrated, the offset voltage can be largely removed. As a result, the influence of the offset voltage on the electronic watt-hour meter is eliminated, and measurement errors can be reduced. Moreover, since it is possible to remove changes in the offset voltage over time, it is possible to provide a highly accurate and stable electricity meter.

Note that the present invention is not limited to the embodiments described above. In the above-mentioned embodiment, the offset voltage was removed by the offset voltage adjustment circuit 20, but if the offset voltage adjustment circuit 2o and a conventional offset voltage automatic adjustment circuit are used together, the offset voltage can be further reduced than in the above-mentioned embodiment. Can be removed. It goes without saying that various other modifications can be made without departing from the gist of the invention.

[Effects of the Invention] According to the present invention, there is an auxiliary transformer that converts the signal into a signal proportional to the load voltage, an auxiliary current transformer that converts the signal into a signal proportional to the load current, and an auxiliary current transformer and an auxiliary transformer. An electronic multiplier that uses a pulse width modulation time division multiplication method to calculate power from a signal, an integrator that converts the multiplier output into pulses, and a display unit that displays the integrator output. In the watt-hour meter, an impedance element is connected to both ends of the output of the multiplier, and the divided voltage at the midpoint of this impedance element is taken into the input terminal of the integrator that is inverted, so that the offset superimposed on the divided voltage is The voltage and the offset voltage superimposed on the integrator are canceled and integrated. As a result, the offset voltage of the OP amplifier, etc. can be largely removed, so measurement errors can be reduced, and changes in the offset voltage over time can be removed, so a highly accurate and stable electronic watt-hour meter can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an offset voltage adjustment circuit in an electronic watt-hour meter according to the present invention, and FIG. 2 is a diagram showing an offset voltage at a midpoint. Fig. 3 is a block diagram showing a conventional electronic watt-hour meter, Fig. 4 is a diagram showing a pulse width modulation time division multiplication circuit, Fig. 5 is a diagram showing a voltage-frequency conversion circuit, and Fig. 6 is a diagram showing error removal. FIG. 7 is a diagram showing an integrator with an added circuit, and FIG. 7 is a diagram showing a detection voltage of an offset voltage. 1.3...Auxiliary transformer, 2,4...Auxiliary current transformer, 5
．． 6...Pulse width modulation time division multiplication circuit, 7゜10...
・Voltage-frequency conversion circuit, 8...Display circuit, 11...
Inverting buffer, 12 Integrator, 20 Offset voltage adjustment circuit, AI, A3...OP amplifier, A2゜A4...
・Comparator, Sa, Sb...switch, eos・
...Offset voltage, e Op, e Qn... Multiplier both ends output, a... Midpoint. Applicant's representative Patent attorney Takehiko Suzue Figure 3 ζ Figure 4 Figure 5 Prefecture Figure 6

Claims (1)

[Claims] An auxiliary transformer that converts the signal into a signal proportional to the load voltage, an auxiliary current transformer that converts the signal into a signal proportional to the load current, and pulse width modulation that calculates power from the signal from this auxiliary current transformer and the auxiliary transformer. An electronic watt-hour meter comprising a multiplier using a division multiplication method, an integrator that converts the multiplier output into pulses, and a display section that displays the integrator output,
An electronic watt-hour meter, characterized in that an impedance element is connected to both ends of the output of the multiplier, and the divided voltage at the midpoint of the impedance element is input to the input end of the integrator for inversion.