JPH04147668A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce noise and mutual intervention by growing an epitaxial layer on a low-resistivity substrate, by forming a diffused high-concentration layer reaching the substrate from the surface, connecting the diffused layer with a power supply, and by forming a semiconductor device within a region surrounded by these high-concentration semiconductor regions. CONSTITUTION:On a high-concentration P-type semiconductor substrate 1 having a resistivity of not exceeding 0.5OMEGAcm, there are formed a P-type epitaxial layer 2 having a lower impurity concentration than the substrate and then an N-type buried layer 3 and an element-separating P-type buried layer 4. Because boron is used as the impurity of the P-type semiconductor substrate 1, the boundary between the P-type epitaxial layer and the semiconductor substrate becomes indistinct according to a thermal process to be conducted] thereafter. Then, an N-type epitaxial layer 5a is formed, a high concentration N-type diffused layer 6 is formed so as to reach the N--type buried layer 3, and an element- separating high-concentration diffusion layer 7 is formed so as to reach the element-separating P-type diffused layer 4. After that, a conventional process is used also in the title method.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly to a semiconductor integrated circuit device and a method for manufacturing the same that reduce noise transmitted between elements or circuit blocks. Regarding.

[Conventional technology]

Dielectric isolation type IC and P
Although there are N-junction isolation type ICs, PN junction isolation is often used from the viewpoint of cost.

Regarding the manufacturing method and cross-sectional structure of a general PN junction isolated type IC, for example, see pages 73 to 78 of Analysis and Design on Analog Ingredient Lad Circuits by Pearl Earl Gray and Robert Schie Mayer, published by John Wiley and Son. Page (PAUL R, GRAY, ROBERTG, MEYE
R, JOHN VILEY & 5ONS “ANAL”
YSISAND DESIGN OF ANAL
OG INTEGRATED CIRCUITS”p
It is described in p73-78). Figure 10 shows the conventional N
FIG. 2 is a cross-sectional structural diagram of a PN transistor.

In normal cases, the P-type substrate 2b has a high resistance of 100 or more to reduce the capacitance between the collector and the substrate and ensure the withstand voltage between the collector and the substrate.
An N-type epitaxial layer 5a is formed on top, this N-type epitaxial layer is separated by a P-type diffusion layer 7 that reaches the P-type substrate from the silicon surface, and elements are formed in each N-type epitaxial layer. This method is being used. Here, the N-type buried layer 3 is used to reduce the resistance of the collector of the NPN transistor shown in the right figure and to reduce the current gain of the parasitic bipolar transistor existing between the P-type diffusion layer 10 of the base and the P-type substrate 1. It is a provision.

[Problem to be solved by the invention]

The above-mentioned PN junction isolation type IC has the advantage of being a lower-cost isolation method than the dielectric isolation type IC, but when driving an inductance load with the above-mentioned conventional PN junction isolation type IC, when the current supply is cut off, the output transistor is collector(
There is a problem in that the voltage of the N-type region 5a) is lower than the voltage of the ground (P-type substrate 1). For this reason, element isolation P
The N junction is forward biased and the P type diffusion layer 12 for the base and P
- Parasitic PNP that exists between the transistor and the P-type semiconductor substrate
There were problems such as transistors turning on, causing circuits to malfunction, and large currents flowing between the power supply and ground. In addition, even when the parasitic bipolar transistor does not work, if there is a sudden potential fluctuation within the semiconductor integrated circuit device, a diffusion current flows through the PN junction for element isolation, There is a problem in that this causes noise to the analog circuit above, making it impossible to realize a highly accurate AD conversion circuit or DA conversion circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which noise and mutual interference transmitted through a semiconductor substrate are reduced between different elements and between different circuit areas.

[Means to solve the problem]

In order to achieve the above purpose, first the resistance of the semiconductor substrate is reduced to 0.
．． The resistance is lowered to 5 Ωcm or less, and an epitaxial layer for forming a semiconductor element is grown on the epitaxial layer, and a highly concentrated diffusion layer of the same conductivity type as the semiconductor substrate is formed so as to reach the low resistance substrate from the surface. These high concentration semiconductor regions were connected to the ground or a power supply, and semiconductor elements were formed in the region surrounded by these high concentration semiconductor regions.

In addition, in order to reduce the current gain of vertical parasitic bipolar transistors or to reduce the on-resistance of bipolar transistors or vertical double-diffused MOS transistors, an N-type buried layer is provided directly on a highly doped substrate. Since boron is used as an impurity in the P-type substrate and has a diffusion constant larger than that of the impurity (antimony or arsenic) in the N-type buried layer, boron diffuses upward during the subsequent thermal process and becomes an N-type buried layer. A problem may arise in which the mixed layer disappears.

Therefore, a low concentration P type diffusion layer or an N type diffusion layer is formed on the high concentration substrate by epitaxial growth, and then an N type buried layer and a P type buried layer for element isolation are formed. , an epitaxial layer is formed, and a P-type diffusion layer for element isolation is formed from the silicon surface as well.
It was connected to the mold diffusion layer. Further, when an EPROM or a flash EEPROM in which hot electrons are injected into the floating gate is used, the body region is connected to the P-type substrate via the P-type buried layer to prevent potential fluctuations in the body region.

[Effect]

According to the present invention, by surrounding a semiconductor element or a semiconductor circuit that is sensitive to noise from adjacent semiconductor elements or adjacent semiconductor circuits with a low-resistance semiconductor region, bipolar transistors that exist parasitically between adjacent elements or adjacent circuits can be eliminated. Since the current gain can be reduced, mutual interference between them can be reduced. Also, by connecting this low resistance area to ground or power supply,
It becomes possible to eliminate noise transmission between adjacent elements or between adjacent circuits. Moreover, by surrounding a semiconductor element or a semiconductor circuit that causes noise generation with the low-resistance semiconductor region, it is possible to reduce the adverse influence on adjacent elements or circuits. Furthermore, the low resistance semiconductor region is
This makes it possible to surround the semiconductor element or semiconductor circuit with a low-resistance N-type buried layer inside the mold and a high-concentration N-type semiconductor region formed to reach this layer. In addition, it becomes possible to enhance the effect of reducing noise between adjacent circuits. Another advantage is that a bipolar transistor or the like using a heavily doped N-type buried layer can be formed inside a low-resistance P-type semiconductor region provided to reduce mutual interference.

Further, even when an EPROM or a flash EEPROM in which hot electrons are injected into the floating gate coexists in the semiconductor circuit device of the present invention, the body region is connected to the P-type via the P-type buried layer to prevent potential fluctuations in the body region.
Since it can be connected to the mold substrate, latch-up due to potential fluctuations in the body region of the nonvolatile memory element can be prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of the structure of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 shows a manufacturing method thereof.

First, a P-type epitaxial layer 2 with a lower concentration is formed on a highly doped P-type semiconductor substrate 1 with a resistivity of 0.5 Ωcm or less, and then an N-type buried layer 3 and a P-type buried layer 3 for element isolation are formed. Including layer 4
form. Since boron is used as the impurity in the P-type semiconductor substrate 1, the boundary with the P-type epitaxial layer becomes unclear due to the subsequent thermal process. For this reason, it is indicated by a broken line in the drawing (FIG. 2(a)). Next, an N-type epitaxial layer 5a is formed, a high concentration N-type diffusion layer 6 is formed so as to reach the N-type buried layer 3, and a high concentration N-type diffusion layer 6 is formed so as to reach the element isolation P-type diffusion layer 4. A high concentration diffusion layer 7 for separation is formed (FIG. 2(b)). Thereafter, the semiconductor integrated circuit device shown in FIG. 1 is obtained by using conventional processes.

If an N-type buried layer using antimony or arsenic is formed directly on a high-concentration substrate, there is a possibility that the N-type buried layer will disappear due to the rise of the high-concentration P-type substrate during the subsequent thermal process. However, according to this embodiment, since the P type epitaxial layer 2 is formed between the highly doped P type substrate and the heavily doped N type buried layer, it is possible to avoid the above-mentioned problems. Further, by providing the P-type buried layer 4 for element isolation, it is possible to increase the concentration of the element isolation region of the lightly doped P-type epitaxial layer 2 and reduce the current gain of the parasitic bipolar transistor in the lateral direction. Furthermore, by forming the element isolation region with the P semi-diffused layers 4 and 7, it is possible to reduce the number of thermal processes compared to the case where only the P-type diffused layer 7 is used. Therefore, it is possible to reduce upward diffusion of boron used in the high concentration P-type substrate 1.

In the embodiment shown in FIG. 1, an output element and a horizontal double-diffusion type N-channel MO8 transistor for high breakdown voltage are shown on the right side. Here, the N-type buried layer 3 and the high concentration N-type diffusion layer 6 are connected to the P-type diffusion layer 12 for the body of the N-channel MoS transistor and the P-type substrate 1°2 or the P-type diffusion layer 4 for element isolation.
This is provided to reduce the current gain of the parasitic bipolar transistor that exists between 7 and 7. In addition, there is a high concentration of N in the center of the figure.
The region surrounded by the type semiconductor layers 3 and 6 is a region in which a high-precision analog circuit that is sensitive to external noise is formed, and is, for example, a region in which an AD converter, a DA converter, or a part of the circuit is formed. In other words, by fixing this highly doped N-type diffusion layer to the power supply, even if noise cannot be removed with a low-resistance P-type substrate, the structure is such that noise is difficult to enter inside the highly doped N-type layer. There is. Note that it is also possible to prevent noise from being released to the outside by inserting a digital circuit section that operates at a high frequency and becomes a source of noise in such a high concentration N-type diffusion layer. In addition, by adjusting the concentration and thickness of the P-type epitaxial layer 2, the diode existing between the N-type buried layer and the P-type diffusion layer of the substrate can be converted into a double-diffusion type MOS)-transistor as shown in the figure. source,
It is also possible to actively use it as a Zener diode for protection between drains. On the left side of Figure 1 is an EPRO that injects hot electrons into the floating gate 11.
This shows a non-volatile memory element such as M or flash EPROM. In this case, a substrate current flows during writing into the P-type diffusion layer 10, which is the body of the nonvolatile memory element, and the substrate potential tends to fluctuate. Therefore, the body needs to be connected to the P-type substrate 1 to prevent latch-up. For this reason, in this embodiment, the P-type substrate 1 and the P-type diffusion layer 10 are connected via the P-type buried layer 4. Note that in this embodiment, the high concentration N-type buried layer 3
Although the epitaxial layer formed between the P-type substrate 1 and the P-type substrate 1 is a low-concentration P-type epitaxial layer 2, an N-type epitaxial layer with the same or low concentration as the N-type buried layer 3 may be used instead. There is an effect.

FIG. 3 is a structural sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. In this embodiment, a P-type epitaxial layer 5b is used in place of the N-type epitaxial layer 5a, but since the same structure as in the previous embodiment can be realized, the same effect can be obtained. However, in this embodiment, as the structure of the double-diffused N-channel MOS transistor on the right side of the figure, it is possible to realize a structure using the N-type diffusion layer 9 and a structure not using the N-type diffusion layer 9 as shown in the figure. In the case of a structure using an N-type diffusion layer 9, a P-type epitaxial layer 5 is formed on the heavily doped N-type buried layer 3.
A region b is created, and this region may be floating, connected to the drain, or connected to the source.

In this embodiment as well, the 4 lightly doped P-type epitaxial layers 2 formed between the highly doped N-type buried layer 3 and the P-type substrate 1 are replaced with N-type epitaxial layers having a concentration similar to or as low as that of the N-type buried layer 3. A similar effect can be obtained using layers.

FIG. 4 is a structural sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. The structure of an N-channel MOS transistor and a P-channel MO8) transistor, which can be used as the lower arm element and upper arm element of a bridge circuit capable of driving an inductance load, was realized using the same manufacturing method as in the second embodiment of the present invention. An example of a cross-sectional structure is shown.

N-channel MO when driving an inductance load
The drain of the S transistor (cloth in the figure) is lower than the substrate voltage, and electrons are injected from the train into the P-type head region 5b, but because it is surrounded by the high concentration P-type diffusion layers 4 and 7, there is no interaction with adjacent elements. It is possible to suppress interference. In addition, in the P-channel MOS transistor (left in the figure), the drain rises above the power supply, and holes are injected from the drain into the N-type diffusion layer 9, but since it is surrounded by the high concentration N-type diffusion layers 3 and 6, the adjacent element It is possible to suppress mutual interference with

FIG. 5 is a structural sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. In this example, by using phosphorus, which has a larger diffusion constant than boron, which is an impurity for the P-type substrate, as the impurity for the high-concentration N-type buried layer, even if the high-concentration P
An example will be shown in which the n-type buried layer 3b is prevented from disappearing even if the type substrate 1 is used. In the case of this embodiment, compared to the first and second embodiments, it is difficult to obtain a low-resistance N-type buried layer, but there is an advantage that the epitaxial layer can be formed only once.

FIG. 6 is a structural sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In the fourth embodiment, an N-type epitaxial layer was used, but in this embodiment, a P-type epitaxial layer 5b is used. In this embodiment, in order to reduce the resistance of the body region of the nonvolatile memory element, the element isolation P-type diffusion layer 7 is always connected to the P-type diffusion layer 9 to prevent potential fluctuations in the body region of the nonvolatile memory element. is necessary. Also, as in the first or second embodiment, P
A mold embedding layer 4 may be added to connect the body of the nonvolatile memory and the substrate.

FIG. 7 is a structural sectional view of a semiconductor integrated circuit according to a fourth embodiment of the present invention. N-channel MOS transistor and P-channel MOS transistor that can be used as the lower arm element and upper arm element of a bridge circuit that can drive an inductance load
An example of a cross-sectional structure when the structure of an OS transistor is realized by the manufacturing method of the fifth embodiment of the present invention is shown. When driving an inductance load, the drain of the N-channel MOS transistor (left in the figure) drops below the substrate voltage, and electrons are injected from the drain to the P-type head region 5b. Since it is surrounded by the type diffusion layer 7, it is possible to suppress mutual interference with adjacent elements.

In addition, in the P-channel MOS transistor (left in the figure), the drain rises above the power supply and holes flow from the drain to the N-type diffusion layer 9.
However, since it is surrounded by the heavily doped N-type diffusion layers 3b and 6, it is possible to suppress mutual interference with adjacent elements.

FIG. 8 is a structural sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention. The embodiments so far have shown cases where a highly doped N-type buried layer is required, that is, cases in which the current gain of a vertical parasitic bipolar transistor is reduced or bipolar transistors coexist. On the other hand, FIG. 8 shows an embodiment of the present invention in which a high concentration N-type buried layer is not required. That is, in the area surrounded by the low-resistance P-type substrate 1 with a resistivity of 0.5 Ω or less and the high-concentration P-type diffusion layer 6 that reaches this substrate, there is a Precision analog circuits, or form part of such circuits. Therefore, it is possible to block noise from outside the area surrounded by the highly concentrated P-type head area.

Conversely, it is also possible to prevent noise from being emitted to the outside by inserting a digital circuit section that operates at a high frequency and becomes a source of noise within the area encompassed by such a high concentration P-type head area. It is possible.

FIG. 9 is a structural sectional view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. In the seventh embodiment, an N-type epitaxial layer 5b was used, but in this embodiment, a P-type epitaxial layer is used. In the case of this embodiment as well, by forming a high-precision analog circuit such as an AD converter or a DA converter, or a part of the circuit, in a region surrounded by the high-concentration P-type diffusion layer 6, which is sensitive to noise from the outside. , it is possible to block noise from outside the area surrounded by the highly concentrated P-type head area. Conversely, it is also possible to prevent noise from being emitted to the outside by inserting a digital circuit section that operates at a high frequency and becomes a source of noise within the area encompassed by such a high concentration P-type head area. It is possible.

〔Effect of the invention〕

According to the present invention, it is possible to reduce mutual interference between adjacent elements or circuits by surrounding a semiconductor element or semiconductor circuit that does not like noise from adjacent semiconductor elements or adjacent semiconductor circuits with a low-resistance semiconductor region. There is an effect that Furthermore, by surrounding the semiconductor element or semiconductor circuit that causes noise generation with the low-resistance semiconductor region, there is an effect that the adverse effect on adjacent elements or circuits can be reduced. Furthermore, the low-resistance semiconductor region is formed of P type, and the semiconductor element or semiconductor circuit is surrounded by an N-type buried layer of low resistance and a high concentration N-type semiconductor region formed to reach this layer. This has the effect that it becomes possible to enhance the noise reduction effect between adjacent elements and between adjacent circuits as described above. Further, at this time, there is an effect that a bipolar transistor or the like using a heavily doped N-type buried layer can be formed inside the low-resistance P-type semiconductor region provided to reduce mutual interference.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a structural cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. is a cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 4 is a cross-sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.
5 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, FIG. 6 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention, and FIG. 7 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. 8 is a cross-sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIG. 9 is a cross-sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention. 10 is a sectional view of a conventional semiconductor integrated circuit device. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... P-type semiconductor layer or N-type semiconductor layer, 2b... P-type semiconductor layer, 3, 3b...
・N-type buried layer, 4 ・-P-type buried layer, 5a, 6, 9, 1
5...N-type semiconductor region, 5b, 7, 10, 12.14
... P-type semiconductor region, 8... Insulating layer, 11.13.
...Gate electrode layer, 16... Electrode layer. Figure 1 Figure 2 (a) Figure 2 (b) WJ3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 b

Claims (1)

[Scope of Claims] 1. A first semiconductor region comprising an N-type semiconductor region or a P-type semiconductor region having a higher resistivity than the first semiconductor region on a highly doped semiconductor substrate (first semiconductor region) with a resistivity of 0.5 Ωcm or less. Further, a high concentration P type diffusion region (third semiconductor region) formed so as to reach the first semiconductor region from the surface is provided, and the third semiconductor region is separated by the first semiconductor region and the third semiconductor region. 2. A semiconductor integrated circuit device and its manufacturing method, characterized in that a semiconductor element is formed in a semiconductor region. 2. A high concentration N-type buried layer (fourth layer) is formed under the second semiconductor region.
2. The semiconductor integrated circuit device and method for manufacturing the same according to claim 1, further comprising: a semiconductor region). 3. A semiconductor element is formed in the second semiconductor region separated by the fourth semiconductor layer and a high concentration N-type diffusion layer (fifth semiconductor region) provided so as to reach the fourth semiconductor layer from the surface. A semiconductor integrated circuit device and its manufacturing method according to claim 1 or 2, characterized in that: 4. The semiconductor integrated circuit device and method of manufacturing the same according to claim 2, wherein phosphorus is used as an impurity in the fourth semiconductor region. 5. The first semiconductor region has a high concentration of P of 0.5 Ωcm or less
Claim 1, characterized in that the semiconductor substrate comprises a P-type semiconductor substrate (sixth semiconductor region) and a P-type semiconductor layer (seventh semiconductor region) or an N-type semiconductor layer (eighth semiconductor region) having a higher resistivity than the sixth semiconductor region. The semiconductor integrated device and its manufacturing method according to items 2 to 4. 6. A high concentration P type diffusion layer (ninth semiconductor region) formed by the third semiconductor region from the surface of the seventh semiconductor region and a high concentration P type diffusion layer (tenth semiconductor region) formed by diffusion from the semiconductor surface 6. The semiconductor integrated device and method for manufacturing the same according to claim 1, wherein the semiconductor integrated device comprises: 7. The semiconductor integrated circuit device according to claim 2, wherein the fourth semiconductor region is formed by diffusion from the surface of the seventh semiconductor region (or the eighth semiconductor region). Production method. 8. Claim 8, characterized in that a P-type diffusion layer (eleventh semiconductor region) serving as a body region of an N-type nonvolatile memory element is formed so as to reach the first semiconductor region or the ninth semiconductor region. A semiconductor integrated circuit device and its manufacturing method according to items 1 to 7. 9. The semiconductor integrated device according to any one of claims 1 to 7, characterized in that a P-type diffusion layer (eleventh semiconductor region) serving as a body region of an N-type nonvolatile element is connected to the third semiconductor region. Circuit devices and their manufacturing methods. 10. The semiconductor according to claim 1, wherein only an analog circuit block is formed in the second semiconductor layer that is divided or separated by the first semiconductor layer and the second semiconductor layer. Integrated circuit devices and their manufacturing methods. 11. The semiconductor integrated circuit device and method of manufacturing the same according to claim 9, wherein the analog circuit block is surrounded by the fourth semiconductor region and the fifth semiconductor layer.