JPH04147334A - Multiplier and multiplier testing method - Google Patents

Abstract

PURPOSE:To obtain a testing method for achieving a high failure detecting ratio and a multiplier consisting of a partial product add circuit by Booth's recoding method easy to test by generating plural input combinations of continouous odd digits of multiplier and adding a particular numeric value to the upper and lower digits to prepare the multiplier. CONSTITUTION:Partial products 110-112 are generated by means of Booth's recoding method. Partial product circuit 120-125 constitute the add step at the first stage of an add tree. Partial product circuits 130-132 constitute the add step at the second stage. Partial product add circuits 140 and 141 constitute the add step at the third stage. Partial product add circuit 150 constitutes the final stage of the add tree. Adder 160 carries out binary number conversion and the final transmission of carry. Partial product add circuits 120-132 are tested using paths 170-175. Specifying a multiplier for testing each add step is by means of Booth's recoding method. Further, by selecting a multiplier, a predetermined partial product add circuit and a shift amount of partial prod uct are tested.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test I~ method for achieving a high fault coverage rate in a one-way adder multiplier, and a multiplier configuration that is easy to test. It is.

[Conventional technology]

As a conventional method for increasing the speed of multipliers, the Booth glue coating method is known, for example, as shown in Nikkei Electronics, May 29, 1978, pages 76 to 90. In the 2-bit Booth glue coat method, the multiplicand is
X7-+ 2"-'+X,,-22'-" ++x
, 2' +Xo (n is a positive integer), the multiplier is Y--y
n,,+2″-1+yn-22″-2+--+y1
20y. shall be. Then, the multiplier Y and the product P=X・Y can be transformed into the following form.

P-χ ・Y Therefore, the product P follows the consecutive three-digit value of the multiplier, and the partial product ±
It is obtained by adding 2X, ±x, 0 with a weight of 22". Now, in addition of partial products, +X
can be realized by ordinary addition, + 2 In addition, when i=0, it is calculated as y-I-0. Furthermore, in the case of multiplication of floating point numbers that have a normalized mantissa, the most significant digit of the mantissa is not a sign but 1, so it is calculated as yn-1-0. By using this recoding method, the number of partial products can be reduced, so the speed of the multiplier can be increased.

Further, regarding an addition tri-type multiplier that performs high-speed multiplication by parallel addition of partial products, for example, see Journal of the Institute of Electronics and Communication Engineers Vol. J66-D, No. 6 (1983)
It is discussed in pages 683 to 690 and pages 1 to 6 of IEICE Technical Research Report ED88-48. These systems use signed digit numbers of radix 2 (hereinafter referred to as redundant binary numbers) as internal arithmetic numbers,
Partial products can be added two by two without carry propagation. The example shown in FIG. 7 shows the additions 1 to 1 of the partial product adding circuit for calculating the products after generating non-negative partial products and non-pressure partial products by the 2-bit Booth recoding method. 601, 602, 603, 604
605, 606, and 607 are partial products, which are generated by adding a non-pressure partial product and a non-negative partial product, respectively.

612.614 and 616 are partial products 601 and 602.601, respectively.
Partial product addition circuit consisting of a redundant binary adder for adding 603 and 604. 605 and 606, 620 and 640
are the outputs of the partial product adder circuit 612, 614, and 6, respectively.
Partial product addition circuit 660 adds the output of Partial product addition circuit 620 and partial product 607.
670 is a conversion circuit for converting the product expressed in redundant binary numbers into a binary number. Note that in each addition stage, the part where only one digit of the lower number exists does not need to be added to the other number, so it is either output as is to the binary conversion circuit as a sum (for example, the lower part of the partial product 601 609), it is added as the next partial product in the next and subsequent addition stages (for example, the partial product addition circuit 61
6 619).

[Problem B to be Solved by the Invention] The addition tri-one type multiplier consists of a multi-input adder configured with a combinational circuit. Therefore, the logic depth from the input terminal to the output terminal of the multiplier becomes deep, so during testing (a
) It becomes difficult to set nodes using test vectors in circuits close to the output side (decreased controllability); (b) failure information in circuits close to the input side is difficult to be transmitted to the output terminal (decreased observability); Two problems arise. Therefore, as the bit width of the multiplier is expanded and the circuit scale becomes larger, it becomes difficult to improve the fault coverage.

This may lead to failures being overlooked during shipping inspections, leading to the serious problem of defects occurring in the market.

One of the test methods that achieves a high fault coverage rate is a random test method that uses all combinations of input signals as test inputs. This method may use random numbers automatically generated by an embedded circuit. For example, in an n-bit linear foot bank shift register, 2"-1 random numbers can be generated. However, in this method, all random numbers can be used to multiply When testing a large-scale circuit, it becomes an unrealistic test method because the test time is long.

For example, in the case of a 20MHz 24-hint multiplier, if 1j random numbers are added to the multiplicand multiplier, the time required for testing is 50n.
secX (2” 1) X (2241) −1
Since it takes 4X 106 seconds, only a part of the random numbers must be used. In this case, as mentioned above, the fault coverage of the test input becomes a problem, and a large number of man-hours are required to improve the fault coverage. Furthermore, when input values are given as test vectors instead of automatic generation, a large amount of disk space is required for the LSI test, and time is required to transfer the test vectors and write them to the buffer memory, resulting in an increase in test costs.

The present invention was made in view of these conventional problems, and by utilizing the properties of the Booth recoding method, it is possible to improve the efficiency of test vector generation and achieve a high fault coverage rate with a small number of test vectors. The technical challenge is to provide a test method for By converting the above test method into hardware and incorporating it into a built-in self-test (b
Our technical objective is to provide a multiplier with high fault coverage that realizes ult-4ns self-test).

[Means to solve the problem]

The invention of claim 1 of the present application is an n-digit long multiplier (Y=yn-+
yLl-□"'-'-'V+ Vo; the most significant digit is y, l-1, n≧2, n is an integer). Generate a partial product from the multiplicand using Booth's recoding method from three consecutive digits, This is a multiplier whose partial product addition circuit is configured with an addition tree that adds multiple partial products and also adds multiple partial products, and the result obtained by adding multiple partial products one by one.
+n+Zk-+ y n+2k-z--- Y m.

+Vn)'h,,I (k≧2; is an integer; m-
n 1+ n 21; if m>n-1)'
m+2k-1= Y n+2k-2-13' n-+
A first step of generating multiple input combinations of = Y t* −〇 ) and the most significant digit y+n+ of 2k+1 digits.
The second step is to set the same value as zk-+ to each digit from yn-+ to Vp-□2 in the multiplier, and y, - in the multiplier.
The same value as 1 from Vn-z to y. The test is performed using the multiplier generated by the third step of setting each digit up to the third step.

Further, the invention of claim 2 of the present application is a multiplier of n digit length (Y=3'n-
1yn-z ”-””Y + Vo ;The most significant digit is y
. -1, n≧2, n is an integer) to generate partial products using the Booth recoding method from consecutive 3 digits, and add the partial products one by one. A multiplier configured as a partial product addition circuit,
additional digit setting means for setting a plurality of additional digits at the upper and lower positions of the multiplier, and generating a partial product located at the lowest position by the multiplier and the additional digits when the test signal is valid, and when the test signal is invalid. A first partial product generating circuit generates a partial product located at the lowest position by setting the value of the additional digit to O, and when the test signal is valid, a partial product located at the highest position is generated by a multiplier and an additional digit. and a second partial product generation circuit that generates a partial product positioned at the highest position by setting the value of the additional digit to 0 when the test signal is invalid.

(Operation) According to the present invention having such characteristics, in a multiplier using the Booth recoding method, partial products ±2X, ±X, and 0 are generated by a combination of three-digit values in the multiplier. 2k+1 after deducting the overlap of 1 digit for each
By setting the digit multiplier, it is possible to limit the partial product addition circuit to be tested and to set the partial products to be added. Also, by setting the multiplier, it is possible to set all other than the partial products to be 0 to 0. This setting is for any consecutive 2n+1 in the multiplier.
Digit 3'11+2k-1ym+Zk-2"'-""5'
Generate multiple input combinations of m+I yII)' +n-1, and set the same digit as -1 in the most significant digit y, 4□ from yn-+ to V +n+2k in the multiplier, and yl-2 From y. This can be achieved by setting up to the same value as y, -1. Using this property, it is possible to test only a certain adder stage in the adder tree, making it easier to set manual values for circuits near the output side and to propagate fault information for circuits near the input side, making it easier to generate test hectors. It becomes possible to improve efficiency and achieve high fault coverage. Also, since this method is easy to implement in hardware, it is possible to implement a built-in self-test (bult-in 5elf-
test) can be realized.

[Example] (Example 1) FIG. 1 is a diagram showing an example of a multiplier test method according to the first invention. In this embodiment, the multiplier performs multiplication of floating point numbers having a 24-bit mantissa part.
The case of a mantissa multiplier in which a partial product addition tree is constructed by adding partial products represented by a number of signed digits (redundant binary numbers) in a bipartite manner is shown. 100, 102, 10
4.106 108 110.112 is an even-numbered partial product generated by the Booth paste method, each digit of which is expressed as a non-negative redundant binary number, 101, 103, 105107 1
09.111 is an odd-numbered partial product generated by the Booth glue coat method and each digit is represented by a non-compression redundant binary number.

Also 120, 121, 122.1.23, 124.125
130131.132 is a partial product addition circuit that constitutes the first addition stage of the addition tree; 140.141 is a partial product addition circuit that constitutes the second addition stage of the addition tree. Partial product addition circuit constituting addition stage, 15
0 is a partial product addition circuit constituting the final addition stage of the addition tree, and 160 is an adder that performs binary conversion and final carry propagation. 170,171.172,173,174
．． 175 are partial product addition circuits 120, 121, 130, respectively.
, 140.150 132 is an example of a path for testing.

A method of specifying a multiplier for testing each addition stage will be explained using FIG. 2 and FIG. 3. In Booth's recoding method, one partial product is determined from three consecutive digits of the multiplier,
One digit of these is also used to generate adjacent partial products.

Then, two partial products are determined by the successive 5 digits, and from these, the recoded value, that is, ±2. A value of ±1 or 0 is determined. Figure 2 is an example of a 5-digit value glue coat.
The result of adding partial products is shown. yo. +V-Y-
The setting of 3'11-:l7m+2V-1 determines the recode value that determines the lower partial product, and the setting of 3'11-:l7m+2V-1 determines the recode value that determines the upper partial product.

In this way, the shift amount of the partial product can be arbitrarily set by recoding the multiplier. FIG. 3 shows the setting of partial products by recoding. In the example in Figure 1, yz;-+y
2+>'z;−+ (i =0. 1.−−−−− n
/2) is recoded using three digits, and the partial products are added with a weight of 22°. At this time, y3 y2 yl
y.

bus 170, y7 y6 y5 Y< yl bus 1
71 can be specified. Similarly, pass 172.
173 and 174 can also be set using a 5-digit multiplier code.

Furthermore, since the partial product addition circuit is a parallel adder, it is only necessary to supply a test signal for testing the adder. This is possible by setting the multiplicand and the shift amount by recoding.

For example, out of the multiplier Y, set V7y6 ys V4y3 to 01
, O], the value of each other digit of the 011th power is 0, and the multiplicand is 11. −−−−] is given. χ
If the negative number of 8 is represented by i (-1 if x+-=t, 1 if -1), and the complement of x is represented by Xi (1 if x+-1 is Olo), then the lower part of the partial product addition circuit 121 11-----1 as human power on the side, F T as input on the upper side
-----t is input. Therefore, partial product circuit 121
The output of will be fixed.

Also, if 0101------1 is given as the multiplicand X,
0101-01 is input as a lower input, and 0101--01 is input as an upper input to the partial product addition circuit 121. As a result, the first stage partial product addition circuit 120~
125 can be tested. In the example shown in Figure 1,
The first partial products generated are arranged in the order of non-negative partial products and non-positive partial products alternately from the lowest order, so when setting a 5-digit multiplier, the addition of non-positive partial products, Combinations of additions of non-negative partial products do not occur. This combination test can be set using a 7-digit multiplier. For example, the bus 175 for adding the non-positive partial product 109 and the non-positive partial product 111 in the partial product addition circuit 132 is connected to the bus 175 from y2:l to yl7.
Can be set in digits. As described above, any partial product addition circuit and partial product shift amount to be tested can be set arbitrarily based on the value of the multiplier, so all combinations of partial product addition can be tested.

Because the logic depth is deep, there is a problem that failure information is not propagated to the output terminal.This problem can be solved by setting all partial products other than those used for testing to 0, and only propagating the output of a specific partial product addition circuit to the output terminal. In other words, by setting the multiplier values other than those set as test input to all 0 or 1 according to the highest and lowest digits of the record digits,
It is possible to set O to all parts other than the partial products used for [Test].

For example, in the test bus 175 example above, V 21 V
20y1. all 1 according to the value of yl or Vz+
Alternatively, by setting it to 0, the value of the partial product 110 can be set to O. This setting is based on the premise that the addition of the partial product and O is correct in each partial product addition circuit, but this can be confirmed by a test in which the multiplication result is 0 when the multiplicand or multiplier is set to 0. Furthermore, since the addition of the partial product and 0 is also tested in the test of each separate stage, if the addition with O is incorrect, it can be detected by the test of that addition stage.

Note that when adding partial products with a large difference in digit weight, the test efficiency decreases because the digit shift between the upper and lower digits becomes large.

For example, partial product addition circuit 1 with partial product 111 and partial product 100
It is possible to test 50, but since there is a weight difference of 222, most of the inputs to the partial product adder are one number or the other. The addition with the smallest digit shift is the addition of adjacent partial products, and considering the addition of non-positive partial products or the addition of non-negative partial products, two adjacent partial products can be used as test input. It is valid up to the addition of .

(Embodiment 2) Next, a multiplier that achieves a high fault coverage according to the second invention will be described. This multiplier implements a built-in self-test l-(
This makes it possible to achieve bult-in (5elf-1est) and high fault coverage.

FIG. 4 is a block diagram of an embodiment of a multiplier to which the present invention is applied. This embodiment is a multiplier that multiplies floating point numbers having a 24-bit mantissa part like the first embodiment, and has the I/RI configuration shown in FIG. It has the configuration of a partial product addition circuit shown in FIG. Also the third
The glue coating method shall be used. 400 is a multiplicand generation circuit that generates a test input as a multiplicand, and can be realized by, for example, a random number generator using a linear feedback shift register, a ROM that is a constant generation means storing constants as a test input, or the like. When using a linear feedback shift register, if the number of multiplicand inputs is too large, it is possible to freeze the number of inputs by stopping the clock supply to the register at a certain predetermined number, or by using multiple registers with a small number of bits. can. 401 is a selector that selects the multiplicand 411 used in normal calculations and the output of the multiplicand generation circuit 400; 412 is a test signal TST that is manually input during testing to set the test operation of the multiplier; 402 is a multiplier and an addition serving as test inputs. Digit yzs, yl4.3'-
403 is a selector that selects the output of multiplier 413 and multiplier generation circuit 402 used for normal calculations, 404 and 405 are manual latches that latch the multiplicand and multiplier, respectively, and 406 is a valid test signal TST412. In this case, 3 digits V+ of multiplier y1yo and i1 adder y−+
The lowest partial product 4 according to the recoded value of yo 3'-+
14, 407 is y23
a second partial product generation circuit 40 that generates partial products other than the lowest and highest partial products 4]5 according to the recoded value of y-1 from
8 is an additional digit yz when the test signal TST412 is valid.
3 digits of s・yl4 and multiplier y23'/25V 24
The top partial product 416 according to the recoded value of V z3
409 is a partial product addition circuit that adds the partial products to generate product 417; 410 is the product 4;
17 for each operation,
For example, as shown in "Fault Diagnosis of Logic Circuits" by Hideo Tamaki, published by Nikkan Kogyo Shimbun, 1983, pp. 138-139, a linear feed huck shift register is used. 418 is the output of the data compressor 410 and is the final test result.

The first partial product generation circuit 406 generates yl by setting the multiplier.
When y2. is 1, the lowest partial product is O. When is 1, the partial product located at the highest position is set to O. In a normal partial product generation circuit, the lowest partial product is −'
Since the binary partial product is determined by the value of y23, the value of the partial product becomes O only when each digit is O. Therefore, when yl and y23 are 1, the lowest partial product and the highest partial product will not become O, and these partial products will also be mixed into the test manual in addition to the partial product set by the multiplier, resulting in failure. Information may not be transmitted properly to external terminals. To prevent deterioration in observability due to this contamination, additional digits are used to determine the recode value during testing. By using this, even when yl is 1, the lowest partial product can be made O by setting all of )'+VoV to 1, as shown in FIG. Also y23 is 1
Also in the case of 3' 25 V 24 as shown in Fig.
By setting all of 3' zi to 1, the most significant partial product can be set to 0. If the test signal is invalid, the values of the additional digits y25, yl4, and y-1 are set to 0, and the paste coating is performed as usual. In addition, y・i, z3' zi−+
When recoding is performed using the three digits of V zi (1-01・-n/2) and the partial products are added with a weight of 22/1, the position of the additional digit changes and becomes 3'24, y-+, )' −z.

If the most significant digit is a code digit, additional digits are added only to the lower part of the multiplier.

The built-in self-test method of this multiplier will be explained. First, the multiplier generation circuit 402k sets a certain multiplier. Next, input the multiplicand and perform multiplication. This product 417 is input to a data compressor 410 for each calculation and data compression is performed. When all test inputs from the multiplicand generation circuit 400 are completed, the setting of the multiplier is changed. Enter the multiplicand again for this multiplier. The compression result 418 may be output and referenced even when all tests are completed or every time the multiplier is set.

The failure detection rate of the data compressor 410 is at most 2-'' for a given test input in the case of an m-bit linear feedback shift register, and can be ignored.

FIG. 5 is a diagram showing an example of the configuration of a multiplier generation circuit 402 that generates a multiplier to be a test input. In this example, the multiplier generation circuit 402 is configured with a 27-digit wide (24-digit multiplier, 3-digit additional digit) incrementer using a sequential carry-addition method. 500 is a cell for one bit of an incrementer, and is constructed by cascading 27 bits of flip-flops with set terminals.

501 is a first test register that stores data for incrementing the incrementer, and 502 is a second test register that stores data that masks the output of the incrementer, each having a data length of 27 bits. 503
is a multiplier that becomes the test input of the multiplier and is given to the selector 403. Now, the pattern generator 504 is connected to the test registers 501 and 502k. The pattern generator 504 generates any consecutive digits 2k+1 digits y, 4°, -1y1- in the multiplier, as described in detail below.
first means 5 for generating combinations of a plurality of inputs in a range of 8;
05 and the most significant digit y of 2k+1 digits. . The upper digits y7-1 to y in the multiplier have the same value as 2k. A second means 506 for setting up to 2k, and all digits up to yl-2yo are O.
or a third means 507 for setting the value to 1. Then, when setting 1 to a certain digit, set 1 to the corresponding focus of the first test register 501, and set 1 to the corresponding focus of the second test register 502.
All you have to do is write O to the corresponding bit. When setting O to a certain digit, 1 is written to the corresponding bit of the first test register 501 and 1 is written to the corresponding bit of the second negative 1-register 502. Because of the sequential carry method, by setting the first test register 501 and manually setting the CE/NO signal to set the value of each digit to 1 and setting the initial carry to 1, the lowest value of the incrementer's operating range can be reached. A carry signal is always input to the digit.

This setting allows incrementing only a certain range of digits, and setting other digits to 1 or O.

Next, the operation of the pattern generator 504 described above will be explained in detail. In the first means 505, the first. The second test registers 501 and 502 are set as shown in FIG. V n 42 k-2'-""-'"/+n The reason for setting O in the digit of the test register 501.
+1・2t1 and yffi-1 are set to 1 or 0 and y,
. This is to make it possible to set a plurality of values by incrementing the 2k+1-digit value consisting of 2k-+ "-"" V m-1. Also, the values of Vp-+ - to --yo of the first test register 501 Set 1 to the corresponding digit. Then, y□−+ '−””−' of the multiplier generation circuit 402
)'o is written in the flip-flop of the corresponding digit. Since this is configured like a cell 500 in which each digit is 1 bit, by setting the value of the flip-flop to 1 and the initial carry to 1, a carry is always generated to the first digit of the multiplier generation circuit. This is to enable incrementing. Then, by activating the test signal TST, a clock is supplied to each pinto cell 500 via the AND circuit 508, and ymt2k-2-~
---y, and the increment operation is performed in the range of V 114 according to the set values of ym+zb-1 and ym-+.
2k+1 consisting of th-+""-'-" V n-+
The digit values are set to various values.

The operation output value y of the second means 506. 2. A value of -1 takes 0 or 1. Therefore, the first. By setting the second test registers 501 and 502 as shown in FIG.
2k-1 are all 1 or 0. ! ,,−+ ”−'
-"' V -12° is all 0, it is necessary to set 1 in the corresponding digit of the second test register 502.

Then, if the digit of the second test register is 1, its output will be set to 0. In this case, the corresponding digit of the first test register 501 may have any value. Also, y.

If ym+2k-1 is all 1, 1 is set in the corresponding digit of the first test register 501 and O is set in the corresponding digit of the second test register 502. Due to the configuration of the cells 500 of each digit, the output of the first test register 501 is connected to the set terminal of each cell, so 1 is set in each cell.

The value of the operation yn-+ of the third means 507 is 1 or O. Therefore, the first. Set the second test registers 501 and 502 as shown in FIG.
V II-+ ""-"' yo are all 1 or O. If y, -1----yo are all 0, 1 in the corresponding digit of the first test register 501, second test) - Set 0 to the corresponding digit of the register 502. If the digit of the second test register is 1, the cell of each digit is reset to O. Here, set 1 to the corresponding digit of the first test register 501. The reason for this is to always generate a carry to the m-th digit of the multiplier generation circuit 402 to enable increment.

V--l"-'-"3' When all o are 1, 1 is set in the corresponding digit of the first test register 501, and O is set in the corresponding digit of the second test register 502. Since the output of the first test register 501 is connected to the set terminal of the flip-flop of each cell, when the value is 1, the contents of the flip-flop are set.

Using the thus set multiplier generation circuit 402, a test multiplier is set using the upper and lower two digits.

In the present invention, an example of an addition tree using a signed digit number as an internal operation number has been shown, but a similar test can also be performed with a carry-save addition tree composed of three-manufactured, two-output full adders.

〔Effect of the invention〕

According to the first invention, the partial product addition circuit to be tested can be selected based on the recoded value of the multiplier, and the test input can be set. (1) The controllability and observability of the circuit are improved. , (2) The test hector generation efficiency is improved and the test man-hours are reduced. (3) A high fault coverage rate can be achieved. (4) The number of test patterns can be reduced, so the test time can be shortened. 5) It has the effect of reducing the disk capacity and memory capacity of the LSI tester used to store test patterns, and is extremely effective in practice.

According to the second invention, since the multiplier generation circuit is made into hardware and compact testing can be performed using the compression circuit, (1) built-in self-testing is possible, making it easy to test the multiplier; (2) It has the following effects: it is possible to achieve a high fault detection rate, (3) it is possible to shorten test time, and (4) it is possible to reduce the disk and memory capacity of the LSI tester used to store test patterns.
'Practical' - extremely effective.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the multiplier test method of the present invention, Fig. 2 is a diagram showing the addition result of two partial products obtained by recoding, and Fig. 3 is a diagram showing the relationship between recoding and the partial product addition circuit to be tested. Figure 4 is a configuration diagram of a multiplier according to the second invention, Figure 5 is a configuration diagram of a multiplier generation circuit, and Figure 6 is a diagram showing the setting contents of the pattern generator of the multiplier generation circuit. Figure 7 shows addition 1 of a multiplier that uses redundant binary numbers as internal calculation numbers.
~ Lee's configuration diagram. 120, 121. 122. 123. 124 1
25---First stage partial product addition circuit, 130.
]]3L] 32------Second stage partial product addition circuit, ], /l O, I 41----To third stage partial product addition circuit, 150-----1 Final stage partial product addition circuit, 170171, . 172,173,174.17
5---Pass for testing partial product addition circuit,
400 multiplicand generation circuit, 402 --- multiplier generation circuit, 406 first node IJ, :11- circuit,
4o7---Second recode circuit, 408---
3rd recode circuit, 409---partial product addition circuit, 410 data compressor, 412---test signal, 41, 6---product, 4]7-product compression result,
5゜0----Cell, 501-----1st test register, 502'--12nd test register, 504 pattern generator, 505-1-
--First means, 506--Second means, 507--
-Third means. Patent applicant Matsushita Electric Industrial Co., Ltd. Patent attorney Yoshiki Okamoto No. 1'';

Claims (4)

[Claims] (1) n-digit multiplier (Y=y_n_-_1y_n_-_
2---------y_1y_0; The most significant digit is y_n_-
_1, n≧2, n is an integer) is an addition in which a partial product is generated from a multiplicand using the Booth recoding method from consecutive 3 digits, and the resulting addition results are also added multiple times. In a multiplier that configures a partial product addition circuit with a tree, any consecutive 2k+1 digits y_m_+_ in the multiplier Y
2_k_−_1y_m_+_2_k_-_2−−−−−
−−−−y_m_+_1y_my_m_−_1 (k≧
2; k is an integer; m=n-1, n-2, ------1
; If m>n-1, y_m_+_2_k_-_1=y
_m_+_2_k_-_2=−−−−−−−−=y_m
a first step of generating a plurality of input combinations of _+_1=y_m=0), and the most significant digit of the 2k+1 digits y_m_+_2_k_-_1
The same value as y_n_-_1 to y_m_+ in the multiplier
A second step of setting each digit up to _2_k, and setting the same value as y_m_-_1 in the multiplier to y_m_-_2.
A multiplier testing method characterized in that a test is performed using a multiplier generated by a third step of setting each digit from y_0 to y_0. (2) n-digit long multiplier (Y=y_n_-_1y_n_-_
2-----y_1y_0; the most significant digit is y_n_-_1
, n≧2, n is an integer) to generate partial products using Booth's recoding method, and add the partial products one by one. A multiplier configured as a product addition circuit, the multiplier comprising: additional digit setting means for setting a plurality of additional digits at the upper and lower positions of the multiplier; a first partial product generation circuit that generates a partial product located at the lowest position and sets the value of the additional digit to 0 when the test signal is invalid to generate a partial product located at the lowest position; and when the test signal is valid; a second partial product generation circuit that generates a partial product located at the highest position using the multiplier and the additional digit, and generates a partial product located at the highest position by setting the value of the additional digit to 0 when the test signal is invalid; A multiplier comprising: (3) Any consecutive 2k+1 digit y_m in the multiplier Y
＿＋＿2＿k＿−＿１y＿m＿＋＿２＿k＿−＿２−−
−−−−−−y_m_+_1y_my_m_−_1(k
≧2; k is an integer; m=n-1, n-2, --------
-1; if m>n-1, y_m_+_2_k_-_1
=y_m_+_2_k_-_2=−−−−−−−−=y
a first means for generating a plurality of input combinations of _m_+_1=y_m=0), and a most significant digit of the 2k+1 digits y_m_+_2_k_-_1
The same value as y_n_-_1 to y_m_+ in the multiplier
A second means for setting up to _2_k, and a third means for setting all of y_m_-_1 to y_0 to 0 or 1, and a test using the multiplier automatically generated by the first to third means. The multiplier according to claim 2, characterized in that: (4) A constant generating means for generating a plurality of multiplicands, and a linear feedback shift register that inputs the product obtained from the partial product addition circuit, and after inputting the plurality of multiplicands or multiplicands, the linear feedback shift register is written to the linear feedback shift register. Claim 2, characterized in that the output data is outputted.
Or the multiplier described in 3.