JPH0414696A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve yield in the case of manufacture by changing relative potential difference between detected substrate bias voltage and a prescribed value according to a signal from the outside and changing the size of a power supply voltage to continuously or intermittently switch the generation of substrate bias. CONSTITUTION:A resistance dividing ratio varying means 4aa composed of a fuse F1 and a PMOS transistor P2 is added to the conventional circuit. Therefore, in respect to the same substrate voltage VBB, a voltage VL of a node NL can be changed to the two kinds of levels. Accordingly, the relative potential difference between the substrate bias voltage detected by a substrate bias detection circuit 4a and the circuit threshold value of an inverter INV3 of a delay circuit 4b can be changed by cutting the fuse F1. When the fuse F1 is cut off and the power source is turned on, a power supply voltage VDD is increased and the substrate bias voltage VBB is lowered. Then, the power supply voltage for switching the substrate bias circuit 3 from the continuous operation to the intermittent operation is made lower than the case of not cutting the fuse F1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to one having a substrate bias voltage generation circuit.

(Prior Art) In a semiconductor memory device, by applying a bias voltage to the substrate, it is possible to prevent the parasitic pn junction from becoming forward biased due to undershoot of an external signal, and to prevent the parasitic pn junction from becoming forward biased due to the undershoot of an external signal. Efforts are being made to widen the width of the circuit to reduce parasitic capacitance and speed up circuit operation.

On the other hand, with the rapid spread of personal computers, there is a need for low power consumption semiconductor storage devices capable of battery backup, which retains data using batteries. DRAM for large capacity and low cost equipment
In order to make it effective or to enable battery backup, the current during standby must be reduced. In a DRAM, there are several circuits that consume current during standby, but the substrate bias voltage generation circuit consumes a large amount of current.

Therefore, in order to reduce the standby current, it is necessary to reduce the current consumption of the substrate bias generation circuit.

The configuration of a conventionally used substrate bias generation circuit is shown in FIG. When the ring oscillator 1 is powered on, it self-oscillates and outputs a constant cycle pulse RING. The substrate bias drive circuit 2 drives the substrate bias circuit 3, and is a NOR circuit NOI? which receives the pulse RING and the control signal SL output from the comparison circuit 14. and two-stage inverters INVI and 1NV2 that output a drive signal Φ2 for driving the substrate bias circuit 3. The NOR circuit NOR outputs a pulse RING as the output signal Φ1 when the control signal SL is at a low level, and stops outputting when the control signal SL is at a high level to fix the output signal Φ1 at a low level. That is, the operation of the substrate bias circuit 3 is controlled by the level of the control signal SL.

The substrate bias circuit 3 includes an N-channel MOS transistor N2 that pumps charge from the substrate, a capacitor IkC1 that accumulates the pumped charge, and an N-channel MOS transistor N1 that discharges the accumulated charge to a ground terminal. . The maximum substrate bias voltage vBBMAx that can be generated by this substrate bias circuit 3 is expressed as in equation (1).

VBBMAx= −K −VDD+ VTNI + V
TN2-(1) Here, K is the coupling ratio between the drive signal Φ2 and the drive signal Φ3 via the capacitor C, VDD is the power supply voltage, VTNI is the threshold voltage of the N-channel MOS transistor N1, and VTN2 is the This is the threshold voltage of the N-channel MOS transistor N2.

Substrate bias voltage VBB outputted by substrate bias circuit 3
is input to the comparison circuit 14. The comparison circuit 14 includes a substrate bias detection circuit 14a and a delay circuit 4b. The substrate bias detection circuit 14a has a power supply voltage VDD.
It has a normally-on P-channel type MO3) transistor P1 and an N-channel type MOS transistor N3 connected in series between the terminal and the substrate bias voltage VBB terminal,
A voltage VL that reflects the level of the substrate voltage VBB based on the impedance ratio is output from the node NL.

The delay circuit 4b includes five stages of inverters I NV3 to 1NV7.
The voltage VL output from the substrate bias detection circuit 14a is input. When the voltage VL is lower than the circuit threshold VTN3 of the inverter INVI, a high-level control signal SL is output because it is assumed that the generation of substrate bias should be stopped. If it is high, a low level control signal SL is output to generate a substrate bias. The reason why the voltage VL is delayed and outputted here is to stabilize the switching between the operating state and the stopped state of the substrate bias circuit 3. For example, when the power supply potential fluctuates due to noise, the level of the substrate voltage VBB also fluctuates, but by delaying it, it functions as a noise filter, and the comparator circuit 14
can prevent malfunctions.

The substrate voltage VBB generated by such a substrate voltage generation circuit
FIG. 6 shows the characteristics of the current consumption 100 and the power supply voltage VDD. When the power is turned on, the substrate bias circuit 3 starts continuous operation in synchronization with the pulse RING to generate a substrate bias. As the power supply voltage VDD increases, the substrate bias voltage VBB decreases as shown by the solid line a, and the current consumption IDD of the substrate bias generation circuit increases sharply.

Then, when the power supply voltage VDD rises to the voltage VP and the substrate voltage VBB decreases until the voltage VL at the node NL is lower than the circuit threshold VTN3 of the inverter INV3 (
The substrate voltage at this time is VBBL), delay circuit 4
The control signal SL output from b becomes high level. Then, the drive signal Φ2 fixed at a low level is applied from the substrate bias drive circuit 2 to the substrate bias circuit 3, and the operation of generating the substrate bias is stopped. From this point on,
The operation shifts to generating a substrate bias intermittently.

Once the operation of generating the substrate bias is stopped, the rate at which the substrate bias voltage VBB decreases decreases as shown by the solid line, and the current consumption IDD of the substrate voltage generation circuit sharply decreases. Here, the dotted line C indicates the substrate bias voltage VBB when the substrate bias circuit 3 is continuously operated, and decreases at the same rate as when the power supply voltage VDD is lower than the voltage Vp.

Substrate bias voltage VBB when intermittent operation is performed
FIG. 7 shows the relationship between the drive signal Φ2 and the drive signal Φ2.

In the section a, the pulse RING is applied to the substrate bias circuit 3 as the drive signal Φ2 to operate, and the substrate bias voltage VBB drops. When the voltage drops to VBBL, the output voltage VL from the node of the substrate bias detection circuit 14a becomes lower than the circuit threshold VTN3 of the inverter INV3. However, after being delayed for a time td by the delay circuit 4b, the control signal SL becomes high level. Therefore, the substrate bias voltage VBB decreases to VBBI, which is lower than the voltage V BBL.

After this period, the substrate bias circuit 3 stops operating. During this time, the drive signal Φ2 is fixed at low level. During this time, the parasitic capacitance existing in the substrate is charged by leakage current in the substrate bias detection circuit 14a and the junction, so that the substrate bias voltage VBB increases.

When the substrate bias voltage VBB rises to the voltage VBBL, the output VL from the substrate bias detection circuit 14a becomes higher than the circuit threshold VTN3 of the inverter INV3.

After being delayed by the time td by the delay circuit 4b, the control signal SL becomes low level. In this case, the substrate bias voltage VBB is changed to the voltage V BBL by the amount of delay.
The voltage rises to VBH3, which is higher than the voltage VBH3. The substrate bias drive circuit 2 outputs the pulse RIN again as the drive signal Φ2.
G is output, a substrate bias is generated from the substrate bias circuit 3, and the substrate bias voltage VBB decreases.

In this way, so that the substrate voltage VBB fluctuates between the voltage VBBI and the voltage VBB2 with the voltage VBBL as the boundary,
The substrate bias circuit 3 intermittently repeats an operating state and a stopped state. As a result, the current consumption of the substrate bias generation circuit is distributed and reduced.

(Problems to be Solved by the Invention) However, such a conventional substrate bias voltage generation circuit has the following problems.

For example, in order to perform backup with a 3V battery, it is necessary to set the power supply voltage Vp to 3V or less when the substrate bias voltage generation circuit switches from continuous operation to intermittent operation. However, the transistor characteristics fluctuate due to manufacturing variations, and it is difficult to set the transistor so that the operation can be switched accurately at the power supply voltage Vp, resulting in a decrease in yield.

The present invention has been made in view of the above circumstances, and is capable of changing the power supply voltage to switch the operation that generates substrate bias from continuous operation to intermittent operation even if the characteristics of the transistor vary due to manufacturing variations. It is an object of the present invention to provide a semiconductor memory device that can be set to a certain value and contribute to an improvement in yield.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a substrate bias circuit that outputs a substrate bias voltage to be applied to a substrate, a substrate bias detection circuit that detects the output substrate bias voltage, and a substrate bias voltage that is detected. A comparison circuit that compares the relative potential difference between and a predetermined value and outputs a signal according to the comparison result, and a substrate bias circuit that continuously generates a substrate bias voltage based on the output signal. It is equipped with a substrate bias drive circuit that switches between a continuous operation state and an intermittent operation state, and the comparison circuit receives a control signal from the outside and compares the substrate bias voltage detected by the substrate bias detection circuit with a predetermined value. It is characterized by having a potential difference variable means for changing the relative potential difference between the two.

Here, in the comparison circuit, one end of the first element group having at least one impedance is connected to the power supply terminal, and the first element group has at least one impedance.
One end of a second element group having at least one impedance is connected to the other end of the element group, and a substrate bias voltage is applied to the other end of the second element group, and the power supply terminal and the first and first elements are connected to each other. An impedance ratio variable means is provided in which an element that is disconnected when a control signal is input from the outside and a third element group having at least one impedance are connected in series between terminals to which the second element group is connected. connected,
Comparing means for comparing the relative potential difference between the voltage generated between the terminals and a predetermined value and outputting a signal according to the comparison result, and delay means for delaying the output of the comparing means are connected between the terminals. It may be something.

(Function) The substrate bias voltage outputted by the substrate bias circuit is detected by the substrate bias detection circuit, and the relative potential difference between the detected substrate bias voltage and a predetermined value is compared by the comparison circuit. A signal corresponding to the comparison result is output from the comparison circuit, and based on this signal, the substrate bias drive circuit switches the substrate bias circuit between a continuous operation state and an intermittent operation state. In this case, the comparator circuit has a potential difference variable means that receives a control signal from the outside and changes the relative potential difference between the substrate bias voltage detected by the substrate bias detection circuit and a predetermined value. Even if the operating characteristics of each element change due to variations, the comparison result changes by changing this relative potential difference, and the power supply voltage at which the substrate bias drive circuit switches the operating state of the substrate bias circuit can be changed. This makes it possible to switch the operating state of the substrate bias circuit with an appropriate power supply voltage even if there are manufacturing variations.
Yield is improved.

Here, when the comparator circuit has the first and second elements, the impedance ratio variable means, the comparison means and the delay means, the case where the element of the impedance ratio variable means is disconnected by inputting a control signal from the outside and the disconnection. In the case where the first element and the second element are not connected, the voltage between the terminals to which the first element and the second element are connected changes. The voltage in the case of not being disconnected is the parallel combined impedance of the first element and the third element,
It is determined by the impedance ratio with the impedance of the second element. The voltage when the element is disconnected is determined by the impedance ratio between the impedance of the first element and the impedance of the second element. In this way, the external control changes the voltage between the terminals to which the first element and the second element are connected, so that the comparison result of the comparison means can be changed. Further, by providing the delay means for delaying the output of the comparison means, the operation of the substrate bias circuit whose operating state can be switched according to the comparison result is stabilized.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of this embodiment. The difference from the conventional case shown in FIG. 5 is that a resistance division ratio variable means 4aa is connected to the node NL of the substrate bias detection circuit 4a of the comparison circuit 4. Other identical components are given the same numbers and their explanations will be omitted.

The impedance ratio variable means 4aa includes fuses F1 and P connected in series between the power supply terminal and the node NL.
It consists of a channel type MO8) transistor P2.

The drain and gate of the P-channel type MO3) transistor P2 are connected to the node NL, and the source is connected to the other end of the fuse F1, one end of which is connected to the power supply terminal.

And this fuse F1 is formed of metal wiring,
It can be cut by being irradiated with a laser beam or the like from the outside.

By providing such an impedance ratio variable means 4aa at the node NL, it becomes possible to change the voltage VL at the node NL to two different levels for the same substrate voltage VBB. The voltage VL when the fuse F1 is not disconnected is the parallel composite impedance formed by the parallel-connected normally-on P-channel type MO transistors P1 and P2, the node NL, and the substrate voltage VBB.
It is determined by the impedance ratio of the impedance with the normally-on N-channel MOS transistor N3 connected between the terminal and the N-channel MOS transistor N3.

On the other hand, the voltage VL when the fuse F1 is cut is P
Since channel type MOS transistor P2 is not involved,
It is determined by the ratio of the impedance of P-channel type MOS transistor P1 and the impedance of N-channel type MOS transistor N3 with respect to substrate voltage VBH. If the fuse F1 is cut here, the voltage VL will be lower than when it is not cut.

In this way, by newly adding the impedance ratio variable means 4aa to the node NL, the substrate bias voltage detected by the substrate bias detection circuit 14a and the delay circuit 4b
The relative potential difference between the inverter 1NV3 and the circuit threshold VTN3 can be changed externally.

FIG. 2 shows the relationship between power supply voltage VDD and consumption current IDD in this embodiment. The substrate bias voltage VBB when the fuse F1 is not cut is shown by solid lines a and b,
Real if disconnected! It is shown by sa and - dotted chain line f. When the power is turned on, the power supply voltage VDD increases and the substrate bias voltage VBB (solid line a) decreases. Substrate bias circuit 3
When switching from continuous operation to intermittent operation, the power supply voltage Vpl when the fuse F1 is disconnected is lower than the voltage vp2 when the fuse F1 is not disconnected, and the switch occurs at a lower power supply voltage. This is because the voltage VL decreases by cutting the fuse F1, so when the substrate voltage VBB is higher than when it is not cut, the inverter I N
This is because it is below the circuit threshold value VTN3 of V3. When the fuse is intermittently operated, the substrate bias voltage VBB becomes higher when the fuse is disconnected (-dotted chain line f) than when it is not disconnected (solid line b).

Accordingly, the current IDD consumed by the substrate bias generation circuit
is better than when fuse F1 is not cut (curve d).
It is smaller when fuse F1 is cut (curve e).

As described above, according to this embodiment, the power supply voltage VDD when the substrate bias voltage generation circuit switches from continuous operation to intermittent operation can be selected from two types by external control. It is possible to deal with variations in transistor characteristics due to variations in the number of transistors, thereby improving yield.

The embodiments described above are merely examples and do not limit the present invention. For example, the substrate bias detection circuit 4a can have various configurations as shown in FIG. 3 or FIG. 4. 3 shows the P-channel MOS transistors P1 and P2 in FIG. 1 replaced with N-channel MOS transistors N4 and N5, and FIG. 4 shows the P-channel MOS transistors P1 and P2 in FIG. and N-channel type MO5) transistor N3, resistor element R1
, R2 and R3.

〔Effect of the invention〕

As explained above, according to the present invention, the substrate bias circuit generates a substrate bias by changing the relative potential difference between the substrate bias voltage detected by the substrate bias detection circuit and a predetermined value by inputting an external signal. The power supply voltage for switching from continuous operation to intermittent operation can be changed, so even if the operating characteristics of each element change due to manufacturing variations, the switch can be made with an appropriate power supply voltage. It is possible to improve the yield.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing changes in current consumption and substrate bias voltage with respect to power supply voltage, showing the operating characteristics of the device. , FIG. 3 is a circuit diagram showing the structure of a semiconductor memory device according to another embodiment of the present invention, FIG. 4 is a circuit diagram showing the structure of a semiconductor memory device according to still another embodiment of the present invention, and FIG. Figure 6 is a circuit diagram showing the configuration of a conventional semiconductor memory device, Figure 6 is a waveform diagram showing the operating characteristics of the device, showing changes in current consumption and substrate bias voltage with respect to power supply voltage, and Figure 7 is the same device. FIG. 3 is a waveform diagram showing changes in substrate voltage when the device is in an intermittent operating state. DESCRIPTION OF SYMBOLS 1... Ring oscillator, 2... Substrate bias drive circuit, 3... Substrate bias circuit, 4... Comparison circuit,
4a... Substrate bias detection circuit, 4aa... Impedance ratio variable means, 4b... Delay circuit, NOR
...NOR circuit, INvl-INV7...inverter, C...capacitance, N1-N5...N-channel MO
S) Transistor, PI, P2...P channel type MOS
Transistor, Fl...Fuse, R1-R3...
resistance.

Claims (1)

[Claims] 1. A substrate bias circuit that outputs a substrate bias voltage to be applied to a substrate; a substrate bias detection circuit that detects the output substrate bias voltage; and a predetermined value of the detected substrate bias voltage. a comparison circuit that compares a relative potential difference between the two and outputs a signal according to the comparison result, and a substrate bias circuit that continuously performs an operation of generating the substrate bias voltage based on the output signal. The comparator circuit includes a substrate bias drive circuit that switches between a continuous operation state and an intermittent operation state, and the comparison circuit receives a control signal from the outside and compares the substrate bias voltage detected by the substrate bias detection circuit with the substrate bias voltage detected by the substrate bias detection circuit. A semiconductor memory device comprising a potential difference varying means for varying a potential difference relative to the predetermined value. 2. In the comparison circuit, one end of a first element group having at least one impedance is connected to a power terminal, and a second element group having at least one impedance is connected to the other end of the first element group. One end is connected and this second
The substrate bias voltage is applied to the other end of the element group, and the element is disconnected when the control signal is input from the outside between the terminal to which the first and second element groups are connected and the power supply terminal. and a third impedance having at least one impedance.
Comparing means is connected to an impedance ratio variable means in which a group of elements are connected in series, and compares a relative potential difference between the voltage generated between the terminals and a predetermined value, and outputs a signal according to the comparison result; 2. The semiconductor memory device according to claim 1, further comprising delay means for delaying the output of said comparison means, and is connected between said terminals.