JPH04142618A - Information processing unit - Google Patents

Abstract

PURPOSE:To make it possible to carry out high speed sequence change processing by providing the present information processing unit with a bit sequence rearrangement circuit that is started when a specific instruction is issued for rearranging specified data words into a bit sequence indicated by sequence information in the specific instruction. CONSTITUTION:When a specific instruction 11 is issued that is specified for rearrangement of bit sequence of data words by an instruction issuing means 10, a bit sequence rearrangement circuit 23 is started. Accordingly, the bit sequence rearrangement circuit 23 executes the bit sequence rearrangement operation indicated by a specific instruction 11 for data words specified by symmetric data word specified information of the specific instruction. Here, the execution instruction is provided with sequence rearrangement information where a rearranged bit sequence can be arbitrarily specified, and the bit sequence rearrangement circuit 23 rearranges a bit sequence of specified data words into a bit sequence indicated by this sequence rearrangement information. With this, a bit sequence of data words can be rearranged into an arbitrary sequence at high speed by one time processing of the specific instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to an information processing apparatus suitable for data conversion processing that involves rearranging the bit order of data words, such as data format conversion.

(Prior Art) One type of data processing performed by an information processing device is data conversion processing performed to accommodate differences in bit representations (formats) of data. Improving the efficiency of this data conversion process is often important for improving the overall data processing performance of an information processing device.

Now, in data conversion processing, the process of changing the order of bits in a data word (bit order, bit arrangement) to another order is extremely important.

Conventionally, operations for rearranging the bit order of data words have often been programmed using a combination of bit-by-bit shift operations and logical operations (OR operations). In addition, there are cases where a dedicated hardware circuit is applied only to rearrangement of a certain specific bit order.

(Problem to be solved by the invention) In order to rearrange the bit order of data words, as in the past,
Programming using a combination of bit-by-bit shift operations and logical operations requires a large number of program steps, which poses a problem in that data processing performance cannot be improved. Further, a method in which only a specific sorting is processed by a dedicated hardware circuit has the problem of being ineffective, expensive, and difficult to use from a language program such as a compiler.

This invention was made in view of the above circumstances, and its purpose is to rearrange the bit order of data words in any order.
An object of the present invention is to provide an information processing device that can perform high-speed command processing in one time.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a specific instruction for instructing rearrangement of the bit order of data words, which includes target data for specifying the data words to be rearranged. an instruction issuing means for issuing various instructions including a specific instruction having word designation information and rearrangement information for indicating the bit order after sorting; ,
The present invention is characterized by the provision of a bit order reordering circuit that rearranges the data words specified by the target data word designation information of the specific instruction in the bit order indicated by the reordering information of the specific instruction.

(Operation) According to the above configuration, when the instruction issuing means issues a specific instruction that instructs to rearrange the bit order of the data word,
The bit order reordering circuit is activated. Thereby, the bit order rearrangement circuit executes the bit order rearrangement operation instructed by the above-mentioned specific instruction on the data word specified by the target data word designation information in the same instruction. Here, the execution instruction is provided with sorting information that can arbitrarily specify the bit order after bit sorting, and the bit order sorting circuit sorts the bits in the designated data word in the bit order indicated by this sorting information. Sort. Therefore, by specifying this sorting information, the bit order of the data word can be rearranged in any order.

(Embodiment) FIG. 1 shows a block configuration of an information processing apparatus according to an embodiment of the present invention. In the figure, 10 is a main memory in which various programs, data, etc. are stored, and 11 is a main memory lO.
Various instruction words (
This is a bit permutation instruction, which is one of the machine language instructions.

This bit permutation instruction 11 is a machine language instruction that instructs to rearrange the bit order of a data word in an arbitrary order, and as shown in FIG. 2, instructs to rearrange the bit order. P code (operation code), source register specification information (SR specification information) that specifies the register (source register) in which the data words to be sorted are stored, and the storage destination register (destination register) for the data words to be sorted. It has destination register designation information (DR designation information) that designates the destination register (Nation register), and rearrangement information that indicates the bit order after rearrangement.

20 is a CPU that executes and controls programs stored in the main memory 10; 30 is the main memory 10 and the CPU;
20 interconnecting buses.

The CPU 20 includes a register file 21 consisting of a group of registers, an arithmetic unit 22 that executes operations such as addition and subtraction (here, 8-bit operations), and a data word (here, 8-bit operations).
Rearrangement control bit C
It has a bit order rearrangement circuit 23 which is a dedicated hardware circuit that executes at high speed according to O to C23.

The CPU 20 also sends data words read from the register file 21 to an arithmetic unit 22 or a bit order sorting circuit 2.
A demultiplexer (D
EMUX) 24, and a multiplexer (MUX) 25 that selects either the output of the arithmetic unit 22 or the bit order rearrangement circuit 23 and outputs it to the register file 21. The CPU 20 further includes an instruction register 26 for holding an instruction word to be executed that is read from the main memory 10 via the bus 30, and decodes the instruction word held in this instruction register 26 and executes the same instruction word. It has an instruction decoder 27 that generates various control signals necessary to perform the operations. When the instruction word held in the instruction register 26 is the bit permutation instruction 11, the instruction decoder 27
The same instruction ll for controlling the bit order rearrangement circuit 23
Sorting control bit CO~ corresponding to the sorting information in
At the same time as generating C23, the data word of the register specified by the SR information is extracted from the register file 21 and inputted to the bit order sorting circuit 28 via the demultiplexer 24, and the data output from this bit order sorting circuit 23. The control signal group 2B necessary for inputting the word to the register in the register file 21 designated by the DR information through the multiplexer 25 is generated.

FIG. 3 shows the internal configuration of the bit order rearrangement circuit 23. The bit order sorting circuit 23 includes an input data buffer 41 that holds the 8-bit data word (bo to b7) outputted from the demultiplexer (DEMUX) 24 shown in FIG. 1, and an instruction decoder shown in FIG. 27, and a rearrangement control data buffer 42 that temporarily holds the rearrangement control bits CO to C23 outputted from 27. The bit order rearrangement circuit 23 further rearranges the bit order of the data words held in the input data buffer 41 by using the output of the rearrangement control data buffer 42 (reorder control bit CO=C2
It has 24 2-bit exchangers EO to E23 for sorting according to 3), and an output data buffer 43 that temporarily holds the 8-bit data words after the sorting. 2 each
The bit exchanger E1 (1 to 0 to 23) each receives 1 bit of left input IL + right input air, 1 bit of left output OL, right output OR, and rearrangement control bit CI.
has a 1-bit control input to which Ci-“0” is input.
” then IL-OL.

CI does not exchange left and right bits like 1R-OR.
-"1°0) ts H I L -OR, I R"0L
The left and right bits are exchanged as shown in (7).

2-bit exchangers EO, El, E2. E3 is the data word b7 and be held in the input data buffer 41.
, b5 and b4. b3 and b2. Let bl and bo be left and right inputs, respectively. 2-bit exchanger E4. E5. E6. E7
i; i, left output of 2-bit exchangers EO and El, right output of 2-bit exchangers EO and El, left output of 2-bit exchangers E2 and E3.

The right side outputs of 2-bit exchangers E2 and E3 are used as left and right inputs, respectively. 2-bit exchanger E8. E9゜E 10.
E11 is the left output of 2-bit exchangers E4 and E5,
The right side outputs of 2-bit exchangers E4 and E5, the left side outputs of 2-bit exchangers E6 and E7, and the right side outputs of 2-bit exchangers E6 and E7 are used as left and right inputs, respectively. 2 bit exchanger E
12. El3. El4. El5 is the left output of 2-bit exchanger E8 and EIO, 2-bit exchanger E8 and EIO.
The right side output of IO, the left side output of 2-bit exchangers E9 and Ell, and the right side output of 2-bit exchangers E9 and Elf are used as left and right inputs, respectively. 2-bit exchanger E1B, El7
．． Elg and El9 are the left outputs of 2-bit exchangers E12 and El4, the left outputs of 2-bit exchangers E13 and El5, the right outputs of 2-bit exchangers EI2 and El4, and 2
The right side outputs of bit exchangers E13 and El5 are used as left and right inputs, respectively. 2-bit exchanger E20. E21. E
22. E23 is the left output of 2-bit exchangers E16 and El7, the right output of 2-bit exchangers E1B and El7, 2
The left side outputs of bit exchangers ElB and El9 and the right side outputs of 2-bit exchangers E18 and El9 are used as left and right inputs, respectively.

Next, the operation of one embodiment of the present invention will be explained.

Now, the bit permutation instruction 11 in the format shown in FIG.
It is assumed that the instruction register 26 in U20 is loaded. When the instruction word loaded into the instruction register 2B is bit permutation instruction 11, the instruction decoder 27 converts the bit permutation instruction 11 into
Sorting control bit CO~ corresponding to the sorting information in
C28 and a control signal group 28 are generated and output.

The control signal group 2B output from the instruction decoder 27 includes:
Contains a control signal for reading the 8-bit data word of the register in the register file 21 indicated by the SR information in the bit permutation instruction 11, and this control signal causes the data word of the corresponding register in the register file 21 to be read. The signal is read out to a demultiplexer (DMUX) 24. When the instruction word loaded into the instruction register 26 is the bit permutation instruction 11, the demultiplexer 24 rearranges the bit order of the data words successively output from the register file 21 according to a predetermined signal in the control signal group 28. Selectively output to the circuit 23.

Bit order reordering circuit 2 by demultiplexer 24
3, the data word selected and output to register file 2
The 8-bit data words (bO to b7) to be read out from 1 and to be rearranged in bit order are held in the input data buffer 41 in the same circuit 23.

A rearrangement control data buffer 42 in this bit order rearrangement circuit 23 holds rearrangement control bits CO to C23 generated and output from the instruction decoder 27. The rearrangement control bits CO to C23 held in the rearrangement control data buffer 42 are supplied to control inputs of two-bit exchangers EO to E23 in the bit order rearrangement circuit 23.

The 2-bit exchangers EO to E23 operate according to the logic values of the rearrangement control bits CO to C23 supplied to the control inputs.
Either swap left and right bits like →OR, IR→OL, or just output without swapping left and right bits like I, →O,,,I, →OR. perform the following actions. Due to the operation of the 2-bit exchangers EO-E23, the 8-bit data words bO-b7 held in the input data buffer 41 are changed to the rearrangement control bits CO-C.
23, and the data word BO~
It is held in the output data buffer 43 as B7. Third
In the example of the bit order rearrangement circuit 23 shown in the figure, if, for example, only C3 among the rearrangement control bits CO to C23 is "1", the bit order of the data words bO to b7 is such that bo and bl are exchanged and bl bOb2 b3 b4 b5 be
If, for example, only C1B to C19 of the rearrangement control bits CO to C23 are "0", the bit order of the data words bO to b7 is reversed and b7 beb
5 b4 b3 b2 bl bO.

The data word after the bit order reordering held in the output data buffer 43 is selectively outputted to the register file 21 by the multiplexer 25, and is sent to the register specified by the DR information of the bit permutation conversion instruction 11 held in the instruction register 26. written to.

In the above embodiment, the reordering control bits CO to C23 given to the bit order reordering circuit 23 were described as being generated by the instruction decoder 27, but the reordering information in the bit permutation conversion instruction ll is arranged as is. It is also possible to adopt a configuration in which it is used as the replacement control bit Co-C23.

Further, in the embodiment described above, the bit order rearrangement of an 8-bit data word has been explained, but the present invention can also be applied to the bit order rearrangement of data words having other bit configurations. Further, the present invention can be applied not only to bit order rearrangement for data format conversion but also to bit manipulation in image processing and graphic processing.

[Effects of the Invention] As described in detail above, according to the present invention, there is provided a specific command that instructs to rearrange the bit order of a data word, and which has rearrangement information to indicate the bit order after the rearrangement. A configuration that prepares an instruction and includes a bit order sorting circuit that is activated when this specific instruction is issued and sorts the data words specified by the instruction in the bit order indicated by the sorting information in the instruction. By doing so, the bit order of the data word can be rearranged in an arbitrary order by one instruction process, and the rearrangement process can be speeded up and the number of processing steps can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the format of the bit permutation instruction 11 shown in FIG. 1, and FIG. 3 is a diagram showing the bits shown in FIG. 1. 2 is a diagram showing the internal configuration of a rearrangement circuit 23. FIG. 10... Main memory, 11... Bit permutation conversion instruction,
20...CPU, 21...Register file, 23
. . . Bit order sorting circuit, 26 . . . Instruction register, 27 . . . Instruction decoder, EO to E23 . Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A specific instruction for instructing rearrangement of the bit order of data words, which indicates target data word designation information for designating the data words to be rearranged and the bit order after rearrangement. an instruction issuing means for issuing various instructions including a specific instruction having rearrangement information for the above-mentioned data; An information processing device comprising: a bit order reordering circuit that rearranges data words designated by designation information in the bit order indicated by the reordering information of this specific instruction.