JPH04142071A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the cooling efficiency of chips by providing a junction having Peltier effect formed while being isolated from a semiconductor chip and an electrode which supplies DC current to this junction. CONSTITUTION:A semiconductor chip 12 is housed in an artificial resin mold package 11, for example, which is also provided with a semiconductor junction 17 having Peltier effect formed based on a mother material which comprises an inner lead section 14, an outer lead section 15 of a lead frame, a bed section 16, a semiconductor chip 12 or a bonding wire 18. DC current is supplied to the junction having Peltier effect during the performance of the semiconductor chip. Therefore, the current flows into the interface having Peltier effect where a metal or a metal compound contacts, thus causing heat absorption reaction on the junction surface and enables direct cooling of the chip inside the package. It is, therefore, possible to enhance the cooling efficiency of chips.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a cooling structure for a semiconductor chip.

(Prior Art) When operating a semiconductor chip in which functional elements are formed on a semiconductor substrate or a semiconductor device housed in a package, for example, as shown in FIG. When operating the semiconductor device housed in the semiconductor chip 42, the heat generated from the semiconductor chip 42 is transferred to the outside of the chip along a path shown by an arrow in the figure. Note that the chip 42 is placed on and fixed to the bed portion of the lead frame 43.

In conventional semiconductor devices, when the amount of heat generated is small, the chip is cooled by natural air cooling, and when the amount of heat generated is relatively large, the chip is cooled by cooling the chip with heat dissipation fins 51 as shown in FIGS. 5(a) and 5(b). 6 Heat dissipation fins 6 as shown in Figures (a) and (b)
1 or radiating fins 71 as shown in FIGS. 7(a) and 7(b) are attached to the package, and the chip is cooled by forced air cooling of the package.

Conventional cooling structures for semiconductor devices as described above do not allow cooling outside the package because the amount of heat generated from the chip is large in LSIs with high power consumption such as logic LSIs (Large-Scale Integrated Circuits) that require high-speed operation. Even with forced air cooling by attaching radiation fins, there is a limit to how much the chip can be cooled due to the thermal resistance of the package itself, and even if the outside temperature is around room temperature, the chip temperature will reach over 100 degrees Celsius. This temperature rise due to heat generated by the chip not only significantly deteriorates the reliability of the semiconductor device but also reduces the operating speed of the chip.

Furthermore, in recent years, in order to realize higher-speed LSIs, consideration has been given to operating LSIs at low temperatures. but,
In conventional cooling structures for semiconductor devices, even if the package is cooled with a liquid such as liquid nitrogen, the chip itself becomes hot due to the chip's self-heating and the package's thermal resistance.
A sufficient cooling effect cannot be obtained, and there is still the problem that not only the reliability of the semiconductor device is significantly deteriorated, but also the operating speed of the chip is reduced.

(Problems to be Solved by the Invention) As mentioned above, in conventional semiconductor devices, even when the chip is cooled by forced air cooling of the package by attaching radiation fins to the outside of the package, the package is cooled with a liquid such as liquid nitrogen. Even when the chip is cooled, the refrigerant is located outside the package, so the cooling effect on the chip cannot be obtained sufficiently, which significantly deteriorates the reliability of semiconductor devices and reduces the operating speed of the chip. There's a problem.

The present invention was made to solve the above-mentioned problems, and its purpose is to make it possible to directly cool the chip inside the package, increase the cooling efficiency of the chip, and reduce the amount of heat generated by the chip. It is an object of the present invention to provide a semiconductor device having a cooling structure that can sufficiently cope with cases where high-speed operation is required.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a semiconductor device in which a semiconductor chip having a functional element formed on a semiconductor substrate or a semiconductor device housed in a package, in which a semiconductor chip and a package are arranged. or a junction having a Peltier effect formed on a semiconductor chip and electrically insulated from at least the semiconductor chip;
It is characterized by comprising an electrode for supplying direct current to this junction.

(Function) By supplying direct current to a junction with the Peltier effect when the semiconductor chip operates, the Peltier effect (current flows through the interface where metals or metal compounds are in contact causes an endothermic reaction at the junction surface). phenomenon), which makes it possible to cool the chip directly inside the package.

Therefore, compared to the conventional cooling structure in which the coolant is placed outside the package, the chip cooling efficiency is higher, so when the present invention is applied to an LSI with large power consumption and large chip heat generation, it is possible to It becomes possible to maintain the temperature at room temperature, and it becomes possible to significantly improve the reliability of the wiring and oxide film inside the integrated circuit. Further, when the present invention is applied to an LSI whose chip generates a small amount of heat, it becomes possible to cool the chip to below room temperature, and high-speed operation becomes possible.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Now, the present invention will be explained in detail. In the semiconductor device of the present invention, a junction having a Peltier effect is formed between a semiconductor chip and a package or on the semiconductor chip while being electrically insulated from the semiconductor chip, and a direct current is applied to this junction. It is characterized by forming an electrode for supplying current.

Here, junctions with the Peltier effect include various combinations, or junctions between a conductor or semiconductor with a positive absolute Peltier coefficient and a conductor or semiconductor with a negative absolute Peltier coefficient, and the Peltier effect B1 is a material that is relatively expensive and does not easily contaminate semiconductor devices.
-3b junction or Cu0Cu20 junction is desirable. Also,
A bond with a Peltier effect is effective whether it is formed directly above or below the semiconductor chip, and the base for forming the bond is the base of the lead frame, which is the chip mounting area in the package, or when the manufacturing process is finished. It is desirable that the chip is When the front or back surface of a chip is used as a base for bonding, a chip may be used in which the bond is formed at the wafer level and then the wafer is diced.

FIG. 1 schematically shows the inside of a semiconductor device in which a semiconductor chip 12 is housed in a synthetic resin mold package 11, for example, with a part cut away. Here, 14 is an inner lead part of the lead frame, 15 is an outer lead part of the lead frame, 16 is a bed part of the lead frame, and 17 is the semiconductor chip 12 or the bed part 1.
Junction with Peltier effect formed using 6 as a matrix, 1
8 is a bonding wire (AuSA, 17, etc.) for electrically connecting the bonding pad on the chip and the inner lead portion 14.

Next, an example of a manufacturing process for a bond having the Peltier effect as described above will be described with reference to FIGS. 2(a) to 2(d).

First, as shown in FIG. 2(a), a metal (generally Au5Pt, Cu, etc.) that will become the lower electrode 21 is placed on the front or back surface (or the bed portion of the lead frame) of the semiconductor chip 20 in a wafer state, for example.

Use A, Q, etc. ) is deposited by sputtering method or the like.

Next, as shown in FIG. 2(b), a lower bonding material (such as Bi or C) for forming a bond is placed on the lower electrode 21.
Use uO. )22 is formed. In this case, when CuO is used, it can be deposited by sputtering Cu in an oxygen atmosphere with a controlled concentration (hereinafter referred to as reactive sputtering).

Next, as shown in FIG. 2(c), an upper bonding material 23 is formed on the lower bonding material 22 to have, for example, the same size as the lower bonding material, and a bond is formed over the entire surface of the chip. In this case, when B1 is used as the lower bonding material 22,
sb is used as the upper bonding material 23, and the lower bonding material 22
When CuO is used as the upper bonding material 23, it is preferable to use Cu2O as the upper bonding material 23, and both can be formed by reactive sputtering.

Next, as shown in FIG. 2(d), metal (such as Au, Pt, Cu, A, and Q) that will become the upper electrode 24 is applied to the entire surface of the upper bonding material 23. ) is deposited and an arched electrode 25 is connected to each electrode.

When the above-described bond is formed on the bed portion of the lead frame, the semiconductor chip 1 is placed on the upper electrode 24.
2 will be mounted.

Note that when using a Cu0Cu20 junction as a junction having a Peltier effect, the lower electrode 21 and the upper electrode 24
If Cu is used as the electrode, it becomes possible to continuously form the lower electrode 21 to the upper electrode 24 by controlling the oxygen concentration and substrate temperature by reactive sputtering.

For a junction having the Peltier effect as described above, when the semiconductor chip 12 is operated, by supplying a direct current from the lower bonding material 22 side to the upper bonding material 23 side, the lower bonding material 22 and the upper bonding material 23 can be bonded. A Peltier effect occurs at the interface of package 1, and heat is absorbed at this interface.
It becomes possible to directly cool the chip 12 inside the chip 1. Therefore, compared to the conventional cooling structure in which the coolant is placed outside the package, the chip cooling efficiency is higher, so when the present invention is applied to an LSI that consumes a large amount of power and generates a large amount of heat from the chip, it is possible to It becomes possible to maintain the temperature at room temperature, and it becomes possible to significantly improve the reliability of the wiring and oxide film inside the integrated circuit. Furthermore, when the present invention is applied to an LSI whose chip generates a small amount of heat, it becomes possible to cool the chip to below room temperature, and high-speed operation becomes possible.

In addition, in the above embodiment, as shown in FIG. 2(C),
Although the upper bonding material 23 is formed to have the same size as the lower bonding material 22 and the bond is formed on the entire surface of the chip, the bond may be formed only on a part of the chip. This will be explained with reference to FIGS. 3(a) to 3(d).

The steps up to FIGS. 3(a) and 3(b) are the same as in the previous embodiment.

Next, as shown in FIG. 3(c), the upper bonding material 23 is patterned so as to be placed above (or below) the area with a large amount of heat generation.
Form a joint only. Note that patterning of the bonding material may be performed by limiting the sputtering area using a metal mask, or by using a photolithography method commonly used in semiconductor processes.

Next, as shown in FIG. 3(d), an interlayer insulating film (SiO2, etc.) 26 is formed on the entire surface of the upper bonding material 23, and holes for forming electrodes are formed. A metal that will become the electrode 25 is deposited.

[Effects of the Invention] As described above, according to the semiconductor device of the present invention, the chip can be directly cooled by the Peltier effect generated inside the package, and the cooling efficiency of the chip is increased.

Therefore, the power consumption is large and the heat generation amount of the chip is large.
When the present invention is applied to SI, it becomes possible to maintain the chip at room temperature, and it becomes possible to significantly improve the reliability of the wiring and oxide film inside the integrated circuit. Furthermore, when the present invention is applied to an LSI with a small chip heat generation,
This makes it possible to cool the chip below room temperature, making it possible to operate at high speed.

[Brief explanation of drawings]

FIG. 1 is a partially cutaway perspective view schematically showing an embodiment of the semiconductor device of the present invention, and FIGS. 2(a) to 2(d) are manufacturing steps of the junction having the Peltier effect shown in FIG. 1. 3(a) to 3(d) are sectional views showing another example of the manufacturing process of the bonding having the Peltier effect shown in FIG. 1, and FIG. 4 is a sectional view showing a conventional synthetic resin mold package. Figures 5(a) and 5(a) are diagrams showing the transmission path of heat generated from a semiconductor chip in a semiconductor device in which a semiconductor chip is housed.
b) to 7(a) and (b) are a front view and a side view, respectively, of various heat dissipating fins attached to the package of FIG. 4. 1 package, 12... semiconductor chip, 13...
Lead frame, 14... Inner lead part, 15.
Outer lead part, 16... Head part, 17... Bonding with Peltier effect, 18... Bonding wire,
21... Lower electrode, 22... Lower bonding material, 23.
...Top bonding material, 24...Top electrode, 26...Interlayer insulating film.

Claims (2)

[Claims] (1) In a semiconductor device in which a semiconductor chip with functional elements formed on a semiconductor substrate is housed in a package, there is at least an electrical connection between the semiconductor chip and the package or on the semiconductor chip. What is claimed is: 1. A semiconductor device comprising: a junction having a Peltier effect that is formed in an electrically insulated state; and an electrode for supplying direct current to the junction. (2) The semiconductor device according to claim 1, wherein the junction is a junction between a conductor or semiconductor having a positive absolute Peltier coefficient and a conductor or semiconductor having a negative absolute Peltier coefficient.