JPH04140182A - Printer - Google Patents

Abstract

PURPOSE:To perform efficient data communication by successively inputting printing data to an FIFO memory from a host computer and reading said data from the FIFO memory by a CPU while the presence of the data in the FIFO memory is confirmed by an empty flag to store the same in a code buffer. CONSTITUTION:When printing data is sent, the strobe signal from a host computer becomes the writing pulse 29 to an FIFO as it is to input the data to the FIFO and, as a result, an empty flag 30 is turned OFF. A CPU looks the empty flag to confirm the presence of the data to store the data in the code buffer region within an RAM. When data possible in bit map development is generated, it is drawn on a page memory. When this processing continues to a certain degree and the FIFO becomes full, a full signal is turned ON and a control part 24 turns a busy signal ON to temporarily stop the transmission of the data from the host computer. Therefore, when even one data is read from the FIFO, the full signal is turned OFF and, therefore, the full signal is turned OFF when even one data is read from the FIFO and, this time, the control part turns the busy signal OFF to again make the data transmission of the host computer possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention applies to a printer device, which develops print data sent from a host computer, which is a host device, into a bit map page by page on a page memory. The present invention relates to a so-called page printer that sends the image data to an engine as a video signal and prints on paper by raster scanning in accordance with the signal.

(b) Conventional technology In a conventional printer device as shown in Fig. 2,
Print data sent from a host computer, which is a higher-level device, is first input to an interface (11) consisting of a dedicated IC such as an 8255, and each time the data arrives, it is input to a CPU (11) consisting of a microprocessor, etc.
2) is multiplied by an interrupt (20), and the data read from the IC is stored in the system random access memory (hereinafter referred to as
The code was stored in a code buffer called RAM ( ) (13).

Note that (17) is a video interface, and (18) is a printer engine.

However, this method requires an interrupt every time data arrives, resulting in large overhead and
When U is performing high-priority processing such as discharging bitmap data or controlling the engine side, the transmission from the host side has to wait, making it an inefficient communication method for print data. It had become.

As an improvement on this point, a method has been proposed in which it is determined whether the print data is a control code or image data, and if the print data is image data, a predetermined number of data are continuously captured by hardware (Japanese Patent Application Laid-Open No. -29375 for details).

(c) The problem to be solved by the invention is that print data is generally written in ASCII (AS) format.
C) In most cases, the II code is sent.
In most cases, the number of ASCn codes that follow the control code is not specified. Therefore, this method is limited to cases where the number of data that comes after the control code is specified, such as when gradation data is sent, so it cannot be said to be very versatile.

The present invention has been made in view of the problems seen in the conventional examples, and an object of the present invention is to provide an efficient printing device.

(d) Means for solving HIM The present invention provides a FIFO memory for inputting image data sent from a host device, a means for transmitting the state of data stored in the FIFO memory to a CPU, The device is characterized in that it has an interface with a higher-level device comprising means for controlling control signals to the higher-level device depending on the state thereof. (e) Function The present invention sequentially inputs print data from the host to the FIFD memory, and the CPU uses the empty flag to input the print data to the FIFD memory.
While checking the existence of data in FO,
It reads from the IFO and stores it in the code buffer, and when the FIFO memory becomes full, it turns on the busy signal to temporarily suspend data transmission from the host, and at the same time generates an interrupt to notify the CPU of this fact. Let me know. Furthermore, if a blank space is created by the CPU reading data from the FIFO, it will turn off the busy signal.
The host can then send data again.

Therefore, when processing that has a higher priority than importing print data, such as discharging bitmap data or controlling the engine, always stops data transmission from the host and waits until the processing is completed. The conventional disadvantages of waiting are eliminated, and when there is no priority processing, the CPU can continuously store data accumulated in the FIFO in the code buffer, reducing the overhead of interrupt processing when receiving print data. can also be reduced,
It has become possible to perform efficient data communication.

(f) Embodiment FIG. 1 shows a block diagram of a specific embodiment of the present invention, centering on the host interface portion.

The interface includes a buffer unit (22) that inputs print data from the host computer or inputs and outputs each control signal, a FIFO memory (23) that can input 512 bytes of print data, and a control unit (24) that controls each control signal. It is made up of.

This embodiment will be described below with reference to FIG.

First, the engine side is still preparing for printing for a while immediately after the power is turned on, so the CPU sends the output control signal (2) to the host.
8) in a state where print data transmission is prohibited (busy signal is ON,
The select signal is set to 0FF). Among these signals, the select signal in the control section is C.
The data set from PU (32) is used as is, and the busy signal is a full signal (31) indicating whether the FIFO is full.
and the data set by the CPU are output. Then, when the engine becomes ready for printing, the CPU turns off the busy data, and since the FIFO is empty and the full signal is turned off, the final busy signal is turned off. The select signal is directly turned on by the CPU via the control unit, thereby enabling the host side to transmit data.

When print data is sent in this state, the strobe signal from the host becomes the write pulse (29) to the FIFO, and the data is input to the FIFO.
As a result, the empty flag (30) is turned OFF.

When the CPU has no processing that should take priority over print data input (mainly when waiting for print data), the CPU checks this embedded flag to confirm that the data exists, reads the data contained therein, and stores it in the system RAM. Store it in the food buffer area inside. Then, when data that can be expanded into a bitmap onto the page memory is generated, for example, the data is
In the case of a CII code, the corresponding font data is taken out from the font memory and drawn on the page memory. If the time required for this drawing process is short, the drawing process can be performed while receiving received data one after another via the FIFO. Conversely, when drawing processing takes time, data accumulates in the FIFO, but unless it becomes full and the full signal is ONL, data transmission from the host is allowed. If the process continues for a certain amount of time, F
When the IFO becomes full, the full signal is ONL, and the control unit (24) turns on the busy signal to temporarily stop data transmission from the host. At the same time, the CPU
An interrupt (34) is also generated, and upon receiving this interrupt, the CPU successively takes in 512 bytes of data accumulated in the FIFO into the code buffer at once. Therefore, FI
If even one piece of data is read from FO, the full signal is O.
Since the busy signal is turned off, the control unit turns off the busy signal to enable the host to transmit data again.

As mentioned above, when the creation of bitmap data for one page is completed by receiving print data, the engine side is started to move on to printing operation, and the bitmap data is output. Start. At this time F
If the IFO is not full, it is still possible to receive data from the host. In other words, after the engine starts, high-priority interrupt processing such as discharging bitmap data and engine control often occurs, but the control unit automatically imports data into the FIFO while monitoring the FIFO full signal. It's about controlling.

In this way, the control section controls the busy signal based on the FIFO status, but as mentioned above, it can also be controlled by data input from the CPU. By setting data in the control section by the CPLI according to various situations, it is possible to control the busy signal and further various control signals such as paper end and select signals.

In this embodiment, one CPU handles all the processing such as data import, bitmap development on page memory, bitmap data output, and engine side control, but a drawing-only IC is used. It is a hot theory that if you install it and let it perform bitmap development and output processing of bitmap data, you can build an even more efficient system.

Further, although the capacity of the FIFO memory is here set to 512 bytes, this capacity may be increased or decreased depending on the transmission speed of the host side and the processing capacity of the printer side. For example, if there is sufficient processing capacity on the printer side compared to the transmission speed of the host, the capacity can be reduced. Furthermore, in this case, an interrupt (33) occurs when the empty flag turns OFF.
If you set it so that it takes, it is possible to use the same method as the conventional method where an interrupt is generated every time data arrives.

In cases where priority interrupt processing such as engine control occurs frequently, setting a large capacity will reduce the rate at which the host side is forced to wait.

Furthermore, the capacity may be set depending on the type of print data. In the case of the above-mentioned ASCI code, the drawing time is relatively short, but when the print data is a bit image, the drawing process takes a long time. Therefore, in this case F
If the IFO capacity is set to be large, efficient data communication can be performed.

(G) Effects of the Invention As described above, according to the present invention, a FIFO memory is adopted for the host interface to reduce the overhead when receiving print data and to reduce data transmission on the host side for processing on the printer side. By eliminating waste such as waiting, it has become possible to create an efficient communication system.

[Brief explanation of the drawing]

115U is a block diagram of an interface unit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 25, system bus, 2o; interrupt signal, 22-buffer section, 23; FIFO memory, 24: control section, 26; received data, 27; input control signal, 28; output control signal, 29; strobe signal (write pulse) ,3
0: Empty flag signal, 31: Full flag signal, 32. Input data to the control unit, 33: Interrupt signal due to empty flag, 34: Interrupt signal due to full flag. Figure 2

Claims (1)

[Claims] (1) A FIFO memory that inputs image data sent from a host device, means for transmitting the state of data stored in the FIFO memory to the CPU, and control signals to the host device based on this state. What is claimed is: 1. A printer device characterized by having an interface with a host device comprising means for