JPH04138744A - Stm signal transfer system - Google Patents

Abstract

PURPOSE:To attain the transfer of an STM signal via an ATM network by realizing a function processing a VC-n (virtual container frame) on an SDH (synchronizing digital hierarchy) line into a cell. CONSTITUTION:A sender side is provided with a cell processing section 102 having a means detecting a virtual container frame on an STM signal network and generating a cell and a means allocating a prescribed sequence number to a cell corresponding to a head of the virtual container frame and adding a dummy pattern to information corresponding to an end of the virtual container frame. Moreover, a receiver side is provided with a de-cell processing section 103 having a means detecting a cell of a prescribed sequence number, discriminating whether or not the state is just after the connection setting and compensating fluctuation, a means detecting consecutive missing of cells, a means detecting a cell corresponding to the end of the virtual container frame and a means outputting the virtual container frame to the STM signal network.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) This invention uses an ATV (asynchronous transmission mode) network to
The present invention relates to an STM signal transfer method for transferring STM (synchronous transmission mode) signals on a DH network.

(Prior Art) Currently, ISDN networks (Integrated Digital Service Networks) are becoming widespread, and networks using ATM technology are being considered as the form of next-generation communication networks. This next generation network will be broadband
It is called a 5DN network and has the following characteristics.

1) It is possible to accommodate multiple media in one network. 2) Bandwidth is variable. 3) One call can have multiple bearers. The creation work is currently in progress. The ATM technology on which broadband I5DN is based is based on fixed-length packets called cells. Cell format is already CCIT
The header section is 5 bytes and the data section is 48 bytes.

On the other hand, existing STM lines are already in operation, and it is difficult to imagine a situation where the STM network will be replaced overnight with this ATM network.

Therefore, in the process of the spread of ATM networks, ST
It is necessary to have the ability to accommodate the M network. for example,
It is thought that high-speed digital lines in accordance with 5DH (Synchronous Digital Hierarchy) defined by CCIT will penetrate corporate networks in the future, but first, an SDR line network must be set up. A development scenario can be considered in which this SDR line is used in an STM network and the SDR line is migrated to an ATM network as ATM becomes more widespread.

In this case, parts of the network will be converted into an ATM network, and it will be necessary to interconnect with the ATM network or to transfer STM signals using the ATM network as a backbone.

The method for accommodating STM line signals in such an ATM network has only just begun to be studied, and the specific method has not yet been determined.

(Problems to be Solved by the Invention) The present invention aims to propose an STM signal transfer method for transferring STM signals using an ATM network as a backbone, which has not yet been determined as described above.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides broadband ISDN.
In the STM signal transfer method for transmitting STM network signals via the STM signal network, the transmitting side includes means for detecting virtual container frames on the STM signal network, means for generating cells, means for generating sequence numbers, A cell converting unit is provided on the receiving side, comprising means for assigning a predetermined sequence number to a cell corresponding to the beginning of the virtual container frame, and means for adding a dummy pattern to information corresponding to the end of the virtual container frame, and on the receiving side, means for detecting a cell with the predetermined sequence number; means for determining whether a connection has just been established; means for fluctuation compensation; means for detecting continuous cell loss; and means for detecting a cell at the end of a virtual container frame. The present invention is characterized in that a decelling unit is provided, which includes a means for detecting a virtual container frame and a means for outputting a virtual container frame onto an STM signal network.

(Operation) Virtual container frame (VC-
n frames) and the detected vCn frames are converted into cells by, for example, a function that generates cells compliant with CCITT type 1. At the time of cell formation, a sequence number is generated, a predetermined sequence number, for example sequence number 0, is assigned to the cell corresponding to the beginning of VC-n, and the VC-n is
A dummy pattern is added to the information at the end of n.

The cells generated by the above means are transferred to the receiving side via the ATM line.

On the receiving side, a cell with sequence number 0 is detected among the received cells. When a cell with sequence number 0 is detected, it is determined whether the connection has just been established, and if it is determined that the connection has just been established, fluctuation compensation is performed and the VC-n
If a cell at the end of the frame is detected, the dummy pattern in the cell is deleted and a VC-n frame is output. Furthermore, when consecutive cell loss is detected, fluctuation compensation is performed again on the cell with sequence number 0.

(Embodiment) FIG. 1 shows an embodiment of a system configuration using the present invention.

On the transmitting side, first, the STM line termination unit 101 transmits 5O
Terminate H (section overhead) and detect the bus. FIG. 5 shows a bus terminated by the STM line termination section 101. In FIG. 5, POH is bus overhead.

The bus detected by the STM line termination section 101 is manually input to the cell forming section 102 as a bit string. STM line termination section 101
The interface between the cell generator 102 and the cell generator 102 is an 8-bit parallel interface. Furthermore, the cell converting unit 102 receives a frame signal indicating the head of the bus from the STM line termination unit 101 in the bit string.

Taking virtual container frame VC~3 as an example, 1
Since the frame length is 765 bytes and 8 bits are transferred in one transfer, a frame signal is generated once every 765 transfers.

The cell generator 102 continues to discard signals until a frame signal is input at system startup. At the same time that a frame signal is input, cells corresponding to the frame signal begin to be converted into cells. FIG. 2 shows the flow of processing in the cell forming section 102.

The cell forming section 102 generates a cell payload based on the information from the ATV line termination section 101, adds a cell header, and outputs it onto a transmission path. The flow of cell payload generation processing in the cell generator 102 will be explained using FIG. 2.

The cell generator 102 first performs initialization processing. In the initialization process, 8-bit information is detected (step 201), and at the same time it is determined whether the frame signal is rising at the time of detection (step 202).

If the frame signal is rising, 8-bit information is accumulated in a buffer (not shown) of the cell generator 102 (step 20B), the sequence number (control variable) is set to 1, and the frame detection flag (control variable) is set. 1 and set the storage amount to 1 (step 204), completes the initialization process, and waits for the next 8 bits to be input (step 204).
Step 205).

Note that if the frame signal has not risen in step 202, the 8-bit information is discarded.

After the initialization process is completed, the cell payload generation process is started.

In the cell payload generation process, 8-bit information is accumulated in a buffer (not shown) of the cell generator 102.

Here, writing to the buffer is done in a contiguous area,
The pointer in the buffer shall be automatically incremented.

FIG. 6 shows an example of a self-format generated by the cell payload generation process. In FIG. 6, GFC is a generic flow control, VPI is a Verticel bus identifier, VCI is a Verticel connection identifier,
HEC is a header error check, and 5ARH is a cell disassembly/assembly header. Further, FIG. 6(a) shows a case where a dummy pattern, which will be described later, is not used, and FIG. 6(b) shows a case where a dummy pattern is used.

In the cell payload generation process, the STM line termination section 101
8-bit information is manually input (step 207), and it is determined whether the frame detection signal is rising (step 208).

When the frame signal is rising, first, the information remaining in the buffer is converted into cells and output.

In other words, a dummy pattern is added to the information in the buffer that is less than 47 bytes to make it 47 bytes, and as 5ARH,
A sequence number and its error correction code are added to generate a cell payload (step 209). The sequence number and error correction code that make up 5ARH are each 4 bits, and 5ARH is set at the beginning of the information in the buffer. After adding a cell header to the cell payload thus generated and generating a cell, the cell is output to the transmission path (step 210). And after outputting the cell,
The sequence number is updated (step 211).

The sequence number is updated based on the following formula.

5eql -5eq mod 15) +l...
- (1) where seq is the current sequence number and eql is the new sequence number.

This will clear the information left in the buffer.

After clearing the information remaining in the buffer, a new frame is received. In this way, by converting information less than 47 bytes into cells each time the beginning of a frame is detected, the signal corresponding to the beginning of the frame can always occupy the beginning position in the cell payload.

Step 2 is performed as cell processing for a new frame.
Following step 11, the 8 bits manually input are written into the buffer (step 212), the frame detection flag is set to 1, and the storage amount is set to 1 (step 213).

The process waits for 8 bits of the extraction method (step 214), and repeats the processing from step 207.

If the frame signal has not risen in step 208, the 8 bits manually generated are written into the buffer and 1 is added to the accumulated amount (step 215).

Next, it is determined whether the buffer storage amount has reached 47 (step 216), and if the storage amount has not reached 47, it waits for the next 8 bits (step 217), and step 207
Repeat the process from.

If the accumulated amount of the buffer reaches 47, it is determined whether the frame detection flag is set (step 218).
).

Here, if the frame detection flag is set, sequence number 0 and an error correction code for the sequence number are set as S'A RH, and a cell payload is generated (step 219).

Thereafter, a cell header is added to this cell payload and output (step 220).

After outputting this cell, reset the frame detection flag to O,
Clear the accumulated amount to 0 (step 221), wait for the next 8 bits (step 223), and repeat the process from step 207.

If the frame detection flag is reset in step 218, the sequence number and its error correction code are set as 5ARH, and a cell payload is generated (step 224). Then, a cell header is added to this cell payload, and a cell is generated and output (step 225).
.

After outputting the cells, the accumulated amount is cleared to 0 and the sequence number is updated (step 226). The sequence number is updated according to the above-mentioned equation (1).

After updating the sequence number, wait for the next 8 bits (step 227) and repeat the process from step 207.

Next, the operation on the receiving side will be explained.

On the receiving side, the VC-n frame structure is restored from the cell payload in the cell stream received from the transmission path and output to the STM line termination section 104. Decellation unit 103 and STM
Similarly to the interface between the cell forming section 102 and the STM line termination section 101, the interface with the line termination section 104 is composed of an 8-bit parallel signal line and a frame signal.

The processing in the decelling section 103 consists of cell reception processing and cell payload decomposition processing.

The cell reception process also includes an initialization process, which is activated first, and this reception process activates the cell payload decomposition process. The cell reception process and the cell payload disassembly process are coupled by a queue, the cell reception process writes the cell payload to the queue, and the cell payload disassembly process reads it.

An overview of cell reception processing will be explained using FIG. 3.

In cell reception processing, initialization processing is performed at startup or when an out-of-synchronization occurs. In the initialization process, the cell header of the received cell is checked (step 3).
01), if an error is detected, discard this cell.Step 302), wait for the next cell (step 303), and repeat the process from step 301.If there is no error, detect the cell payload and discard the cell. Detects the 5ARH set in the first byte of the payload, that is, the 4-bit sequence number and its 4-bit error correction code (
Step 304).

Next, it is determined whether error correction is possible using the error correction code (step 305), and if correction is not possible, the cell is discarded (step 302), and the next cell is waited (step 303), and step 301 Repeat the process from.

If it can be corrected, the cell payload is accepted and it is determined whether the sequence number is 0 (step 306). If the sequence number is not 0, discard the cell (step 302) and wait for the next cell (step 3).
03), repeat the process from step 301. Also,
If the sequence number is 0, write the cell payload to the queue and set the timer (step 307);
Wait for the next cell (step 308). At this stage, the initialization processing is completed and regular cell reception processing is performed.

In regular cell reception processing, following step 308, the cell header is checked every time a cell is received (
309), if there is an error, discard the cell (step)
, the process from step 308 is repeated. If there is no error in the cell header, it is checked whether there is an error in the sequence number in the cell payload (step 311).

If there is an error in the sequence number, the cell payload is discarded (step 310) and the process from step 308 is repeated. If there is no error in the sequence number, the cell payload is written to the queue (step 312), and the processing from step 308 is repeated.

Next, the cell payload disassembly process will be explained using FIG. 4.

The cell payload decomposition process is activated by the timeout of the timer activated by the decellization unit 103 in the initialization process. After the cell payload disassembly process is started, step 40 reads the cell payload from the head of the queue.
1), 8, which is the second byte from the beginning of the cell payload
The frame detection signal is set while outputting the bi-soto signal (step 402).

After outputting the frame detection signal, set the shift variable to 2, the number of output bytes to 1, and the predicted sequence number (control variable) to 1 (step 403), and wait for the next output timing (step 404).

Then, at the next output timing, if the frame detection signal is set, the frame detection signal is reset, and the 1-byte information located at the position shifted from the beginning by the contents of the shift variable in the cell payload ST
The signal is output to the M terminal section 104 (step 405).

After outputting one byte of information, the number of output bytes is incremented by 1 (step 406), and it is determined whether the number of output bytes is equal to one frame length (step 407).

If the number of output bytes is equal to one frame length, find the next cell payload in the queue and check if the sequence number is equal to 0 (step 408). If they are equal, wait for the next output timing (step 40).
9). When the next output timing comes, 1 byte of information located at the 2nd byte in the cell payload is output to the STM line termination unit 104 (step 410), the shift variable is set to 2, the number of output bytes is set to 1, The process from step 404 is repeated.

If the sequence number is not equal to 0 as determined in step 408, it is assumed that a continuous loss of undetectable cells has occurred, and the cell reception process is restarted from the initialization process to restart the decelling process (step 411
).

If it is determined in step 407 that the number of output bytes is different from the frame length, it is determined whether the value of the shift variable is equal to 47 (step 412). If the value of the shift variable is equal to 47, the next cell payload in the queue is read (step 413), and it is determined whether the sequence number in the cell payload matches the predicted sequence number (step 414). If they match, the shift variable is set to 1 and the predicted sequence number is updated (step 415), and the process from step 404 is repeated. The predicted sequence number is updated using the formula (1) used on the sending side.
This is done using

If the sequence number in the cell payload is different from the predicted sequence number, it is determined whether the sequence number in the cell payload is within the window (step 416). Whether the sequence number in the cell payload is within the window is determined by whether it is included in the seven sequence numbers starting with the predicted sequence number. for example,
If the predicted sequence number is 12, the sequence number in the received cell payload is 12.13.14.
．． 15.1.2.3, it is considered to be inside the window; otherwise, it is considered to be outside the window.

If it is determined that the cell is within the window, it is assumed that the cell corresponding to the predicted sequence number is missing, the read cell payload is returned to the head of the queue, and the fixed pattern is used as the cell payload in place of the missing cell (step 417 ). Furthermore, the value of the shift variable is set to 1, and the predicted sequence number is updated (step 415).
, repeats the process from step 404.

If it is determined in step 416 that the cell is outside the window, it is assumed that the cell did not arrive in time for the predetermined timing due to an increase in the delay time within the network, and the cell payload is discarded (step 419), and the processing from step 413 is performed. repeat.

If it is determined in step 412 that the shift variable is not equal to 47, 1 is added to the shift variable (step 418), and the processing from step 404 is repeated.

In the above embodiment, sequence number 0 is assigned to the cell corresponding to the beginning of VC-n, but a similar configuration can be made even if a predetermined sequence number other than sequence number 0 is assigned.

〔Effect of the invention〕

As explained above, according to the present invention, by realizing the function of converting VC-n frames on an SDR line into cells, it is possible to transfer STM signals via an ATM network. have

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing one embodiment of the present invention, FIG. 2 is a flowchart showing the flow of processing in the cellization processing section of this embodiment, and FIG. 3 is a system configuration diagram showing an embodiment of the present invention. 4 is a flowchart showing the flow of the cell payload decomposition process in the decellization processing unit of this embodiment. FIG. 5 is a diagram showing an example of the terminal bus of this embodiment. The figure shows the self-automatic data generated by the decellation processing section of this embodiment. 101... STM line termination section, 102... Cell forming section, 103... Decell forming section, 104... STM line line termination acid FIG.

Claims (1)

[Claims] ST that transfers STM network signals via broadband ISDN
In the M signal transfer method, the transmitting side includes: a means for detecting a virtual container frame on the STM signal network; a means for generating a cell; a means for generating a sequence number; and a cell corresponding to the beginning of the virtual container frame. The receiving side is provided with a cell generator including means for allocating a predetermined sequence number and means for adding a dummy pattern to information at the end of the virtual container frame, and the receiving side detects a cell having the predetermined sequence number. a means for determining whether a connection has just been established; a means for fluctuation compensation; a means for detecting continuous cell loss; a means for detecting a cell at the end of a virtual container frame; An STM characterized in that a decelling unit is provided with a means for outputting a virtual container frame.
Signal transfer method.