JPH04135308A - Hilbert transforming unit due to time region processing - Google Patents
Hilbert transforming unit due to time region processingInfo
- Publication number
- JPH04135308A JPH04135308A JP25796090A JP25796090A JPH04135308A JP H04135308 A JPH04135308 A JP H04135308A JP 25796090 A JP25796090 A JP 25796090A JP 25796090 A JP25796090 A JP 25796090A JP H04135308 A JPH04135308 A JP H04135308A
- Authority
- JP
- Japan
- Prior art keywords
- hilbert
- lsi
- transforming unit
- outputs
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001131 transforming effect Effects 0.000 title abstract 2
- 238000005070 sampling Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 2
- 230000001364 causal effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Complex Calculations (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は時間域処理によるヒルベルト変換器に係る。[Detailed description of the invention] The present invention relates to a Hilbert transformer with time domain processing.
従来からヒルベルト変換器は全域通過回路網、直角移相
器々どと呼ばれ周波数領域で扱われてきた。この場合構
成される回路中のりアクタンス素子の値が比較的大きく
なるため回路のIC化は困難となる。Conventionally, Hilbert transformers have been called all-pass networks, quadrature phase shifters, etc., and treated in the frequency domain. In this case, the value of the actance element in the constructed circuit becomes relatively large, making it difficult to integrate the circuit.
本発明はヒルベルト変換器のLSI(大規模集積回路)
による実現を目的とするもので、これにより更に5SB
−8C(搬送波抑圧単側波帯方式)の変調回路のLSI
化を可能ならしめようとするものである。The present invention is a Hilbert converter LSI (Large Scale Integrated Circuit)
The aim is to realize this by increasing the number of 5SB.
-8C (carrier suppression single sideband method) modulation circuit LSI
The aim is to make this possible.
上記目的を達成するため本発明においては、信号をディ
ジタル化し論理回路によって実時間処理する方式が採用
される。論理回路は容易にLSIによって製作できるの
で時間域処理によるヒルベルト変換器はLSI化され得
ることとなる。In order to achieve the above object, the present invention employs a method in which signals are digitized and processed in real time by a logic circuit. Since a logic circuit can be easily manufactured using an LSI, a Hilbert transformer based on time domain processing can be implemented as an LSI.
本発明の目的および特長は以下の図面を参照した実施例
説明より明らかとなろう。The objects and features of the present invention will become clear from the description of the embodiments with reference to the following drawings.
因果性をもつ信号m(1)のヒルベルト変換m(1)は
次の積分で与えられる。The Hilbert transform m(1) of the causal signal m(1) is given by the following integral.
m(t)−fo(m(u)/7r(t u))du=
、f o (m (tu )/ffu ) du・・・
・・・・・・・・(1)
この式において時間tを離散化する際tく1のとき積分
値は非常に大きくtの影響を受けるので信号m(1)の
ナイキスト間隔を時間lとするとき実際の標本化クロッ
クを例えば01とし、 離散時間■と書けば式(1)は
、
m(■)−〇、1o=1Σm (I−0,1n ) 1
0. 1 n T
=nだ、Σm (1−0,L n ) /n 1r・・
・・・・・・・(2)
但し、標本値の個数Nは100とすれば十分である。そ
れは式(2)の分母はn = 1のときT。m(t)−fo(m(u)/7r(t u))du=
, f o (m (tu)/ffu) du...
・・・・・・・・・(1) In this equation, when the time t is discretized, the integral value is very greatly influenced by t when t×1, so the Nyquist interval of the signal m(1) is set as the time l. For example, if the actual sampling clock is 01 and the discrete time ■ is written, then equation (1) becomes m(■)-〇, 1o=1Σm (I-0,1n) 1
0. 1 n T = n, Σm (1-0, L n ) /n 1r...
(2) However, it is sufficient to set the number N of sample values to 100. That is, the denominator of equation (2) is T when n = 1.
=100のとき100′Irであり、信号の因果性によ
りl<0.1nなるnに対してはm(Io−tn)=0
であることによる。= 100, it is 100'Ir, and due to the causality of the signal, for n where l<0.1n, m(Io-tn) = 0
By being.
式(2)に基づきヒルベルト変換器の回路構成は第1図
のようになる。図において1は入力端子で、これにA/
D変換器によってディジタル化された信号m(1)が加
えられると、これはN個の素子からなるシフトレジスタ
21,22゜2Nに導かれる。シフトレジスタには信号
のシフトのための0,1間隔のクロック・パルスが加え
られていて、それらの素子からそれぞれ出力m(1−0
,1)、m(1−0,2)、 −−、m(1−0、
I N )が出され、これらにまたそれぞれ係数乗算器
31,32.・・・、3Nによって係数に□/′Ir、
k /2′I′r、・・・、kN/N′Irがそれぞれ
乗ぜられる。但し、k、、に2. 、kNは補
正値とする。それらの結果は全て加算器4に導かれて加
算され、出力端子5に出力される。かくして端子5から
近似的なヒルベルト変換出力m(1)のディジタル信号
が得られる。Based on equation (2), the circuit configuration of the Hilbert transformer is as shown in FIG. In the figure, 1 is the input terminal, and A/
When the signal m(1) digitized by the D-converter is applied, it is guided to a shift register 21, 22.degree. 2N consisting of N elements. Clock pulses at intervals of 0 and 1 are applied to the shift register for signal shifting, and each of these elements outputs m(1-0
,1),m(1-0,2), --,m(1-0,
I N ), which are also supplied with coefficient multipliers 31, 32 . ..., 3N makes the coefficient □/'Ir,
k/2'I'r, . . . , kN/N'Ir are respectively multiplied. However, k, 2. , kN are correction values. All of these results are led to adder 4, added, and output to output terminal 5. In this way, a digital signal with an approximate Hilbert transform output m(1) is obtained from the terminal 5.
第1図の回路構成はその壕ま−まとめにLSIとして作
製可能である。The circuit configuration shown in FIG. 1 can be fabricated in its entirety as an LSI.
以上説明したとおり、本発明のヒルベルト変換器によれ
ばLSIの特長である小型、軽量、低消費電力、長寿命
、かつ安価にそれが実現できるという利益がある。As explained above, the Hilbert converter of the present invention has the advantage of being able to realize the characteristics of LSI, such as small size, light weight, low power consumption, long life, and low cost.
第1図は時間域処理によるヒルベルト変換器の構成略図
である。
1:ディジタル化された信号の入力端子21、・・・、
2N=シフトレジスタ素子31、・・・、3N:係数乗
算器FIG. 1 is a schematic diagram of the configuration of a Hilbert transformer using time domain processing. 1: Digitized signal input terminal 21,...
2N=Shift register element 31,..., 3N: Coefficient multiplier
Claims (1)
隔でその信号をディジタル化したのち多数個の素子から
なるシフトレジスタに導き、それら素子の出力にそれぞ
れ適当な係数を乗じて加算することによシ近似的にヒル
ベルト変換を実現するヒルベルト変換器。A signal can be approximated by digitizing the signal at the Nyquist interval or a sampling interval narrower than that, leading it to a shift register consisting of many elements, and multiplying the outputs of these elements by appropriate coefficients and adding them. A Hilbert transformer that realizes the Hilbert transform in a practical manner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25796090A JPH04135308A (en) | 1990-09-27 | 1990-09-27 | Hilbert transforming unit due to time region processing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25796090A JPH04135308A (en) | 1990-09-27 | 1990-09-27 | Hilbert transforming unit due to time region processing |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04135308A true JPH04135308A (en) | 1992-05-08 |
Family
ID=17313603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25796090A Pending JPH04135308A (en) | 1990-09-27 | 1990-09-27 | Hilbert transforming unit due to time region processing |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04135308A (en) |
-
1990
- 1990-09-27 JP JP25796090A patent/JPH04135308A/en active Pending
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